import pmbus_csr_pkg :: *;

module pmbus_csr
#(
parameter AW = 32,
parameter DW = 32
)
(
// Clock and Reset
input logic clk,
input logic rst_n,

//AXI Interface
input logic awvalid,
input logic [AW-1:0] awaddr,
input logic [3:0] awlen,
input logic [2:0] awsize,
output logic awready,

//
input logic wvalid,
input logic [DW-1:0] wdata,
output logic wready,

output logic bvalid,

input logic bready,
output logic [1:0] bresp,

input logic arvalid,

input logic [AW-1:0] araddr,
input logic [3:0] arlen,
input logic [2:0] arsize,
output logic arready,

output logic [1:0] rresp, // read responce

output logic rvalid,
output logic [DW-1:0] rdata,
input logic rready,

input reg_ro_port_list in_port_list,

output reg_rw_port_list out_port_list,

// CSR CMD LUT Interface

output logic cmd_lut_0_wr_en_o,
output logic [AW-1:0] cmd_lut_0_wr_addr_o,
output logic cmd_lut_1_wr_en_o,
output logic [AW-1:0] cmd_lut_1_wr_addr_o,

output logic cmd_lut_0_rd_en_o,

output logic [AW-1:0] cmd_lut_0_rd_addr_o,
output logic cmd_lut_1_rd_en_o,
output logic [AW-1:0] cmd_lut_1_rd_addr_o,

output logic [DW-1:0] cmd_lut_x_data_o,

input logic [DW-1:0] cmd_lut_0_rd_data_i,
input logic [DW-1:0] cmd_lut_1_rd_data_i,

// FSM CMD LUT Interface

input logic [AW-1:0] hw_cmd_lut_rd_addr_i,
 input logic hw_cmd_lut_rd_req_i,
output logic [DW-1:0] hw_cmd_lut_rd_data_o,
output logic hw_cmd_lut_rd_ack_o,

output logic fast_int,

output logic norm_int
);

//Register Address parameters

localparam C0_PMBUS_CTRL0_ADDRESS = 16'd0000;
localparam C0_PMBUS_CTRL1_ADDRESS = 16'd0004;
localparam C0_PMBUS_CTRL2_ADDRESS = 16'd0008;
localparam C0_PMBUS_CTRL3_ADDRESS = 16'd0012;
localparam C0_PMBUS_ADDR_CTRL0_ADDRESS = 16'd0024;
localparam C0_PMBUS_ADDR_CTRL1_ADDRESS = 16'd0028;
localparam C0_PMBUS_ADDR_CTRL2_ADDRESS = 16'd0032;
localparam C0_PMBUS_ADDR_CTRL3_ADDRESS = 16'd0036;
localparam C0_PMBUS_STS0_ADDRESS = 16'd0040;
localparam C0_PMBUS_ERR_STS0_ADDRESS = 16'd0044;
localparam C0_PMBUS_STS1_ADDRESS = 16'd0048;
localparam C0_PMBUS_ERR_STS1_ADDRESS = 16'd0052;
localparam C0_PMBUS_RX_DBUF_ADDRESS = 16'd0064;
localparam C0_PMBUS_TX_BUF_ADDRESS = 16'd0084;
localparam C0_PMBUS_ACK_CTRL_ADDRESS = 16'd0096;
localparam C0_PMBUS_INT_MASK_CTRL_ADDRESS = 16'd0100;
localparam C0_PMBUS_CLK_LOW_TO_ADDRESS = 16'd0104;
localparam C0_RAIL_ENABLE_ADDRESS = 16'd0112;
localparam C0_PHASE_ENABLE_ADDRESS = 16'd0116;
localparam C0_PARTITION_ENABLE_ADDRESS = 16'd0120;

//wire/reg/logic declartion

//write signals
logic write_b;
logic reg_write;
logic [AW-1:0] reg_write_address;

//read signals
logic reg_read_csr;
logic reg_read_csr_d;
logic rvalid_csr;
//logic rvalid_d;
logic [AW-1:0] reg_read_address;

logic rvalid_csr_d;
logic rvalid_cmdlut_d;
logic rvalid_tmp;
//logic rvalid_o;

//cmd lut
logic hw_cmd_lut_0_rd_en;
logic hw_cmd_lut_1_rd_en;
logic hw_cmd_lut_0_rd_en_d;
logic hw_cmd_lut_1_rd_en_d;
logic hw_cmd_lut_x_rd_en;
logic cmd_lut_0_rd_en_o_d;
logic cmd_lut_1_rd_en_o_d;

///////////////////////////////////////////////////////////////////////////////////
////////////
/// write transfer enable
reg write_en;
always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n)begin
write_en <= 0;
end
else if(awready)begin
write_en <=1'b1;
end else if(bvalid && bready)
write_en <=1'b0;
end
// Write Address Channel Handshake
always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
awready <= 0;
end
else begin
// if(awvalid && !awready)
awready <= awvalid && !awready && !write_en;//1'b1;
end
end

// Write Data Channel Handshake

always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
wready <= 0;
end
else begin
wready <= wvalid && !wready;
end
end

/// read transfer enable

reg read_en;
always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n)begin
read_en <= 0;
end
else if(arready)begin
read_en <=1'b1;
end else if(rvalid)
read_en <=1'b0;
end
///read addr handshake
always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n)begin
arready <= 0;
end
else begin
arready <=arvalid && !arready && !read_en;
end
end
//----temp logic for axi read valid---
always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
rvalid_csr <= 0;
 end
else if (arready && !hw_cmd_lut_x_rd_en) begin
rvalid_csr <= 1;
end
else begin
rvalid_csr <= 0;
end
end

//--when axi wants to read RX FIFO, rvalid needs to be delayed due to data path
delay
/*always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
rvalid_d <= 0;
end
else begin
rvalid_d <= rvalid_csr && (reg_read_address == C0_PMBUS_RX_DBUF_ADDRESS);
end
end*/

//--- Align all valid signals with rdata by delaying them one cycle ---
always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
rvalid_csr_d <= 0;
rvalid_cmdlut_d <= 0;
end
else begin
rvalid_csr_d <= rvalid_csr;
rvalid_cmdlut_d <= rvalid_csr_d;
end
end
assign cmdlut_en = ((reg_read_address[11:0] >= 12'h800) && (reg_read_address[11:0]
<= 12'hFFC) || (reg_read_address[11:0] == 12'h40));

//--- Combine delayed CSR & cmdlut valid

assign rvalid_tmp = cmdlut_en ? rvalid_csr_d : rvalid_csr;

//assign rvalid = rvalid_csr_d;

//--- Final aligned rvalid signal (one cycle delayed to match rdata)
// assign rvalid_o = (reg_read_address == C0_PMBUS_RX_DBUF_ADDRESS) ? rvalid_d :
rvalid_tmp;

//lc assign rvalid_o = (reg_read_address == C0_PMBUS_RX_DBUF_ADDRESS) ?

rvalid_csr_d : rvalid_tmp;

always_ff @(posedge clk or negedge rst_n) begin

if (!rst_n) begin
rvalid <= 0;
end
else if (rvalid && !rready) begin
rvalid <= rvalid;
end
else begin
//rvalid <= rvalid_o;
rvalid <= rvalid_tmp;
end
 end

//pulse creation for write transaction when wvalid comes

always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
write_b<=0;
end
else if (wvalid) begin
write_b <= 1;
end
else begin
write_b <=0;
end
end

assign reg_write = wvalid && write_b;

//assign reg_write = write_b;
//axi write address stored in temp register
always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
reg_write_address <= 32'd0;
end
else if(awvalid) begin
reg_write_address <= awaddr;
end
end

//axi read address stored in temp register

always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
reg_read_address <= 32'd0;
end
else if(arvalid) begin
reg_read_address <=araddr;
end
end

// Read transaction state tracking

always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
reg_read_csr <= 1'b0;
end
// else if (arvalid && arready) begin
else if(arready)begin
reg_read_csr <= 1'b1;
end
else if (rvalid && rready) begin
reg_read_csr <= 1'b0;
end
end

// Read transaction delayed version for rx data buffer

always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
reg_read_csr_d <= 1'b0;
end
else begin
reg_read_csr_d <= reg_read_csr;
 end
end

assign reg_read = (reg_read_address == C0_PMBUS_RX_DBUF_ADDRESS) ?

reg_read_csr_d : reg_read_csr;

////////////////////////// error condition for address mismatch

function logic is_valid_csr_addr(input logic [15:0] addr);

if (addr[1:0] != 2'b00)
return 1'b0;

// predefined CSR addresses

case (addr)
16'd0000, 16'd0004, 16'd0008, 16'd00012,
16'd0024, 16'd0028, 16'd0032, 16'd0036,
16'd0040, 16'd0044, 16'd0048, 16'd0052,
16'd0064, 16'd0084, 16'd0096, 16'd0100,
16'd0104, 16'd0112, 16'd0116, 16'd0120:
return 1'b1;
default: begin
// Allow address range 0x0800 to 0x0BFC
if (addr >= 16'h0800 && addr <= 16'h0BFC && addr[1:0] == 2'b00)
return 1'b1;
// Allow address range 0x0C00 to 0x0FFC
else if (addr >= 16'h0C00 && addr <= 16'h0FFC && addr[1:0] == 2'b00)
return 1'b1;
else //if(!bready)
return 1'b0;
end
endcase
endfunction
//
logic addr_valid;

always_ff @(posedge clk or negedge rst_n) begin

if (!rst_n) begin
addr_valid <= 32'b0;
end else
addr_valid <= is_valid_csr_addr(reg_write_address[15:0]);
end

////////////////write responce
logic [1:0] bresp_reg;
logic bvalid_reg;
always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
bresp_reg <= 2'b00;
bvalid_reg <= 1'b0;
end else begin
if (reg_write) begin
if (!is_valid_csr_addr(reg_write_address[15:0])) begin
bresp_reg <= 2'b11; // DECERR
end else begin
bresp_reg <= 2'b00; // OKAY
end
bvalid_reg <= 1'b1;
end else if (bvalid_reg && bready) begin
// Response accepted by master
 bvalid_reg <= 1'b0;
bresp_reg <= 2'b0;
end
end
end

assign bresp = bresp_reg;

assign bvalid = bvalid_reg;
//////////////////read responce

logic [1:0]rresp_reg;
always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
rresp_reg <= 2'b00;
end
if (reg_read) begin
if (!is_valid_csr_addr(reg_read_address[15:0])) begin
rresp_reg <= 2'b11; // DECERR
end else begin
rresp_reg <= 2'b00; // OKAY
end
end else
rresp_reg <= 2'b0;
end
assign rresp = rvalid ? rresp_reg : 2'b0;

// CMD LUT Read Interface//

always_comb begin
// Default values
cmd_lut_0_rd_en_o = 1'b0;
cmd_lut_0_rd_addr_o = 32'd0;
cmd_lut_1_rd_en_o = 1'b0;
cmd_lut_1_rd_addr_o = 32'd0;

hw_cmd_lut_0_rd_en = 1'b0;
hw_cmd_lut_1_rd_en = 1'b0;

// Read by FW (via AXI) TODO: add semaphore later

if (reg_read) begin
//------normal command lut---------
if ((reg_read_address[11:0] >= 12'h800) && (reg_read_address[11:0] <=
12'hBFC)) begin
cmd_lut_0_rd_en_o = 1'b1;
cmd_lut_0_rd_addr_o = reg_read_address;
end
//---extended command lut -----
else if ((reg_read_address[11:0] >= 12'hC00) && (reg_read_address[11:0] <=
12'hFFC)) begin
cmd_lut_1_rd_en_o = 1'b1;
cmd_lut_1_rd_addr_o = reg_read_address;
end
end
// Read by HW (from PMBus FSM)
else if (hw_cmd_lut_rd_req_i) begin
//------normal command lut---------
if ((hw_cmd_lut_rd_addr_i[11:0] >= 12'h800) && (hw_cmd_lut_rd_addr_i[11:0] <=
12'hBFC)) begin
cmd_lut_0_rd_en_o = 1'b1;
cmd_lut_0_rd_addr_o = hw_cmd_lut_rd_addr_i;
 hw_cmd_lut_0_rd_en = 1'b1;
end
//---extended command lut -----
else if ((hw_cmd_lut_rd_addr_i[11:0] >= 12'hC00) &&
(hw_cmd_lut_rd_addr_i[11:0] <= 12'hFFC)) begin
cmd_lut_1_rd_en_o = 1'b1;
cmd_lut_1_rd_addr_o = hw_cmd_lut_rd_addr_i;
hw_cmd_lut_1_rd_en = 1'b1;
end
end
end

// CMD LUT Write Interface

always_comb begin
cmd_lut_0_wr_en_o = 1'b0;
cmd_lut_1_wr_en_o = 1'b0;
cmd_lut_0_wr_addr_o = 32'b0;
cmd_lut_1_wr_addr_o = 32'b0;

if (reg_write) begin
if ((reg_write_address[11:0] >= 12'h800) && (reg_write_address[11:0] <=
12'hBFC)) begin
cmd_lut_0_wr_en_o = 1'b1;
cmd_lut_0_wr_addr_o = reg_write_address;
cmd_lut_x_data_o = wdata;//wvalid ? wdata : 32'b0;
end
else if ((reg_write_address[11:0] >= 12'hC00) && (reg_write_address[11:0] <=
12'hFFC)) begin
cmd_lut_1_wr_en_o = 1'b1;
cmd_lut_1_wr_addr_o = reg_write_address;
cmd_lut_x_data_o = wdata;//wvalid ? wdata : 32'b0;
end
end
end

always_ff @(posedge clk or negedge rst_n) begin

if (!rst_n) begin
hw_cmd_lut_0_rd_en_d <= 1'b0;
hw_cmd_lut_1_rd_en_d <= 1'b0;
end
else begin
hw_cmd_lut_0_rd_en_d <= hw_cmd_lut_0_rd_en;
hw_cmd_lut_1_rd_en_d <= hw_cmd_lut_1_rd_en;
end
end

assign hw_cmd_lut_rd_data_o = (hw_cmd_lut_0_rd_en_d) ? cmd_lut_0_rd_data_i :

(hw_cmd_lut_1_rd_en_d) ? cmd_lut_1_rd_data_i : 32'd0;
assign hw_cmd_lut_rd_ack_o = (hw_cmd_lut_0_rd_en_d | hw_cmd_lut_1_rd_en_d);
assign hw_cmd_lut_x_rd_en = (hw_cmd_lut_0_rd_en | hw_cmd_lut_1_rd_en);

///////////////////////////////////////////////////////////////////////////////////
//////////
//\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
\\\\\\\\\
//WRITE LOGIC
//write logic for register c0_pmbus_ctrl0
logic [31:0] c0_pmbus_ctrl0;
logic [3:0] c0_pmbus_ctrl0_alert_en_vld;
localparam C0_PMBUS_CTRL0_RESERVED_MASK = 32'h3730_0ff7;

always_ff @(posedge clk or negedge rst_n) begin

if (!rst_n) begin
c0_pmbus_ctrl0 <= { 2'h0, 2'h0, 1'h0, 3'h0, 2'h0, 1'h0, 1'h0, 8'h0, 1'h0,
1'h0, 1'h0, 1'h0, 1'h0, 1'h0, 1'h0, 1'h0, 1'h0, 1'h0, 1'h0, 1'h0 };
c0_pmbus_ctrl0_alert_en_vld <= 4'b0;
end
else if ((reg_write_address == C0_PMBUS_CTRL0_ADDRESS) && reg_write) begin
c0_pmbus_ctrl0_alert_en_vld <= {wdata[7:4]};

case(awsize)
3'b000: c0_pmbus_ctrl0 <= {c0_pmbus_ctrl0[31:8], wdata[7:0]} &
C0_PMBUS_CTRL0_RESERVED_MASK;// 1 byte
3'b001: c0_pmbus_ctrl0 <= {c0_pmbus_ctrl0[31:16], wdata[15:0]} &
C0_PMBUS_CTRL0_RESERVED_MASK;// 2 byte
3'b010: c0_pmbus_ctrl0 <= {wdata[31:0]} &
C0_PMBUS_CTRL0_RESERVED_MASK;// 4 byte
endcase
end
else begin
c0_pmbus_ctrl0[4] <= ~in_port_list.c0_pmbus_ctrl0_clr_alert_en[0] &
c0_pmbus_ctrl0[4];
c0_pmbus_ctrl0[5] <= ~in_port_list.c0_pmbus_ctrl0_clr_alert_en[1] &
c0_pmbus_ctrl0[5];
c0_pmbus_ctrl0[6] <= ~in_port_list.c0_pmbus_ctrl0_clr_alert_en[2] &
c0_pmbus_ctrl0[6];
c0_pmbus_ctrl0[7] <= ~in_port_list.c0_pmbus_ctrl0_clr_alert_en[3] &
c0_pmbus_ctrl0[7];
c0_pmbus_ctrl0_alert_en_vld <= 4'b0;
end
end

assign out_port_list.c0_pmbus_ctrl0_pmbus_ctrl_en = c0_pmbus_ctrl0[0];

assign out_port_list.c0_pmbus_ctrl0_sgl_multi_dev_addr = c0_pmbus_ctrl0[1];
assign out_port_list.c0_pmbus_ctrl0_pec_en = c0_pmbus_ctrl0[2];
assign out_port_list.c0_pmbus_ctrl0_alert_en0 = c0_pmbus_ctrl0[4];
assign out_port_list.c0_pmbus_ctrl0_alert_en1 = c0_pmbus_ctrl0[5];
assign out_port_list.c0_pmbus_ctrl0_alert_en2 = c0_pmbus_ctrl0[6];
assign out_port_list.c0_pmbus_ctrl0_alert_en3 = c0_pmbus_ctrl0[7];
assign out_port_list.c0_pmbus_ctrl0_alert_auto = c0_pmbus_ctrl0[8];
assign out_port_list.c0_pmbus_ctrl0_alert_en_vld =
c0_pmbus_ctrl0_alert_en_vld;
assign out_port_list.c0_pmbus_ctrl0_zone_en = c0_pmbus_ctrl0[9];
assign out_port_list.c0_pmbus_ctrl0_zone_wr_act = c0_pmbus_ctrl0[10];
assign out_port_list.c0_pmbus_ctrl0_zone_rd_act = c0_pmbus_ctrl0[11];
assign out_port_list.c0_pmbus_ctrl0_zdht_en = c0_pmbus_ctrl0[20];
assign out_port_list.c0_pmbus_ctrl0_nack_for_bsy = c0_pmbus_ctrl0[21];
assign out_port_list.c0_pmbus_ctrl0_page_no =
c0_pmbus_ctrl0[26:24];
assign out_port_list.c0_pmbus_ctrl0_page_no_def =
c0_pmbus_ctrl0[29:28];
//write logic for register c0_pmbus_ctrl1
logic [31:0] c0_pmbus_ctrl1;
localparam C0_PMBUS_CTRL1_RESERVED_MASK = 32'hff7d_f7df;

always_ff @(posedge clk or negedge rst_n) begin

if (!rst_n)
c0_pmbus_ctrl1 <= { 8'h0, 1'h0, 5'h0, 1'h0, 5'h0, 1'h0, 5'h0, 1'h0,
5'h0 };
else if ((reg_write_address == C0_PMBUS_CTRL1_ADDRESS) && reg_write) begin

case(awsize)
3'b000: c0_pmbus_ctrl1 <= {c0_pmbus_ctrl1[31:8], wdata[7:0]} &
C0_PMBUS_CTRL1_RESERVED_MASK;// 1 byte
3'b001: c0_pmbus_ctrl1 <= {c0_pmbus_ctrl1[31:16], wdata[15:0]} &
C0_PMBUS_CTRL1_RESERVED_MASK;// 2 byte
3'b010: c0_pmbus_ctrl1 <= {wdata[31:0]} &
C0_PMBUS_CTRL1_RESERVED_MASK;// 4 byte
endcase
end
end

assign out_port_list.c0_pmbus_ctrl1_phase_no_pg0 = c0_pmbus_ctrl1[4:0];

assign out_port_list.c0_pmbus_ctrl1_phase_no_pg1 = c0_pmbus_ctrl1[10:6];
assign out_port_list.c0_pmbus_ctrl1_phase_no_pg2 =
c0_pmbus_ctrl1[16:12];
assign out_port_list.c0_pmbus_ctrl1_phase_no_pg3 =
c0_pmbus_ctrl1[22:18];
assign out_port_list.c0_pmbus_ctrl1_sw_reset_vec =
c0_pmbus_ctrl1[31:24];

//write logic for register c0_pmbus_ctrl2

logic [31:0] c0_pmbus_ctrl2;
localparam C0_PMBUS_CTRL2_RESERVED_MASK = 32'hffff_ffff;

always_ff @(posedge clk or negedge rst_n) begin

if (!rst_n)
c0_pmbus_ctrl2 <= { 8'h0, 8'h0, 8'h0, 8'h0 };
else if ((reg_write_address == C0_PMBUS_CTRL2_ADDRESS) && reg_write) begin

case(awsize)
3'b000: c0_pmbus_ctrl2 <= {c0_pmbus_ctrl2[31:8], wdata[7:0]} &
C0_PMBUS_CTRL2_RESERVED_MASK;// 1 byte
3'b001: c0_pmbus_ctrl2 <= {c0_pmbus_ctrl2[31:16], wdata[15:0]} &
C0_PMBUS_CTRL2_RESERVED_MASK;// 2 byte
3'b010: c0_pmbus_ctrl2 <= {wdata[31:0]} &
C0_PMBUS_CTRL2_RESERVED_MASK;// 4 byte
endcase
end
end

assign out_port_list.c0_pmbus_ctrl2_page_base_addr_pg0 = c0_pmbus_ctrl2[7:0];

assign out_port_list.c0_pmbus_ctrl2_page_base_addr_pg1 = c0_pmbus_ctrl2[15:8];
assign out_port_list.c0_pmbus_ctrl2_page_base_addr_pg2 =
c0_pmbus_ctrl2[23:16];
assign out_port_list.c0_pmbus_ctrl2_page_base_addr_pg3 =
c0_pmbus_ctrl2[31:24];

//write logic for register c0_pmbus_ctrl3

logic [31:0] c0_pmbus_ctrl3;
localparam C0_PMBUS_CTRL3_RESERVED_MASK = 32'h7d01_bf77;

always_ff @(posedge clk or negedge rst_n) begin

if (!rst_n)
c0_pmbus_ctrl3 <= { 1'h0, 2'h0, 1'h0, 1'h1, 1'h1, 1'h0, 1'h0, 7'h0, 1'h0,
1'h0, 1'h0, 6'h19, 1'h0, 3'h4, 1'h0, 3'h2 };
else if ((reg_write_address == C0_PMBUS_CTRL3_ADDRESS) && reg_write) begin

case(awsize)
3'b000: c0_pmbus_ctrl3 <= {c0_pmbus_ctrl3[31:8], wdata[7:0]} &
C0_PMBUS_CTRL3_RESERVED_MASK;// 1 byte
3'b001: c0_pmbus_ctrl3 <= {c0_pmbus_ctrl3[31:16], wdata[15:0]} &
C0_PMBUS_CTRL3_RESERVED_MASK;// 2 byte
3'b010: c0_pmbus_ctrl3 <= {wdata[31:0]} &
C0_PMBUS_CTRL3_RESERVED_MASK;// 4 byte
endcase
end
end

assign out_port_list.c0_pmbus_ctrl3_tx_low_threhold = c0_pmbus_ctrl3[2:0];

assign out_port_list.c0_pmbus_ctrl3_glitch_fltr_len = c0_pmbus_ctrl3[6:4];
assign out_port_list.c0_pmbus_ctrl3_tsu_dat = c0_pmbus_ctrl3[13:8];
assign out_port_list.c0_pmbus_ctrl3_clock_low_en = c0_pmbus_ctrl3[15];
assign out_port_list.c0_pmbus_ctrl3_clock_high_en = c0_pmbus_ctrl3[16];
assign out_port_list.c0_pmbus_ctrl3_rx_buf_size_dbg = c0_pmbus_ctrl3[24];
assign out_port_list.c0_pmbus_ctrl3_scl_low_en_dbg = c0_pmbus_ctrl3[26];
assign out_port_list.c0_pmbus_ctrl3_tx_db_ur_cs_dbg = c0_pmbus_ctrl3[27];
assign out_port_list.c0_pmbus_ctrl3_slv_ip_busy = c0_pmbus_ctrl3[28];
assign out_port_list.c0_pmbus_ctrl3_data_rate =
c0_pmbus_ctrl3[30:29];

//write logic for register c0_pmbus_addr_ctrl0

logic [31:0] c0_pmbus_addr_ctrl0;
localparam C0_PMBUS_ADDR_CTRL0_RESERVED_MASK = 32'h0000_7f7f;

always_ff @(posedge clk or negedge rst_n) begin

if (!rst_n)
c0_pmbus_addr_ctrl0 <= { 17'h0, 7'h0, 1'h0, 7'h0 };
else if ((reg_write_address == C0_PMBUS_ADDR_CTRL0_ADDRESS) && reg_write) begin

case(awsize)
3'b000: c0_pmbus_addr_ctrl0 <= {c0_pmbus_addr_ctrl0[31:8], wdata[7:0]}
& C0_PMBUS_ADDR_CTRL0_RESERVED_MASK;// 1 byte
3'b001: c0_pmbus_addr_ctrl0 <= {c0_pmbus_addr_ctrl0[31:16], wdata[15:0]}
& C0_PMBUS_ADDR_CTRL0_RESERVED_MASK;// 2 byte
3'b010: c0_pmbus_addr_ctrl0 <= {wdata[31:0]}
& C0_PMBUS_ADDR_CTRL0_RESERVED_MASK;// 4 byte
endcase
end
end

assign out_port_list.c0_pmbus_addr_ctrl0_pmbus_slave_address=
c0_pmbus_addr_ctrl0[6:0];
assign out_port_list.c0_pmbus_addr_ctrl0_pmbus_slave_addr_mask=
c0_pmbus_addr_ctrl0[14:8];

//write logic for register c0_pmbus_addr_ctrl1

logic [31:0] c0_pmbus_addr_ctrl1;
localparam C0_PMBUS_ADDR_CTRL1_RESERVED_MASK = 32'h007f_7f7f;
always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n)
c0_pmbus_addr_ctrl1 <= { 9'h0, 7'h0C, 1'h0, 7'h28, 1'h0, 7'h37 };
else if ((reg_write_address == C0_PMBUS_ADDR_CTRL1_ADDRESS) && reg_write) begin

case(awsize)
3'b000: c0_pmbus_addr_ctrl1 <= {c0_pmbus_addr_ctrl1[31:8], wdata[7:0]}
& C0_PMBUS_ADDR_CTRL1_RESERVED_MASK;// 1 byte
3'b001: c0_pmbus_addr_ctrl1 <= {c0_pmbus_addr_ctrl1[31:16], wdata[15:0]}
& C0_PMBUS_ADDR_CTRL1_RESERVED_MASK;// 2 byte
3'b010: c0_pmbus_addr_ctrl1 <= {wdata[31:0]}
& C0_PMBUS_ADDR_CTRL1_RESERVED_MASK;// 4 byte
endcase
end
end

assign out_port_list.c0_pmbus_addr_ctrl1_zw_addr =
c0_pmbus_addr_ctrl1[6:0];
assign out_port_list.c0_pmbus_addr_ctrl1_zr_addr =
c0_pmbus_addr_ctrl1[14:8];
assign out_port_list.c0_pmbus_addr_ctrl1_ara_addr =
c0_pmbus_addr_ctrl1[22:16];

//write logic for register c0_pmbus_addr_ctrl2

logic [31:0] c0_pmbus_addr_ctrl2;
localparam C0_PMBUS_ADDR_CTRL2_RESERVED_MASK = 32'hffff_ffff;

always_ff @(posedge clk or negedge rst_n) begin

if (!rst_n)
c0_pmbus_addr_ctrl2 <= { 1'h0, 7'h0, 1'h0, 7'h0, 1'h0, 7'h0, 1'h0, 7'h0 };
else if ((reg_write_address == C0_PMBUS_ADDR_CTRL2_ADDRESS) && reg_write) begin

case(awsize)
3'b000: c0_pmbus_addr_ctrl2 <= {c0_pmbus_addr_ctrl2[31:8], wdata[7:0]}
& C0_PMBUS_ADDR_CTRL2_RESERVED_MASK;// 1 byte
3'b001: c0_pmbus_addr_ctrl2 <= {c0_pmbus_addr_ctrl2[31:16], wdata[15:0]}
& C0_PMBUS_ADDR_CTRL2_RESERVED_MASK;// 2 byte
3'b010: c0_pmbus_addr_ctrl2 <= {wdata[31:0]}
& C0_PMBUS_ADDR_CTRL2_RESERVED_MASK;// 4 byte
endcase
end
end

assign out_port_list.c0_pmbus_addr_ctrl2_pg0_slv_addr =
c0_pmbus_addr_ctrl2[6:0];
assign out_port_list.c0_pmbus_addr_ctrl2_pg0_addr_en =
c0_pmbus_addr_ctrl2[7];
assign out_port_list.c0_pmbus_addr_ctrl2_pg1_slv_addr =
c0_pmbus_addr_ctrl2[14:8];
assign out_port_list.c0_pmbus_addr_ctrl2_pg1_addr_en =
c0_pmbus_addr_ctrl2[15];
assign out_port_list.c0_pmbus_addr_ctrl2_pg2_slv_addr =
c0_pmbus_addr_ctrl2[22:16];
assign out_port_list.c0_pmbus_addr_ctrl2_pg2_addr_en =
c0_pmbus_addr_ctrl2[23];
assign out_port_list.c0_pmbus_addr_ctrl2_pg3_slv_addr =
c0_pmbus_addr_ctrl2[30:24];
assign out_port_list.c0_pmbus_addr_ctrl2_pg3_addr_en =
c0_pmbus_addr_ctrl2[31];

//write logic for register c0_pmbus_addr_ctrl3

logic [31:0] c0_pmbus_addr_ctrl3;
localparam C0_PMBUS_ADDR_CTRL3_RESERVED_MASK = 32'hffff_ffff;

always_ff @(posedge clk or negedge rst_n) begin

if (!rst_n)
c0_pmbus_addr_ctrl3 <= { 1'h0, 7'h0, 1'h0, 7'h0, 1'h0, 7'h0, 1'h0, 7'h0 };
else if ((reg_write_address == C0_PMBUS_ADDR_CTRL3_ADDRESS) && reg_write) begin

case(awsize)
3'b000: c0_pmbus_addr_ctrl3 <= {c0_pmbus_addr_ctrl3[31:8], wdata[7:0]}
& C0_PMBUS_ADDR_CTRL3_RESERVED_MASK;// 1 byte
3'b001: c0_pmbus_addr_ctrl3 <= {c0_pmbus_addr_ctrl3[31:16], wdata[15:0]}
& C0_PMBUS_ADDR_CTRL3_RESERVED_MASK;// 2 byte
3'b010: c0_pmbus_addr_ctrl3 <= {wdata[31:0]}
& C0_PMBUS_ADDR_CTRL3_RESERVED_MASK;// 4 byte
endcase
end
end

assign out_port_list.c0_pmbus_addr_ctrl3_rsv0_slv_addr =
c0_pmbus_addr_ctrl3[6:0];
assign out_port_list.c0_pmbus_addr_ctrl3_rsv0_addr_en =
c0_pmbus_addr_ctrl3[7];
assign out_port_list.c0_pmbus_addr_ctrl3_rsv1_slv_addr =
c0_pmbus_addr_ctrl3[14:8];
assign out_port_list.c0_pmbus_addr_ctrl3_rsv1_addr_en =
c0_pmbus_addr_ctrl3[15];
assign out_port_list.c0_pmbus_addr_ctrl3_rsv2_slv_addr =
c0_pmbus_addr_ctrl3[22:16];
assign out_port_list.c0_pmbus_addr_ctrl3_rsv2_addr_en =
c0_pmbus_addr_ctrl3[23];
assign out_port_list.c0_pmbus_addr_ctrl3_rsv3_slv_addr =
c0_pmbus_addr_ctrl3[30:24];
assign out_port_list.c0_pmbus_addr_ctrl3_rsv3_addr_en =
c0_pmbus_addr_ctrl3[31];

logic rx_buf_pop;
//--- pop logic for rx data ----
always_comb
begin
// rx_buf_pop = 0;
//------only for this particular address as up now------
if ((reg_read_address == C0_PMBUS_RX_DBUF_ADDRESS) && arready )
begin
rx_buf_pop = 1;
end
else
rx_buf_pop = 0;
end

//---create pop signal for rx data when firmware writes into the register---
assign out_port_list.rx_data_pop = rx_buf_pop;

logic [31:0] c0_pmbus_rx_dbuf;

//---data from the rx fifo and updating rx buf register----
always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n)
c0_pmbus_rx_dbuf <= 0;
else if(rx_buf_pop)
c0_pmbus_rx_dbuf <= 32'h0101;//in_port_list.c0_pmbus_rx_dbuf_rx_data;
end

//write logic for register c0_pmbus_tx_buf

logic [31:0] c0_pmbus_tx_buf;
localparam C0_PMBUS_TX_BUF_RESERVED_MASK = 32'hffff_ffff;

always_ff @(posedge clk or negedge rst_n) begin

if (!rst_n)
c0_pmbus_tx_buf <= 32'h0;
else if ((reg_write_address == C0_PMBUS_TX_BUF_ADDRESS) && reg_write) begin

case(awsize)
3'b000: c0_pmbus_tx_buf
<= {c0_pmbus_tx_buf[31:8], wdata[7:0]} &
C0_PMBUS_TX_BUF_RESERVED_MASK;// 1 byte
3'b001: c0_pmbus_tx_buf <= {c0_pmbus_tx_buf[31:16], wdata[15:0]} &
C0_PMBUS_TX_BUF_RESERVED_MASK;// 2 byte
3'b010: c0_pmbus_tx_buf <= {wdata[31:0]} &
C0_PMBUS_TX_BUF_RESERVED_MASK;// 4 byte
endcase
end
end

//assign out_port_list.c0_pmbus_tx_buf_tx_data =
c0_pmbus_tx_buf[31:0];

logic reg_write_d;
logic [31:0] tx_buf_data;
logic tx_buf_data_val;

//------push logic for tx data buffer ------

always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n)
reg_write_d <= 0;
else
reg_write_d <= reg_write;
end

//-- tx data logic-----

always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n)
begin
tx_buf_data <= 32'b0;
tx_buf_data_val <= 1'b0;
end
else if ( (reg_write_address == C0_PMBUS_TX_BUF_ADDRESS) && reg_write_d
)
begin
tx_buf_data <= c0_pmbus_tx_buf;
tx_buf_data_val <= 1'b1;
end
 else
begin
tx_buf_data <= 32'b0;
tx_buf_data_val <= 1'b0;
end
end

//-----push and data for hardware----------

assign out_port_list.tx_buf_tx_data = tx_buf_data[31:0];
assign out_port_list.tx_buf_tx_data_push = tx_buf_data_val;

//write logic for register c0_pmbus_ack_ctrl

logic [31:0] c0_pmbus_ack_ctrl;
localparam C0_PMBUS_ACK_CTRL_RESERVED_MASK = 32'h0000_0001;

always_ff @(posedge clk or negedge rst_n) begin

if (!rst_n)
c0_pmbus_ack_ctrl <= { 31'h0, 1'h0 };
else if ((reg_write_address == C0_PMBUS_ACK_CTRL_ADDRESS) && reg_write) begin

case(awsize)
3'b000: c0_pmbus_ack_ctrl <= {c0_pmbus_ack_ctrl[31:8], wdata[7:0]} &
C0_PMBUS_ACK_CTRL_RESERVED_MASK;// 1 byte
3'b001: c0_pmbus_ack_ctrl <= {c0_pmbus_ack_ctrl[31:16], wdata[15:0]} &
C0_PMBUS_ACK_CTRL_RESERVED_MASK;// 2 byte
3'b010: c0_pmbus_ack_ctrl <= {wdata[31:0]} &
C0_PMBUS_ACK_CTRL_RESERVED_MASK;// 4 byte
endcase
end
end

assign out_port_list.c0_pmbus_ack_ctrl_ack_ctrl = c0_pmbus_ack_ctrl[0];

//write logic for register c0_pmbus_int_mask_ctrl

logic [31:0] c0_pmbus_int_mask_ctrl;
localparam C0_PMBUS_INT_MASK_CTRL_RESERVED_MASK = 32'h00fb_00fb;

always_ff @(posedge clk or negedge rst_n) begin

if (!rst_n)
c0_pmbus_int_mask_ctrl <= { 8'h0, 1'h0, 1'h0, 1'h0, 1'h0, 1'h0, 1'h0, 1'h0,
1'h0, 8'h0, 1'h0, 1'h0, 1'h0, 1'h0, 1'h0, 1'h0, 1'h0, 1'h0 };
else if ((reg_write_address == C0_PMBUS_INT_MASK_CTRL_ADDRESS) && reg_write)
begin

case(awsize)
3'b000: c0_pmbus_int_mask_ctrl <= {c0_pmbus_int_mask_ctrl[31:8], wdata[7:0]}
& C0_PMBUS_INT_MASK_CTRL_RESERVED_MASK;// 1 byte
3'b001: c0_pmbus_int_mask_ctrl <= {c0_pmbus_int_mask_ctrl[31:16],
wdata[15:0]} & C0_PMBUS_INT_MASK_CTRL_RESERVED_MASK;// 2 byte
3'b010: c0_pmbus_int_mask_ctrl <= {wdata[31:0]}
& C0_PMBUS_INT_MASK_CTRL_RESERVED_MASK;// 4 byte
endcase
end
end

assign out_port_list.c0_pmbus_int_mask_ctrl_stop_f_en =
c0_pmbus_int_mask_ctrl[0];
assign out_port_list.c0_pmbus_int_mask_ctrl_cmd_data_val_f_en=
c0_pmbus_int_mask_ctrl[1];
assign out_port_list.c0_pmbus_int_mask_ctrl_rx_buf_of_f_en =
c0_pmbus_int_mask_ctrl[3];
assign out_port_list.c0_pmbus_int_mask_ctrl_tx_buf_low_f_en =
c0_pmbus_int_mask_ctrl[4];
assign out_port_list.c0_pmbus_int_mask_ctrl_tx_buf_ur_f_en =
c0_pmbus_int_mask_ctrl[5];
assign out_port_list.c0_pmbus_int_mask_ctrl_slv_bsy_f_int =
c0_pmbus_int_mask_ctrl[6];
assign out_port_list.c0_pmbus_int_mask_ctrl_multi_f_int =
c0_pmbus_int_mask_ctrl[7];
assign out_port_list.c0_pmbus_int_mask_ctrl_stop_n_en =
c0_pmbus_int_mask_ctrl[16];
assign out_port_list.c0_pmbus_int_mask_ctrl_cmd_data_val_n_en=
c0_pmbus_int_mask_ctrl[17];
assign out_port_list.c0_pmbus_int_mask_ctrl_rx_buf_of_n_en =
c0_pmbus_int_mask_ctrl[19];
assign out_port_list.c0_pmbus_int_mask_ctrl_tx_buf_low_n_en =
c0_pmbus_int_mask_ctrl[20];
assign out_port_list.c0_pmbus_int_mask_ctrl_tx_buf_ur_n_en =
c0_pmbus_int_mask_ctrl[21];
assign out_port_list.c0_pmbus_int_mask_ctrl_slv_bsy_n_int =
c0_pmbus_int_mask_ctrl[22];
assign out_port_list.c0_pmbus_int_mask_ctrl_multi_n_int =
c0_pmbus_int_mask_ctrl[23];

//write logic for register c0_pmbus_clk_low_to

logic [31:0] c0_pmbus_clk_low_to;
localparam C0_PMBUS_CLK_LOW_TO_RESERVED_MASK = 32'h00ff_ffff;

always_ff @(posedge clk or negedge rst_n) begin

if (!rst_n)
c0_pmbus_clk_low_to <= { 8'h0, 24'h0 };
else if ((reg_write_address == C0_PMBUS_CLK_LOW_TO_ADDRESS) && reg_write) begin

case(awsize)
3'b000: c0_pmbus_clk_low_to <= {c0_pmbus_clk_low_to[31:8], wdata[7:0]}
& C0_PMBUS_CLK_LOW_TO_RESERVED_MASK;// 1 byte
3'b001: c0_pmbus_clk_low_to <= {c0_pmbus_clk_low_to[31:16], wdata[15:0]}
& C0_PMBUS_CLK_LOW_TO_RESERVED_MASK;// 2 byte
3'b010: c0_pmbus_clk_low_to <= {wdata[31:0]}
& C0_PMBUS_CLK_LOW_TO_RESERVED_MASK;// 4 byte
endcase
end
end

assign out_port_list.c0_pmbus_clk_low_to_clk_low_to =
c0_pmbus_clk_low_to[23:0];

//write logic for register c0_rail_enable

logic [31:0] c0_rail_enable;
localparam C0_RAIL_ENABLE_RESERVED_MASK = 32'h0000_000f;

always_ff @(posedge clk or negedge rst_n) begin

if (!rst_n)
c0_rail_enable <= { 28'h0, 4'h0 };
else if ((reg_write_address == C0_RAIL_ENABLE_ADDRESS) && reg_write) begin

case(awsize)
 3'b000: c0_rail_enable <= {c0_rail_enable[31:8], wdata[7:0]} &
C0_RAIL_ENABLE_RESERVED_MASK;// 1 byte
3'b001: c0_rail_enable <= {c0_rail_enable[31:16], wdata[15:0]} &
C0_RAIL_ENABLE_RESERVED_MASK;// 2 byte
3'b010: c0_rail_enable <= {wdata[31:0]} &
C0_RAIL_ENABLE_RESERVED_MASK;// 4 byte
endcase
end
end

assign out_port_list.c0_rail_enable = c0_rail_enable[3:0];

//write logic for register c0_phase_enable

logic [31:0] c0_phase_enable;
localparam C0_PHASE_ENABLE_RESERVED_MASK = 32'h00ff_ffff;

always_ff @(posedge clk or negedge rst_n) begin

if (!rst_n)
c0_phase_enable <= { 8'h0, 24'h0 };
else if ((reg_write_address == C0_PHASE_ENABLE_ADDRESS) && reg_write) begin

case(awsize)
3'b000: c0_phase_enable <= {c0_phase_enable[31:8], wdata[7:0]} &
C0_PHASE_ENABLE_RESERVED_MASK;// 1 byte
3'b001: c0_phase_enable <= {c0_phase_enable[31:16], wdata[15:0]} &
C0_PHASE_ENABLE_RESERVED_MASK;// 2 byte
3'b010: c0_phase_enable <= {wdata[31:0]} &
C0_PHASE_ENABLE_RESERVED_MASK;// 4 byte
endcase
end
end

assign out_port_list.c0_phase_enable_phase_en =
c0_phase_enable[23:0];

//write logic for register c0_partition_enable

logic [31:0] c0_partition_enable;
localparam C0_PARTITION_ENABLE_RESERVED_MASK = 32'h0000_003f;

always_ff @(posedge clk or negedge rst_n) begin

if (!rst_n)
c0_partition_enable <= { 26'h0, 6'h0 };
else if ((reg_write_address == C0_PARTITION_ENABLE_ADDRESS) && reg_write) begin

case(awsize)
3'b000: c0_partition_enable <= {c0_partition_enable[31:8], wdata[7:0]}
& C0_PARTITION_ENABLE_RESERVED_MASK;// 1 byte
3'b001: c0_partition_enable <= {c0_partition_enable[31:16], wdata[15:0]}
& C0_PARTITION_ENABLE_RESERVED_MASK;// 2 byte
3'b010: c0_partition_enable <= {wdata[31:0]}
& C0_PARTITION_ENABLE_RESERVED_MASK;// 4 byte
endcase
end
end

assign out_port_list.c0_partition_enable_partition_en =
c0_partition_enable[5:0];

//write one to clr enable signals for fast status

logic [31:0] c0_pmbus_sts0;
logic [31:0] c0_pmbus_err_sts0;
logic [31:0] c0_pmbus_sts1;
logic [31:0] c0_pmbus_err_sts1;

//write one to clr enable signals for fast status

/*logic stop_f;
logic cmd_data_avl_f;
logic rx_buf_of_f;
logic tx_buf_low_f;
logic tx_buf_ur_f;
logic slv_busy_f;
logic multi_f;*/

logic stat0_reg_en_f;

logic stop_clr_f;
logic cmd_data_avl_clr_f;
logic rx_buf_of_clr_f;
logic tx_buf_low_clr_f;
logic tx_buf_ur_clr_f;
logic slv_busy_clr_f;
logic multi_clr_f;

logic stop_sc_f_nxt;
logic cmd_data_avl_sc_f_nxt;
logic rx_buf_of_sc_f_nxt;
logic tx_buf_low_sc_f_nxt;
logic tx_buf_ur_sc_f_nxt;
logic slv_busy_sc_f_nxt;
logic multi_sc_f_nxt;

//write one to clr enable signals for normal status

/*logic stop_n;
logic cmd_data_avl_n;
logic rx_buf_of_n;
logic tx_buf_low_n;
logic tx_buf_ur_n;
logic slv_busy_n;
logic multi_n;*/

logic stat1_reg_en_n;

logic stop_clr_n;
logic cmd_data_avl_clr_n;
logic rx_buf_of_clr_n;
logic tx_buf_low_clr_n;
logic tx_buf_ur_clr_n;
logic slv_busy_clr_n;
logic multi_clr_n;

logic stop_sc_n_nxt;
logic cmd_data_avl_sc_n_nxt;
logic rx_buf_of_sc_n_nxt;
logic tx_buf_low_sc_n_nxt;
logic tx_buf_ur_sc_n_nxt;
logic slv_busy_sc_n_nxt;
logic multi_sc_n_nxt;
//----------write one to clear enable signals for the status registers-------
// TODO: Fix this
always_comb begin
/* stop_f = 1'b0;
cmd_data_avl_f = 1'b0;
rx_buf_of_f = 1'b0;
tx_buf_low_f = 1'b0;
tx_buf_ur_f = 1'b0;
slv_busy_f = 1'b0;
multi_f = 1'b0;

stop_n = 1'b0;
cmd_data_avl_n = 1'b0;
rx_buf_of_n = 1'b0;
tx_buf_low_n = 1'b0;
tx_buf_ur_n = 1'b0;
slv_busy_n = 1'b0;
multi_n = 1'b0;*/

stat0_reg_en_f = 1'b0;
stat1_reg_en_n = 1'b0;

if (reg_write) begin
case (reg_write_address)
C0_PMBUS_STS0_ADDRESS: begin
stat0_reg_en_f = 1'b1;
/* stop_f = 1'b1;
cmd_data_avl_f = 1'b1;
rx_buf_of_f = 1'b1;
tx_buf_low_f = 1'b1;
tx_buf_ur_f = 1'b1;
slv_busy_f = 1'b1;
multi_f = 1'b1;*/
end
C0_PMBUS_STS1_ADDRESS: begin
stat1_reg_en_n = 1'b1;
/* stop_n = 1'b1;
cmd_data_avl_n = 1'b1;
rx_buf_of_n = 1'b1;
tx_buf_low_n = 1'b1;
tx_buf_ur_n = 1'b1;
slv_busy_n = 1'b1;
multi_n = 1'b1;*/
end
endcase
end
end

// Write 1 to clear logic for for fast interupt

assign stop_clr_f = reg_write & stat0_reg_en_f ? wdata[0] : 1'b0;
assign cmd_data_avl_clr_f = reg_write & stat0_reg_en_f ? wdata[1] : 1'b0;
assign rx_buf_of_clr_f = reg_write & stat0_reg_en_f ? wdata[3] : 1'b0;
assign tx_buf_low_clr_f = reg_write & stat0_reg_en_f ? wdata[4] : 1'b0;
assign tx_buf_ur_clr_f = reg_write & stat0_reg_en_f ? wdata[5] : 1'b0;
assign slv_busy_clr_f = reg_write & stat0_reg_en_f ? wdata[6] : 1'b0;
assign multi_clr_f = reg_write & stat0_reg_en_f ? wdata[7] : 1'b0;

assign stop_sc_f_nxt = ~stop_clr_f &

(in_port_list.c0_pmbus_sts0_stop_f | c0_pmbus_sts0[0]);
assign cmd_data_avl_sc_f_nxt = ~cmd_data_avl_clr_f &
(in_port_list.c0_pmbus_sts0_cmd_data_avl_f | c0_pmbus_sts0[1]);
assign rx_buf_of_sc_f_nxt = ~rx_buf_of_clr_f &
(in_port_list.c0_pmbus_sts0_rx_buf_of_f | c0_pmbus_sts0[3]);
assign tx_buf_low_sc_f_nxt = ~tx_buf_low_clr_f &
(in_port_list.c0_pmbus_sts0_tx_buf_low_f | c0_pmbus_sts0[4]);
assign tx_buf_ur_sc_f_nxt = ~tx_buf_ur_clr_f &
(in_port_list.c0_pmbus_sts0_tx_buf_ur_f | c0_pmbus_sts0[5]);
assign slv_busy_sc_f_nxt = ~slv_busy_clr_f &
(in_port_list.c0_pmbus_sts0_slv_busy_f | c0_pmbus_sts0[6]);
assign multi_sc_f_nxt = ~multi_clr_f &
(in_port_list.c0_pmbus_sts0_multi_f | c0_pmbus_sts0[7]);

// Write 1 to clear logic for for normal interupt

assign stop_clr_n = reg_write & stat1_reg_en_n ? wdata[0] : 1'b0;
assign cmd_data_avl_clr_n = reg_write & stat1_reg_en_n ? wdata[1] : 1'b0;
assign rx_buf_of_clr_n = reg_write & stat1_reg_en_n ? wdata[3] : 1'b0;
assign tx_buf_low_clr_n = reg_write & stat1_reg_en_n ? wdata[4] : 1'b0;
assign tx_buf_ur_clr_n = reg_write & stat1_reg_en_n ? wdata[5] : 1'b0;
assign slv_busy_clr_n = reg_write & stat1_reg_en_n ? wdata[6] : 1'b0;
assign multi_clr_n = reg_write & stat1_reg_en_n ? wdata[7] : 1'b0;

assign stop_sc_n_nxt = ~stop_clr_n &

(in_port_list.c0_pmbus_sts1_stop_n | c0_pmbus_sts1[0]);
assign cmd_data_avl_sc_n_nxt = ~cmd_data_avl_clr_n &
(in_port_list.c0_pmbus_sts1_cmd_data_avl_n | c0_pmbus_sts1[1]);
assign rx_buf_of_sc_n_nxt = ~rx_buf_of_clr_n &
(in_port_list.c0_pmbus_sts1_rx_buf_of_n | c0_pmbus_sts1[3]);
assign tx_buf_low_sc_n_nxt = ~tx_buf_low_clr_n &
(in_port_list.c0_pmbus_sts1_tx_buf_low_n | c0_pmbus_sts1[4]);
assign tx_buf_ur_sc_n_nxt = ~tx_buf_ur_clr_n &
(in_port_list.c0_pmbus_sts1_tx_buf_ur_n | c0_pmbus_sts1[5]);
assign slv_busy_sc_n_nxt = ~slv_busy_clr_n &
(in_port_list.c0_pmbus_sts1_slv_busy_n | c0_pmbus_sts1[6]);
assign multi_sc_n_nxt = ~multi_clr_n &
(in_port_list.c0_pmbus_sts1_multi_n | c0_pmbus_sts1[7]);

always_ff @(posedge clk or negedge rst_n) begin

if (!rst_n) begin
c0_pmbus_sts0[0] <= 1'b0;
c0_pmbus_sts0[1] <= 1'b0;
c0_pmbus_sts0[2] <= 1'b0;
c0_pmbus_sts0[3] <= 1'b0;
c0_pmbus_sts0[4] <= 1'b0;
c0_pmbus_sts0[5] <= 1'b0;
c0_pmbus_sts0[6] <= 1'b0;
c0_pmbus_sts0[7] <= 1'b0;
end
else begin
c0_pmbus_sts0[0] <= stop_sc_f_nxt;
c0_pmbus_sts0[1] <= cmd_data_avl_sc_f_nxt;
c0_pmbus_sts0[2] <= 1'b0;// TODO: Rsvd
c0_pmbus_sts0[3] <= rx_buf_of_sc_f_nxt;
c0_pmbus_sts0[4] <= tx_buf_low_sc_f_nxt;
c0_pmbus_sts0[5] <= tx_buf_ur_sc_f_nxt;
c0_pmbus_sts0[6] <= slv_busy_sc_f_nxt;
c0_pmbus_sts0[7] <= multi_sc_f_nxt;
end
end

always_ff @(posedge clk or negedge rst_n) begin

if (!rst_n) begin
c0_pmbus_sts1[0] <= 1'b0;
c0_pmbus_sts1[1] <= 1'b0;
c0_pmbus_sts1[2] <= 1'b0;
c0_pmbus_sts1[3] <= 1'b0;
c0_pmbus_sts1[4] <= 1'b0;
c0_pmbus_sts1[5] <= 1'b0;
c0_pmbus_sts1[6] <= 1'b0;
c0_pmbus_sts1[7] <= 1'b0;
end
else begin
c0_pmbus_sts1[0] <= stop_sc_n_nxt;
c0_pmbus_sts1[1] <= cmd_data_avl_sc_n_nxt;
c0_pmbus_sts1[2] <= 1'b0;// TODO: Rsvd
c0_pmbus_sts1[3] <= rx_buf_of_sc_n_nxt;
c0_pmbus_sts1[4] <= tx_buf_low_sc_n_nxt;
c0_pmbus_sts1[5] <= tx_buf_ur_sc_n_nxt;
c0_pmbus_sts1[6] <= slv_busy_sc_n_nxt;
c0_pmbus_sts1[7] <= multi_sc_n_nxt;
end
end

//replication of hardware signals for normal status register

assign c0_pmbus_sts0[8] = in_port_list.c0_pmbus_sts0_cmd_val_f;
assign c0_pmbus_sts0[9] = in_port_list.c0_pmbus_sts0_data_avl_f;
assign c0_pmbus_sts0[10] = in_port_list.c0_pmbus_sts0_rpt_start_val_f;
assign c0_pmbus_sts0[11] = in_port_list.c0_pmbus_sts0_ext_cmd_val_f;
assign c0_pmbus_sts0[12] = in_port_list.c0_pmbus_sts0_rd_val_f;
assign c0_pmbus_sts0[13] = in_port_list.c0_pmbus_sts0_err_det_f;
assign c0_pmbus_sts0[15:14] = in_port_list.c0_pmbus_sts0_pg_det_f;
assign c0_pmbus_sts0[18:16] = in_port_list.c0_pmbus_sts0_rx_data_buf_fill_cnt_f;
assign c0_pmbus_sts0[21:19] = in_port_list.c0_pmbus_sts0_tx_data_buf_fill_cnt_f;
assign c0_pmbus_sts0[23:22] = 2'b0;
assign c0_pmbus_sts0[31:24] = in_port_list.c0_pmbus_sts0_cmd_f;

assign c0_pmbus_sts1[8] = in_port_list.c0_pmbus_sts1_cmd_val_n;

assign c0_pmbus_sts1[9] = in_port_list.c0_pmbus_sts1_data_avl_n;
assign c0_pmbus_sts1[10] = in_port_list.c0_pmbus_sts1_rpt_start_val_n;
assign c0_pmbus_sts1[11] = in_port_list.c0_pmbus_sts1_ext_cmd_val_n;
assign c0_pmbus_sts1[12] = in_port_list.c0_pmbus_sts1_rd_val_n;
assign c0_pmbus_sts1[13] = in_port_list.c0_pmbus_sts1_err_det_n;
assign c0_pmbus_sts1[15:14] = in_port_list.c0_pmbus_sts1_pg_det_n;
assign c0_pmbus_sts1[18:16] = in_port_list.c0_pmbus_sts1_rx_data_buf_fill_cnt_n;
assign c0_pmbus_sts1[21:19] = in_port_list.c0_pmbus_sts1_tx_data_buf_fill_cnt_n;
assign c0_pmbus_sts1[23:22] = 2'b0;
assign c0_pmbus_sts1[31:24] = in_port_list.c0_pmbus_sts1_cmd_n;

//replication of hardware signals for fast error status register

assign c0_pmbus_err_sts0[0] = in_port_list.c0_pmbus_err_sts0_pec_err_f;
assign c0_pmbus_err_sts0[1] = in_port_list.c0_pmbus_err_sts0_cmd_err_f;
assign c0_pmbus_err_sts0[2] = in_port_list.c0_pmbus_err_sts0_oth_err_f;
assign c0_pmbus_err_sts0[5:3] = in_port_list.c0_pmbus_err_sts0_misc_err_enc_f;
assign c0_pmbus_err_sts0[7:6] = 2'b0;
assign c0_pmbus_err_sts0[10:8] = in_port_list.c0_pmbus_err_sts0_to_enc_f;
assign c0_pmbus_err_sts0[11] = in_port_list.c0_pmbus_err_sts0_ara_f;
assign c0_pmbus_err_sts0[31:12] = 20'b0;
//replication of hardware signals for normal error status register
assign c0_pmbus_err_sts1[0] = in_port_list.c0_pmbus_err_sts1_pec_err_n;
assign c0_pmbus_err_sts1[1] = in_port_list.c0_pmbus_err_sts1_cmd_err_n;
assign c0_pmbus_err_sts1[2] = in_port_list.c0_pmbus_err_sts1_oth_err_n;
assign c0_pmbus_err_sts1[5:3] = in_port_list.c0_pmbus_err_sts1_misc_err_enc_n;
assign c0_pmbus_err_sts1[7:6] = 2'b0;
assign c0_pmbus_err_sts1[10:8] = in_port_list.c0_pmbus_err_sts1_to_enc_n;
assign c0_pmbus_err_sts1[11] = in_port_list.c0_pmbus_err_sts1_ara_n;
assign c0_pmbus_err_sts1[31:12] = 20'b0;

logic [31:0] reg_data_out_nxt;

always_comb begin
reg_data_out_nxt = {DW{1'b0}};
if(reg_read) begin
case(reg_read_address)
C0_PMBUS_CTRL0_ADDRESS : reg_data_out_nxt = c0_pmbus_ctrl0
[31:0];
C0_PMBUS_CTRL1_ADDRESS : reg_data_out_nxt = c0_pmbus_ctrl1
[31:0];
C0_PMBUS_CTRL2_ADDRESS : reg_data_out_nxt = c0_pmbus_ctrl2
[31:0];
C0_PMBUS_CTRL3_ADDRESS : reg_data_out_nxt = c0_pmbus_ctrl3
[31:0];
C0_PMBUS_ADDR_CTRL0_ADDRESS : reg_data_out_nxt = c0_pmbus_addr_ctrl0
[31:0];
C0_PMBUS_ADDR_CTRL1_ADDRESS : reg_data_out_nxt = c0_pmbus_addr_ctrl1
[31:0];
C0_PMBUS_ADDR_CTRL2_ADDRESS : reg_data_out_nxt = c0_pmbus_addr_ctrl2
[31:0];
C0_PMBUS_ADDR_CTRL3_ADDRESS : reg_data_out_nxt = c0_pmbus_addr_ctrl3
[31:0];
C0_PMBUS_STS0_ADDRESS : reg_data_out_nxt = c0_pmbus_sts0
[31:0];
C0_PMBUS_ERR_STS0_ADDRESS : reg_data_out_nxt = c0_pmbus_err_sts0
[31:0];
C0_PMBUS_STS1_ADDRESS : reg_data_out_nxt = c0_pmbus_sts1
[31:0];
C0_PMBUS_ERR_STS1_ADDRESS : reg_data_out_nxt = c0_pmbus_err_sts1
[31:0];
C0_PMBUS_RX_DBUF_ADDRESS : reg_data_out_nxt = c0_pmbus_rx_dbuf
[31:0];
//C0_PMBUS_TX_BUF_ADDRESS : reg_data_out_nxt = c0_pmbus_tx_buf
[31:0];
C0_PMBUS_ACK_CTRL_ADDRESS : reg_data_out_nxt = c0_pmbus_ack_ctrl
[31:0];
C0_PMBUS_INT_MASK_CTRL_ADDRESS: reg_data_out_nxt =
c0_pmbus_int_mask_ctrl[31:0];
C0_PMBUS_CLK_LOW_TO_ADDRESS : reg_data_out_nxt = c0_pmbus_clk_low_to
[31:0];
C0_RAIL_ENABLE_ADDRESS : reg_data_out_nxt = c0_rail_enable
[31:0];
C0_PHASE_ENABLE_ADDRESS : reg_data_out_nxt = c0_phase_enable
[31:0];
C0_PARTITION_ENABLE_ADDRESS : reg_data_out_nxt = c0_partition_enable
[31:0];
endcase
end
end
// TODO: check if we need to call mask or enable
assign fast_int = |{~c0_pmbus_int_mask_ctrl[7:0] & c0_pmbus_sts0[7:0]};
assign norm_int = |{~c0_pmbus_int_mask_ctrl[23:15] & c0_pmbus_sts1[7:0]};

always_ff @(posedge clk or negedge rst_n) begin

if (!rst_n) begin
cmd_lut_0_rd_en_o_d <= 1'b0;
cmd_lut_1_rd_en_o_d <= 1'b0;
end
else
begin
cmd_lut_0_rd_en_o_d <= cmd_lut_0_rd_en_o;
cmd_lut_1_rd_en_o_d <= cmd_lut_1_rd_en_o;
end
end
reg [31:0]rdata_buf;
assign rdata = rvalid ? rdata_buf : 32'b0;

always_ff @(posedge clk or negedge rst_n) begin

if (!rst_n)
rdata_buf <= {DW{1'b0}};
else if(rvalid && !rready)
rdata_buf <= rdata_buf;
else begin
// FW Read CMD LUT 0
if (cmd_lut_0_rd_en_o_d ) //& !hw_cmd_lut_0_rd_en_d & !
hw_cmd_lut_1_rd_en_d) // TODO: fix this
rdata_buf <= cmd_lut_0_rd_data_i;
// FW Read CMD LUT 0
else if (cmd_lut_1_rd_en_o_d) //& !hw_cmd_lut_0_rd_en_d & !
hw_cmd_lut_1_rd_en_d) // TODO: fix this no need of unnecessary even data there in
rdata rvalid wont be there so rvalid validates data
rdata_buf <= cmd_lut_1_rd_data_i;
else begin
case(arsize)
3'b000: rdata_buf <= reg_data_out_nxt & 32'h0000_00ff;
3'b001: rdata_buf <= reg_data_out_nxt & 32'h0000_ffff;
3'b010: rdata_buf <= reg_data_out_nxt & 32'hffff_ffff;
endcase
end
end
end

/*
always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n)
rdata <= {DW{1'b0}};
else if(rvalid)begin
case(arsize)
3'b000: rdata <= reg_data_out_nxt & 32'h0000_00ff;
3'b001: rdata <= reg_data_out_nxt & 32'h0000_ffff;
3'b010: rdata <= reg_data_out_nxt & 32'hffff_ffff;
endcase
*//*if(rvalid && !rready)
rdata <= rdata;
else *//* begin
// FW Read CMD LUT 0
 if (cmd_lut_0_rd_en_o_d ) //& !hw_cmd_lut_0_rd_en_d & !
hw_cmd_lut_1_rd_en_d) // TODO: fix this
rdata <= cmd_lut_0_rd_data_i;
// FW Read CMD LUT 0
else if (cmd_lut_1_rd_en_o_d) //& !hw_cmd_lut_0_rd_en_d & !
hw_cmd_lut_1_rd_en_d) // TODO: fix this no need of unnecessary even data there in
rdata rvalid wont be there so rvalid validates data
rdata <= cmd_lut_1_rd_data_i;
end
end
else
rdata <= {DW{1'b0}};
end*/

endmodule