MODULE 3

ASSEMBLY LANGUAGE PROGRAMMING TECHNIQUES

1. Looping, Indexing and Delay Generation in 8085

Looping in 8085

Looping is a programming technique that instructs the Microprocessor to repeat tasks. It is accomplished by
changing the sequence of execution using jump instructions.

Loops can be classified into two groups:

1. Continuous Loops.
2. Conditional Loops.

Continuous Loops

A continuous loops repeats a task continuously. It is setup by using unconditional jump instruction. A program
with a continuous loop will keep repeating tasks until the system is reset as shown in the flowchart.

Flowchart of a Continuous Loop

Conditional Loops

A conditional loop repeat a task if some conditions are satisfied. They are setup by conditional jump instructions.
These instructions check flags(Z, CY, P, S) and repeat the tasks based on the flag values. These loops include
counting and indexing.

Conditional Loop and Counter

A counter is a typical application of the conditional loop. To achieve the looping task, the microprocessor requires
a counter and a flag. A counter is set up by loading a suitable count into a register. Counting is accomplished by
either incrementing or decrementing the counter. A conditional jump instruction creates the loop and the end of
counting is indicated by a flag.

The following flowchart illustrates the approach needed for the microprocessor to repeat a task five times.

These notes are taken from and distributed through BSC CS CU Study Notes
 Task Repetition Using Conditional Loops

Indexing

Pointing objects with sequential numbers is called indexing. Data bytes are stored in memory locations and are
referred to by their memory locations.

Delay Generation in 8085

The counting method described above has a significant downside in that it is performed at such a high speed that
only the final count can be seen. So to notice the counting, there must be an appropriate time delay between
counts.

Depending on the time delay required, a register is loaded with a number, and then the register is decremented
until it reaches zero by setting up a loop with a conditional jump instruction. The delay is caused by the loop,
which is determined by the system’s clock period.

The following methods are used for generating delays:

• Using NOP instructions.

• Using 8-bit register as counter.
• Using 16-bit register pair as counter.

Using NOP Instructions

These notes are taken from and distributed through BSC CS CU Study Notes
One of the most common applications of the NOP instruction is in the generation of delays. The NOP instruction
requires four clock pulses to fetch, decode, and execute. As a result, this form of NOP instruction can be used to
induce a few milliseconds of time delay.

Time Delay Using One Register

The following program will demonstrate the time delay using 8-bit counter.

MVI B, FFH

LOOP: DCR B

JNZ LOOP

RET

The first instruction will be executed once, which will take 7 T-states. The DCR C instruction requires 4 T-states.
This will be executed 255 (FF) times. The JNZ instruction takes 10 T-states when it jumps (It jumps 254 times),
otherwise it will take 7 T-States. The RET instruction requires 10 T-States.

So we can use this technique with some other values in the place of FF, when we need some small delay.

Time Delay Using a Register Pair

Instead of an 8-bit counter, we can do the same task with a 16-bit register pair. More time delay can be generated
using this method. For example:

LXI B,FFFFH

LOOP: DCX B

MOV A,B

ORA C

JNZ LOOP

RET

This method can be used to get more than 0.5 seconds delay.

2. STACK in 8085
The stack in an 8085 can be described as a reserved area of the memory in the R/W memory where we can store
temporary information. It is a shared resource as it can be shared by the microprocessor and the programmer.
Programmers use the stack to store data and the microprocessors use the stack to execute subroutines.

The 8085 has a 16-bit register known as the Stack Pointer. The function of the stack pointer is to hold the starting
address of the stack. This address can be decided by the programmer.

The stack operates on the Last In, First Out (LIFO) principle. The location of the most recent data on the stack is
known as the TOP of the stack. The stack pointer always points to the top of the stack. Contents can be stored in
the stack using the PUSH instruction and can restore the contents by using the instruction POP.

These notes are taken from and distributed through BSC CS CU Study Notes
 MNEMONIC DESCRIPTION

LXI SP, 16-

Load the stack pointer register with a 16-bit address.
bit

PUSH Rp Copies the contents of the specified register pair on the stack

Copies the contents of the top two memory locations of the stack into the specified register
POP Rp
pair.

PUSH and POP Operation in 8085

PUSH Rp

This is a 1-byte instruction. This instruction copies the contents of the specified register pair on the stack as
described below:

• The stack pointer is decremented and the contents of the higher-order register are copied to the location
shown by the stack pointer register.
• The stack pointer is again decremented and the contents of the low-order register are copied to that location.

POP Rp

This is a 1-byte instruction. This instruction copies the contents of the top two memory locations of the stack into
the specified register pair.

• First, the contents of the memory location indicated by the stack pointer register are copied into the low-
order register and then the stack pointer register is incremented by 1.
• The contents of the next memory location are copied into the high-order register and the stack pointer register
is again incremented by 1.

Example
LXI SP,2099H

LXI H, 42F2H

PUSH H

Delay Counter

POP H

• The instruction LXI SP, 2099H will initialize the stack pointer with the address of 2099H.
• LXI H, 42F2H will initialize or load HL register pair with 42F2H data so H = 42 and L = F2.

These notes are taken from and distributed through BSC CS CU Study Notes
• After the execution of PUSH H instruction the stack pointer is decreased by one to 2098H and the contents
of the H register are copied to memory location 2098H.
• The stack pointer is again decreased by one to 2097H and the contents of the L register are copied to
memory location 2097H.

Contents of Stack and Registers After PUSH Operation

• After the execution of POP H instruction, the contents of the top of the stack location shown by the stack
pointer are copied in the L register and the stack pointer is increased by one to 2098H.
• The contents of the top of the stack are copied in the H register and the stack pointer is increased by one.
• The contents of the memory locations 2097H and 2098H are not destroyed until some other data bytes are
stored in these locations.

Contents of Stack and Registers After POP Operation

These notes are taken from and distributed through BSC CS CU Study Notes
3. Subroutines in 8085
A subroutine is a set of instructions that will be used repeatedly in different locations of the program. Instead of
repeating the same instructions several times, they can be combined into a subroutine that is called from various
locations. A subroutine in Assembly language can exist anywhere in the code. However, It is a common practice
to separate subroutines from the main program.

Subroutine Call and Program Transfer

The 8085 microprocessor has two instructions to implement subroutines. The CALL instruction is used to
redirect program execution to a subroutine. The RET instruction is used to return the execution to the calling
routine. They are described in the following table.

MNEMONIC DESCRIPTION

3-byte instruction.
CALL 16-bit address
Jumps unconditionally to the memory location specified.

1-byte instruction.
RET
Unconditionally returns from the subroutine.

When the CALL instruction has been executed the contents of the program counter is saved to the top of
the stack. This return address is retrieved from the stack when the RET instruction is executed.

4. Interrupts
Interrupt I/O is a data transfer method in which an external device informs the microprocessor that it is ready for
communication and requests attention. The 8085-interrupt process is controlled by the Interrupt Enable flip-flop.

The microprocessor is said to be interrupted when the flipflop is enabled and the signal INTR goes high. The
instruction EI and DI are used to set and reset the Interrupt Enable flip-flop respectively.

OPCODE DESCRIPTION

Sets the Interrupt Enable flip-flop and enables the interrupt process.
EI
System reset or an interrupt disables the interrupt process.

DI Resets the Interrupt Enable flip-flop and disables the interrupt.

These notes are taken from and distributed through BSC CS CU Study Notes
Interrupts in 8085 can be described in terms of the following 8 steps.

1. Set the Interrupt Enable flipflop using EI instruction.

2. During the execution of each instruction, the microprocessor checks the INTR signal.
3. If INTR is high and interrupt is enabled, then the microprocessor disables the Interrupt Enable flipflop and
sends an Interrupt Acknowledge signal ̅̅̅̅̅̅̅
𝐼𝑁𝑇𝐴.
̅̅̅̅̅̅̅ signal inserts a RST instruction through external hardware.
4. This 𝐼𝑁𝑇𝐴
5. Once the RST instruction is received, the microprocessor saves the contents of PC into the stack.
6. The program control is then transferred to a specific memory location and the corresponding service routine
is executed.
7. The service routine should include the instruction EI.
8. Once the service routine has completed executing, the RET instruction retrieves the memory address the
where the program was interrupted and continues the execution.

Types of Interrupts

Maskable and Non-Maskable Interrupts

An interrupt that can be disabled by writing some instructions is referred to as a Maskable Interrupt; otherwise,
it is referred to as a Non-Maskable Interrupt.

Software Interrupts

A software interrupt is a set of instructions that can be inserted into the programme at any time. The 8085
microprocessor has eight software interrupts from RST0 through RST7. The INT instruction is used to initiate a
software interrupt. This event immediately terminates programme execution and transfers control to the INT
handler. The INT handler is typically part of the operating system and decides the appropriate action. This occurs
when an application software terminates or requests specific services from the operating system.

They enable the microprocessor to switch programme control from the main program to the subroutine program.
When the subroutine program is finished, the program control returns to the main program.

Hardware Interrupts

A hardware interrupt is caused by a hardware device, such as a request to start an I/O, a hardware failure, or
something similar. Hardware interrupts were implemented to avoid spending the processor’s crucial time in
polling loops waiting for external events.

There are 5 pins available for hardware interrupt in 8085: TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR.

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Below listed portions of the 3rd module are missing in this pdf.

5. Interfacing peripheral devices

5.1. The intel 8255A PPI

5.2. The intel 8253/8254 Interval timer

These notes are taken from and distributed through BSC CS CU Study Notes
5.3. 8237 Programmable DMA controller

5.3.1. The intel 8237 DMA Controller

These notes are taken from and distributed through BSC CS CU Study Notes