Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

1. Inverting amplifier so vout/vin = –R2/R1.

(a) vout = –100(5)/100 = –5 V

(b) vout = –200R1/R1 = –200 V

(c) vout = –47(20sin 5t)/ 4.7 = –200 sin 5t V

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

2. Inverting amplifier so vout/vin = –R2/R1.

P100 = (vout)2/100

R2/R1 vout (V) P100 (W)

(a) 0.5 –2 0.04

(b) 22 –88 77.44

(c) 101/100 –404/100 0.163

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

3. Non-inverting op amp so vout/vin = 1 + R1/R2

(a) vout = (1 + 1)(5) = 10 V

(b) vout = (1 + 0.1)(2) = 2.20 V

(c) R1 = 1000  is okay, but R2 = 0 leads to shorting of voltage source. Thus, vout = 0.

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

4.
We know that the current flowing at input terminals is zero.

We can determine the current at the output terminal by finding vout and writing a KCL
expression.

We can find vout by writing a KCL expression at the inverting input terminal.
vin vin - vout
+ =0
R2 R1
æ R ö
vout = ç 1+ 1 ÷ vin
è R2 ø
vout = 3 V

Note that this is a non-inverting amplifier.

KCL at the output, with current direction defined exiting the output terminal:
v -v v
iout = out in + out
R1 RL
3 - 0.5 3
iout = +
500 50
iout = 65 mA

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

5.
<Design>
One possible solution:

(a) Need “gain” of 4/9. This is not possible in a noninverting configuration so we choose
an inverting amplifier with Rf/R1 = 4/9. Selecting Rf = 4 k yields R1 = 9 k.

(b) We have a source 9 cos 5t V with its negative terminal grounded and its positive
terminal connected to R1. Then vout = (-4/9)(9 cos 5t) = -4 cos 5t V.

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

6.
<Design> One possible solution:

Since attenuation is required, only an inverting amplifier is appropriate. Thus, we need

Rf/R1 = 5/9. For standard 10% resistor values, selecting Rf = 10  leads to R1 = 18 .

Next, connect the negative terminal of a 9 V source to R1, and ground the positive
terminal of the source.

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

7.
The feedback resistor is R1, so vout = (1 + R1/R2)vin

We want P = 5 W = vout2/RL
vout2 = (1 + 50/R2)2vin2 = 250
æ 250 ö
R2 = 50 ç -1÷
è v in ø

(a) R2 = 23.12 

(b) R2 = 5.241 

Now we need (1 + 50/R2)2vin2 = 110

(c) 45.55 ; 8.344 

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

8.
In this configuration, we see that the inverting terminal is grounded, and no current flows
through Rp, therefore all of iin flows through R3. Alternatively, a source transformation
yields vin = Rpiin, with a series resistance connection of Rp, equivalent to an inverting
amplifier.

vout = –(R3/Rp)vin = –R3iin

(a) –1 V

(b) –17.0 V

(c) Regardless of component values chosen above, the circuit is electrically equivalent to
the inverting amplifer circuit.

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

9.
<Design> One possible solution:

(a) Implement the circuit shown below, with Rf = 2 k and R1 = 1 k.

(b) vout = – (Rf/R1)(v1 + v2) = –2(v1 + v2).

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

10.
<Design> One possible solution: Define v1, v2, v3 as being with respect to ground (i.e.
think of them as nodal voltages, with ground as the reference).

(a) Implement the following, with all resistors as 1 . Define i as upwards through RL.

(b) vout = -(Rf/R)(v1 + v2 + v3) = -(v1 + v2 + v3)

i = -vout/RL = v1 + v2 + v3

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

11.
<Design> One possible solution: change the choice of resistors to “and” instead of “or”
(a) Implement the circuit below, with all resistors equal to 1.5 k.
That’s done by using two of the 1.5 k resistors, three 500  resistors in series, and 4
6 k resistors in parallel.

j
(b) This is a classic difference amplifier with vout = v2 – v1, since all resistor values are
equal.

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

12.
Define the unknown node voltage v1 at the positive terminal of vx. Write KCL equations
at v1 and the inverting input terminal of the op amp. Note that the voltage at the inverting
terminal of the op amp is given by the dependent source as 3vx

v1 - 3vx v1 - vo
1+ + =0
8 10
3vx 3vx - v1
+ -1 = 0
4 8
The node voltages are related by vx = v1 − vo

Substituting and solving, we get that both v1 = −8 V and vo = −8 V!

vo 8
io = = - = -1.333 A
6 6

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

13. The two 850  resistors may be combined to 1700 . Peform a source transformation on
the current source so that a 10 V source is in series with 10 k, connected to the non-
inverting input.
No current flows through the 1 M so it is neglected.

By KCL, 0 = (10 – 9)/100 + (10 – V1)/1700

Solving, V1 = 27.0 V

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

14.
Using nodal analysis,

v− − v+ v− − vout
0= +
R1 Rf
R3
v+ = v2  since v+ = v−
R2 + R3
 R3   R3 
  v2 − v1   v2 − vout
 R2 + R3  +  R2 + R3 
=0
R1 Rf
Solving for vout leads to:

 Rf   R3  Rf
vout =  + 1   v2 − v1
 R1  R2 + R3  R1

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

15.
(a) No current can flow into either input pin of an ideal op amp.

(b) There can be no voltage difference between the input pins of an ideal op amp.

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

16.
We have a non-inverting amplifier so with the assistance of a source transformation,
 Rf   500 
 ( − Ry I s ) =  1 + ( )( )
−3
vout = 1 +  4.7 10 2 10 = –14 V
3

 Rx   1000 

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

17.
Noting that the voltage at the non-inverting terminal will be given by –RyIs,

æ R ö
(
vout = ç 1+ f ÷ - Ry I s
è Rx ø
)
æ R ö
(
2 = ç 1+ f ÷ (500 ) 1.667 ´ 10 -3
è 250 ø
)
Solving,

Rf = 350 

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

18.
Noting that the output stage is an inverting amplifier,
1k 10
vp = vs = vs
1k +100 11
æ 3ö
( )( )
vout = - ç ÷ -10-3 vp 1000 = -3vp = - vs
è 1ø
30
11

(a) –5.4545 cos 100t mV

(b) –5.4545 sin (4t + 19o) V

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

19.
The first stage is an inverting amplifer which puts (2)(-5/10) = -1 V across the 10 
resistor.

The second stage is also an inverting amplifer, which multiplies the voltage across the 10
 resistor (-1 V) by -2000/Rx.

Thus, vout = (-2000/Rx)(-1) = 2 V

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

20.
Left stage is an inverting amplifer with gain -5/10 hence (-5/10)(2) = -1 V appears across
the 10  resistor.

The right hand stage is also an inverting amplifer, now with gain -2000/Rx (Rx in ohms).

Thus, vout = (-1)(-2000/Rx) = 10 so Rx = 200 

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

21.
The left-hand stage provides (1 + 15/10)vin = 2.5vin to the second stage.

Hence, the second stage provides an output voltage (-5000/R4)(2.5vin)

(a)
15

10

5
vout (V)

-5

-10

-15
-2 -1.5 -1 -0.5 0 0.5 1 1.5 2
vin (V)

(b)
0

-0.5

-1

-1.5
vout (V)

-2

-2.5

-3

-3.5

-4
1000 2000 3000 4000 5000 6000 7000 8000 9000 10000
R4 (ohms)

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

22.
(a) Use dc sweep of Vin, plot V(out)

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

(b) Step parameter R4, plot V(out)

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

23. On the right we have a difference amplifier where vout = v1 – vleft

(vleft = output of left-hand stage).

So, vleft = (1.5)(-1500/500) = -4.5 V

Hence, vout =

(a) 0 – (-4.5) = 4.5 V

(b) 1 – (-4.5) = 5.5 V

(c) -5 – (-4.5) = -0.5 V

(d) 2sin100t + 4.5 V

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

24.
In this configuration, we are combining the two circuits of Figs. 6.49 and 6.50, resulting
in four stages (numbered from left to right, starting with Fig. 6.49).

Stage 1 delivers vin(1 + 15/10) = 2.5vin to stage 2

Stage 2 delivers (-5000/2000)(2.5vin) = -6.25vin to stage 3

Stage 3 delivers (-1500/500)(-6.25vin) = 18.75vin to stage 4

Stage 4 delivers v1 – 18.75vin = vout

Thus,

(a) vout = 1 – 37.5 = -36.5 V

(b) vout = -18.75 V

(c) vout = -1 – 18.75 = -19.75 V

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

25.
The last stage is merely a buffer and has no effect on the output.
The remainder is a summing amplifier with (defining Rf = 200 k),

0 − v1 0 − v2 0 − v3 0 − vout
0= + + +
R1 R2 R3 Rf
v v v  v v v 
Solving, vout = − R f  1 + 2 + 3  = −200 103  1 + 2 + 3 
 R1 R2 R3   R1 R2 R3 

(a) vout = -30.8 V

(b) vout = 0.8 V

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

26.
<Design> One possible solution:

(a) Max sensor voltage = 5 V

Max summed voltage = 15 V
Adjust to obtain 2 V output when all three inputs are 3 V.

We take a summing amplifier with all resistor values set to 1 . This output is fed
into an inverting amplifer with R1 = 15  and feedback resistor Rf = 2 

(b) The first stage provides a voltage equal to –(v1 + v2 + v3).

This is multiplied by -2/15 by the second stage.

Check: When v1 = v2 = v3 = 0, vout = (-2/15)(0) = 0 (Ok)

When v1 = v2 = v3 = 5 V, vout = (-2/15)[-(5 + 5 + 5)] = 2 V (Ok)

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

27.
<Design> One possible solution:

(a) We start with a difference amplifer as shown in Table 6.1 with all resistors set to 1
k, but with v2 designated as the input voltage to the inverting input and v1 to the
noninverting input. The output of this stage is taken to the input of an inverting
amplifer with R1 = 1 k and Rf = 10 k

(b) vout = (-Rf/R1)(v1 – v2) = 10 (v2 – v1).

For v1 = v2, vout = 0; for v1 – v2 = 1 the output is 10 V.

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

28.
<Design> One possible solution:

(a) Maximum = 400,000 kg = 10 V

Sensor: 10 V = 1 kg therefore 400,000 kg on one sensor yields 4 V

We take a general summing amplifier with all resistors set to 1 k. The output of this
stage is taken as the input voltage to an inverting amplifier with R1 = 4 k and Rf = 10
k.

(b) The first stage sums the three sensor voltages v1, v2 and v3 to obtain –(v1 + v2 + v3)
at the input to the second stage. The second stage multiplies this voltage by -2.5.
If v1 + v2 + v3 = 4 V (400,000 kg total), vout = -2.5(-4) = 10 V.

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

29. <Design> One possible solution:

(a) Designate the tank sensor output voltages as v1, v2, v3, v4. Each has a maximum
value of 5 V. We desire 3 V when their sum is 20 V, and 1.5 V when their sum is
zero.

Thus, we need a dc offset in addition to an adjusted sum of these voltages.

(b) The first stage sums the sensor voltages and attenuates the result such that -1.5 V is
obtained at the stage output when each sensor voltage is 5 V. The second stage adds
the necessary dc offset and inverts the sign of the output voltage. Thus, when all input
voltages are equal to zero, vout = (-1)(0 – 1.5) = 1.5 V.
When all voltages are 5 V, vout = (-1)[-(75)(5 + 5 + 5 + 5)/1000 – 1.5) = 3 V

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

30.
The left-hand stage is an inverting amplifier with output voltage vout = -(R2/R1)vin.

The middle stage is an inverting amplifier with output –(200/50)(-R2/R1)vin. The value
of R3 is not critical, but needs to be sufficiently greater than zero.

The last stage is a voltage follower and so does not affect the output voltage.

Thus, 4 = -(200/50)(-R2/R1)(8)

One possible solution:

Arbitrarily set R1 = 8 k. Then R2 = 1 k. Arbitrarily set R3 = 1 k.

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

31. The left-hand stage is a general difference amplifier. The right-hand stage is a simple
inverting amplifier, which multiplies the output of the difference amplifier by

æ R ö
vout = ç 1+ 6 ÷ vout left-hand stage
è R5 ø

Analyzing the left-hand stage then:

æ R3 ö
v- = v+ = vin ç ÷
è R2 + R3 ø

v- - vout left-hand stage v- -1

So 0 = +
R4 R1

Substituting and solving for vout yields

æ R ö éæ 1 1 ö æ R3 ö 1ù
vout = R4 ç 1+ 6 ÷ êç + ÷ ç ÷ vin - ú
è R5 ø êëè R1 R4 ø è R2 + R3 ø R1 úû

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

32.
Start with KCL at the inverting terminal of the left stage, noting that the terminal voltage
is zero. Label the node voltage at the output of the left stage as vx. Write a second KCL
equation for the noninverting terminal of the right stage.

0 - 5 0 - vx 0 - vout
0= + +
3k 6k 15k
vx - vout vx
0= +
9k 12k

Solving,

vx = -5.882 V

vout = -10.294 V

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

33.
Write a KCL expression at the inverting terminal of the left stage, noting that the terminal
voltage is defined as +1V. Label the node voltage at the output of the left stage (and input
to the right stage) as vx.

1- ( -1) 1- vx 1- vo
0= + +
4.2k 6k 2k

Write a KCL expression at the inverting terminal of the right stage

vx -1 vx - vo
0= +
7.2k 5.4k

Solving,

vx = 1.4571 V

vo = 1.8 V

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

34.
<Design> One possible solution:

 −1 V, no finger (R  10 M)
Desired: vout = 
+1 V, finger present (R < 10 M)

We employ a voltage divider and a 1 V reference into a comparator circuit. With no

finger present, a voltage greater than 1 V appears at the inverting input, so that the output
voltage is -1 V. With the finger present, the voltage at the inverting input will drop below
50% of the driving voltage (2 V), so that +1 voltage will appear at the output.

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

35.
The voltage at the inverting terminal of the op amp is given by a voltage divider
Rsensor
v- = ( 5 V)
100 + Rsensor

The output voltage of the comparator will be

ìï -5 V; v- > 2 V
vout = í
ïî +5 V; v- < 2 V

We therefore need to find the temperature where v− = 2 V

Rsensor = 66.67 W
T = −16.67 °C

As temperature decreases, the sensor resistance decreases, and v- decreases.

Therefore,

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

36.
<Design> One possible solution:

We build a two-stage circuit where a comparator has vin applied to its non-inverting
input, and a 1 V reference to the inverting input. The output of this stage is 0 V when vin
> 1 V and -1.3 V otherwise. This is summed with a -1.2 V reference source, the output of
which is inverted and so is either +2.5 V for vin > 1 V or +1.2 V otherwise.

vin

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

37.
This comparator circuit will switch between the supply voltages of 0 V and +18 V. The
output will be vout = 0 V when vactive < vref , and vout = +18 V when vactive > vref .

(a) For vref = −3 V

(b) For vref = +3 V

20
v out (V); v ref =-3V

15

10

0
-5 -4 -3 -2 -1 0 1 2 3 4 5

20
v out (V); v ref =+3V

15

10

0
-5 -4 -3 -2 -1 0 1 2 3 4 5
v active (V)

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

38.
This comparator circuit will switch between the supply voltages of −5 V and +5 V. The
output will be vout = −5 V when v2 < v1 , and vout = +5 V when v2 > v1 .

4
v out (V); v 2 =2V

-2

-4

-6
-5 -4 -3 -2 -1 0 1 2 3 4 5
v 1 (V)

4
v out (V); v 1 =2V

-2

-4

-6
-5 -4 -3 -2 -1 0 1 2 3 4 5
v 2 (V)

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

39. We have a comparator circuit with zero reference tied to the inverting input, and matched
12 V supplies. The expected (ideal) output is therefore:

vout (V)

12

vactive (V)

–12

Simulating using a A741 results in the following, which exhibits the expected shape
with only a slight reduction in maximum and minimum voltages:

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

40.
<Design> One possible solution:

This comparator circuit follows the negative supply voltage (0 V) until vin exceeds 1.5 V,
at which point 5 V appears at the output.

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

41.
<Design>
One possible solution:
Place the temperature sensor in a voltage divider to define the input to an inverting
comparator Schmitt trigger, such as shown in Fig. 6.25. First, calculate the resistance for
the temperatures where the alarm should be tripped:

At 100oC: RT = Rnax = 80[1+0.004(100-25)] = 104 Ω

At 10oC: RT = Rmin = 80[1+0.004(10-25)] = 75.2 Ω

The lower threshold will switch when the temperature exceeds 100oC, or R increases
above 104 Ω. The upper threshold will switch when the temperature drops below 10 oC,
or R decreases below 75.2 Ω.

Using a voltage divider between the ±5 V supplies, we can find a value where the voltage
of the divider is symmetric about zero for the temperature sensor resistor values of Rmin =
75.2 Ω and Rmax = 104 Ω.

The voltage at the divider can be written by KCL as

vx - 5 vx + 5
+ =0
RT R
æ 1 1ö
çè R - R ÷ø
vx = 5 T
æ 1 1ö
çè R + R ÷ø
T
lower
We want −VT =VTupper = vx
æ 1 1ö
çè R - R ÷ø
VTlower = 5 max = -vx
æ 1 1ö
çè R + R ÷ø
max

æ 1 1ö
çè R - R ÷ø
VTupper = 5 min = +vx
æ 1 1ö
çè R + R ÷ø
min

Solving, we get vx = 0.4045 V and R = 88.44 Ω

Now we need to choose values for the feedback resistors for the Schmitt trigger

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

R1
VTlower = -5 = -0.4045 V
R1 + R2
R1
VTupper = +5 = +0.4045 V
R1 + R2
Choose
R1 = 1 kΩ
R2 = 11.36 kΩ

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

42.
Writing KCL at the non-inverting op amp terminal, and labeling the terminal voltage Vx,
Vx - vin Vx Vx - vout
+ + =0
R1 R2 R3
æ 1 1 1ö v v
Vx ç + + ÷ = in + out
è R1 R2 R3 ø R1 R3
The output switches between Vs and 0 V, where the trigger points will occur when the
voltage at Vx = vref. Substituting Vx = vref and solving for vin
æ 1 1 1ö R
vin = vref R1 ç + + ÷ - vout 1
è R1 R2 R3 ø R3

æ R Rö R
vin = vref ç 1+ 1 + 1 ÷ - vout 1
è R2 R3 ø R3
For vout =0 V,
æ R Rö
vin = VTupper = vref ç 1+ 1 + 1 ÷
è R2 R3 ø
For vout = Vs,
æ R Rö R
vin = VTlower = vref ç 1+ 1 + 1 ÷ -Vs 1
è R2 R3 ø R3

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

43.
<Design> One possible solution

From problem definition, VS = 5 V

æ R Rö
VTupper = vref ç 1+ 1 + 1 ÷
è R2 R3 ø
æ R Rö R
VTlower = vref ç 1+ 1 + 1 ÷ - Vs 1
è R2 R3 ø R3
R1
VTlower = VTupper - Vs
R3
R1/R3 = 3/5

Choose
R1 = 3 kΩ
R3 = 5 kΩ
Need to find R2 and vref
æ R Rö æ 3k 3ö
VTupper = vref ç 1+ 1 + 1 ÷ = vref ç 1+ R + 5 ÷ = 4 V
è R2 R3 ø è 2 ø
Choosing vref = 1 V, R2 = 1.25 kΩ

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

44.
<Design> One possible solution

The voltage output will range from -2 to + 2 V for a low output, and +3 to +7 V for a
high output. Choose a Schmitt trigger as shown in Fig. 6.60, with the following
parameters:

R1 = 1 kΩ
R2 = 500 Ω
R3 = 2 kΩ
vref = 1 V

These values provide lower and upper thresholds at 1 and 3.5 V, respectively.

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

45.
<Design> One possible solution

The voltage output will range from -2 to + 2 V for a low output, and +3 to +7 V for a
high output. Choose a Schmitt trigger as shown in Figure 6.60, with the following
parameters:

R1 = 1 kΩ
R2 = 500 Ω
R3 = 2 kΩ
vref = 1 V

These values provide lower and upper thresholds at 1 and 3.5 V, respectively.

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

46.
From Eq. [23],

R4  1 + R2 R1  R2
vout =   v+ − v−
R3  1 + R4 R3  R1
The differential input is v+ − v− and hence the differential gain is
R4  1 + R2 R1  R2
  v+ − v−
R 1 + R4 R3 
Adm = out = 3 
v R1
v+ − v− v+ − v−
For common mode components we must average the inputs, and hence the common-
mode gain is
R4  1 + R2 R1  R2
  v+ − v−
R 1 + R4 R3 
Acm = 2 out = ( 2 ) 3 
v R1
v+ + v− v+ + v−
Adm
CMRR is defined as the absolute value of their ratio: CMRR = .
Acm

(a) R1 = R3 and R2 = R4 . Eq. [1] above reduces to R2/R1.

R2  v+ − v−  v+ + v−
Eq. [2] above reduces to Acm = 2   . Thus, CMRR = .
R1  v+ + v−  2 ( v+ − v− )

v+ + v−
(b) All resistors are different. Then the above reduces to CMRR =
2 ( v+ − v− )

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

47.
<Design>

We note that the short circuit should not appear across the + and – terminals of vout as it
appears in the first printing.

(a) We designate the bottom node as the reference node, then name the top node V in, the
node at the “+” terminal of Vout as VA, and the remaining node VB.
R2 R3
By voltage division, VA = Vref and VB = Vref . Thus,
R1 + R2 R3 + RGauge
 R2 R3 
Vout = VA − VB = Vin  − .
 R1 + R2 R3 + RGauge 

(b) Set all four resistors equal; specify as RG. Then,

 R R 
Vout = Vin  G − G  = 0
 2 RG RG 

(c) One possible solution:

Connect -12 V to pin 4; connect +12 V to pin 7. Ground pin 2.
Employ a bridge circuit such as the one shown in Fig. 6.60(a) with the strain gauge in
place of RGauge and all other resistors precisely 5000 . Connect four 12 V supplies in
series to botain Vin = 48 V. Then Vout = Vin(2.5×10-6) = 1.2×10-4 V. A 1 V signal
requires a gain of 1/1.2×10-4 = 8333.

This value is in excess of our maximum gain of 1000 so connect a resistor having
50.5 103
value = 50.55  across pins 1 and 8. This provides a gain of 1000.
1000 − 1

The voltage Vout is connected across pins 3 and 2 with the “+” reference at pin 3. We
still require a gain of 8.333 so connect the pin 6 output to the non-inverting terminal
of a non-inverting amplifer powered by ±12 V supplies. Then, set R1 = 1 k and Rf =
7.333 k. This completes the design.

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

48.
(a) Employing nodal analysis,

−vd + 0.45 −vd + 0.45 − vout vd

0= + −
250 1400 2 106
v + v − 0.45 vout + 2 105 vd
0 = out d +
1400 75

Solving, vout = 2.970 V

(b) The ideal model predicts vout = (0.45)(1 + 1400/250) = 2.970 V

Thus, the ideal model is accurate to better than 0.1%.

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

49.
We identify the non-grounded side of the 250  with the nodal voltage vm., and assume
zero output resistance and infinite input resistance.
v 1400
For an ideal op amp, out = 1 + = 6.60
0.45 250

Applying nodal analysis to the detailed model,

−vd + 0.45 −vd + 0.45 − Avd

0= +
250 1400
14.85 A
which can be solved to obtain Avd = .
5 A + 33

Thus, 2% of the ideal (closed-loop) value is

(0.98)(6.60) = Avd/0.45 and so Amin = 323

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

50.
By nodal analysis,
−v + 0.45 −vd + 0.45 − vout −vd
0= d + +
250 1400 Rin
v + v − 0.45 vout − Avd
0 = out d +
1400 Ro

Solving,

Finally, we note the input bias current is simply vd/Rin.

(a) A741: vd = 18.6 V; input bias current = 9.31 pA

(b) LF411: vd = 2.98 V; input bias current = 2.98 aA

(c) AD549K: vd = 31.2 V; input bias current = 0.312 aA

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

51.
(a) Employing nodal analysis and defining nodal voltages v- and v+ at the input,

v− − 2 v− − vout v− − v+
0= + +
1500 1500 2 106
v −5 v v −v
0= + + + + + −6
1500 1500 2  10
vout − v− vout − 2 105 vd vout
0= + +
1500 75 RL
vd = v+ − v−

Solving,
1.067 104 RL
vout =
3.556 103 RL + 2.669

(b) The ideal model predicts vout = 5 – 2 = 3 V

We note that for any appreciable value of RL, the exact model reduces to

(1.067×104)/(3.56×103) = 3.0006 V

so in this situation the ideal model is better than 0.1% accurate.

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

52.
(a) Using the ideal op amp model, we end up with an ideal voltage follower so the output
is vout = 2 V.

(b) Using parameters for a 741 op amp in conjunction with nodal analysis,

vout v − 2 v − 2 105 vd
0= + out 6 + out
4700 2 10 75
−2 + vd + vout = 0

Solving, vout = 1.99999 V

(c) LTspice simulation:

(d) All three agree to at least four decimal places, so the ideal model is adequate in this
instance.

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

53.
(a) This non-inverting amplifer has a gain of 1 + 470/4700 = 1.1
We therefore expect an output of (1.1)(2) = 2.2 V

The output voltage cannot exceed the supply voltage, or 9 V in this case.
Thus, (1 + Rf/4700)(2) = 9

Solving, Rfmax = 16.45 k

(c) Using LT1001 and a parameter sweep for the resistance, we see that the maximum
output voltage achieved is 8.05 V, with a feedback resistor value of 14.45 k .

Rfmax = 14.5 k

Real op amps such as the LT1001 cannot provide the full voltage range of the
supplies, where saturation typically occurs approximately 1 V from the supply
voltage.

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

54.
The common mode output will be ‘rejected’ by the ratio of CMRR

∆𝑉𝑖𝑛,𝐶𝑀
∆𝑉𝑜𝑢𝑡,𝐶𝑀 = 𝐶𝑀𝑅𝑅

The CMRR is given in the decibel scale:

μA741: 90 dB = 1090/20 =3.16×104
LM324: 85 dB = 1085/20 = 1.78×104
LT1001: 110 dB =10110/20 = 3.16×105

μA741: ΔVout = 5/3.16×104 = 158 μV

LM324: ΔVout = 5/1.78×104= 281 μV
LT1001: ΔVout = 5/3.16×105= 15.8 μV

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

55.
Define nodeal voltages v- and v+ at the op amp input terminals. Then

v− − v2 v− − vout
0= +
R1 R2
v −v v v −v
0 = + 1 + + + + out
R3 RL R4
With an ideal op amp, v- = v+.

Solving, vout =
( R1R4 RL + R2 R4 RL ) v1 − ( R2 R3 R4 + R2 R3 RL + R2 R4 RL )v2
R1 R3 R4 + R1 R4 RL − R2 R3 RL

v+ R1 R4 v1 − R2 R3v2
And I L = =
RL R1 R3 R4 + R1 R4 RL − R2 R3 RL

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

56.
Define two nodal voltages vm and vp at the inverting and non-inverting input terminals,
respectively. For an ideal op amp, vm = vp. Then,

vp v p − vout
0= +
1000500
v p − v1
v p v p − vout
0= + +
1000 100 500

Solving, vp = v1/10 and IL = vp/100 = v1/1000 (independent of RL)

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

57.
<Design> One possible solution:

(a) RTH of the switch = 5/1×10-3 = 5 k

We thus need a circuit with minimum gain 5/0.25 = 20
Select a non-inverting amplifer circuit. Connect the microphone to the non-inverting
input terminal, select R1 = 1 k and so Rf = 19 k.

(b) Although general speaking may not correspond to peak microphone voltage, we are
not provided sufficient information to address this, and note that the gain may need
adjusting in the final circuit.
Thus, we should connect the feedback resistor Rf in series with a variable 20 k
resistor, initially set to 0 . This will allow us to vary the actual gain between 1 +
Rf/R1 = 1 + 19/1 = 20 and 1 + 39/1 = 40.

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

58.
<Design> One possible solution:

We employ a summing amplifer such as that shown in Table 6.1, but with 5 inputs. We
model each microphone as an ideal voltage source and connect a resistor R1, R2 etc with
each.

We set R1 = R2 = R3 = R4 = 1 k and Rf = 10 k

The lead singer’s microphone is then connected in series with R5 = 10 k.

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

59.
<Design> One possible solution:

Rf(dark) = 100 k; Rf(light) = 10 k, measured at 6 candela.

Deliver 1.5 V to RL

Arbitrarily, select Vs = 1 V.
Assume the resistance scales linearly with light intensity, so
 100 103 − 10 103 
R f ( 2 candela ) =   (2) + 100 10 = 70 k
3

 0 − 6 
With Rf = 70 k and vout = (1 + Rf/R1)Vs = 1.5, R1 = 2Rf = 140 k

Check:
0 candela leads to Rf = 100 k, so vout = (1 + 100/140)(1) = 1.7 V and it will not activate.
6 candela leads to Rf = 10 k so vout = (1 + 10/140)(1) = 1.07 V and it will activate.

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

60.
<Design> One possible solution:

Use a Schmitt trigger with two positive thresholds.

The resistance values for the triggers are

R = 2000e-200/500 = 1,340.6 W at 200 lux
R = 2000e-1000/500 = 270.67 W at 1000 lux

You desire a high voltage output when R>1340.6 Ω to turn lights on

And a low voltage output when R<270.67 Ω to turn lights on

Use a voltage divider, input into a buffer circuit, and then input into the Schmitt trigger.

Selecting a resistance of 1 kΩ for the voltage divider, the threshold voltages are:

VTupper = 2.8638 V
VTlower = 1.0651 V
The relations for the Schmitt trigger will define the other circuit values
æ R Rö
VTupper = vref ç 1+ 1 + 1 ÷
è R2 R3 ø
æ R Rö R
VTlower = vref ç 1+ 1 + 1 ÷ - Vs 1
è R2 R3 ø R3
R1
VTlower = VTupper - Vs
R3
Selecting R1 = 1 kΩ and VS = 5 V
R3 = 2.78 kΩ

Need to find R2 and vref

æ R Rö æ 3k 3ö
VTupper = vref ç 1+ 1 + 1 ÷ = vref ç 1+ R + 5 ÷ = 4 V
è R2 R3 ø è 2 ø
Choosing vref = 1 V, R2 = 665 Ω

The resulting schematic and component values are shown below:

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

61.
<Design> One Possible Solution:

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

62.
<Design> One possible solution:

When the wind velocity exceeds 50 km/h, the fountain height must be ≤ 2 m.

We assume the valve position tracks the applied voltage linearly (e.g. 2.5 V corresponds
to 50% open). We also assume the flow rate scales linearly with the valve position.

So, 2 m height corresponds to 5 - (2/5)(5) = 3 V applied to the valve.

Description: When the sensor voltage is above 2 V, corresponding to a wind velocity

greater than 50 km/h, the comparator stage outputs 0 V. This is summed with –3 V, the
sign of which is inverted by the second stage to yield 3 V, or 2 m height. When the sensor
voltage drops below 2 V, the comparator stage output is –2 V. This is summed with –3 V
and the sign inverted, or 5 V output, corresponding to the valve fully open, which is
presumably 100 l/s flow rate.

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

63.
The schematic and resulting output for the precision LT1001 is shown in the following,
assuming the worst case DC voltage of 5 V.

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

For the 741,

We see that the CMRR is excellent for the LT1001, while a clear common mode signal is
observed for the 741. A DC value of only 226 nV results for the circuit with LT1001,
while a DC value of -13.69 mV is observed for the 741 (which is more than 10% of the
AC amplitude).
Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.
 Engineering Circuit Analysis 9th Edition Chapter Six Exercise Solutions

64.
By nodal analysis,
v −v v −v
0 = m 1 + m out
R R
R v2
vm = v2 =
2R 2
Consequently,
0.5v2 − v1 0.5v2 − vout
0= + and vout = v2 – v1. Thus, the resistor value is unimportant.
R R
(a) (b)
8 1

0.8
6

0.6
4
0.4
2
0.2

vout (V)
vout (V)

0
0

-2
-0.2

-4 -0.4

-6 -0.6

-8 -0.8
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
t (s)
t (s)

(c)
-1

-1.1

-1.2

-1.3

-1.4
vout (V)

-1.5

-1.6

-1.7

-1.8

-1.9

-2
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
t (s)

Copyright ©2018 McGraw-Hill Higher Education. Permission required for reproduction or display. All rights reserved.