1.

Memory Hierarchy

●​ Definition: Memory hierarchy organizes computer memory by speed, cost, and size
to optimize performance. It includes registers, cache, main memory, and auxiliary
memory.
●​ Key Points:
○​ Registers: Fastest, smallest, inside CPU (e.g., store temporary data).
○​ Cache: SRAM-based, fast, stores frequently used data.
○​ Main Memory: RAM/ROM, moderate speed, stores active programs.
○​ Auxiliary Memory: HDD/SSD, slowest, largest, non-volatile.
○​ Purpose: Balances speed (expensive, small) and capacity (cheap, large).
●​ Diagram: Draw a pyramid:
○​ Top: Registers (e.g., 100 bytes, <1 ns).
○​ Middle: Cache (e.g., 1 MB, 1–10 ns), Main Memory (e.g., 8 GB, 10–100 ns).
○​ Bottom: Auxiliary Memory (e.g., 1 TB, ms).
●​ Exam Tip: For “Explain memory hierarchy” (potential 5-mark question), write 100
words: Define, list components, explain speed/size trade-off, draw pyramid.
●​ Past Paper Link: Q1(ix) (“A memory that is part of a control unit is referred to as a
___ memory”) relates to control memory, a specialized part of the hierarchy. Answer:
Control Memory.

2. Main Memory

●​ Definition: Main memory (primary memory) is volatile storage (except ROM) directly
accessed by the CPU to store active programs and data.
●​ Key Points:
○​ Types: RAM (read/write, volatile) and ROM (read-only, non-volatile).
○​ Role: Holds data/instructions during execution.
○​ Example: 8 GB DDR4 RAM in a laptop.
●​ Exam Tip: Define main memory in 50 words, mention RAM/ROM, and contrast with
cache (faster) and auxiliary (slower).

3. Types of Main Memory

●​ RAM (Random Access Memory):

○​ Definition: Volatile, read/write memory for temporary data storage.
○​ Types:
■​ SRAM (Static RAM): Uses flip-flops, fast, used in cache.
■​ DRAM (Dynamic RAM): Uses capacitors, slower, used in main
memory.
○​ Example: DDR4 DRAM in PCs.
●​ ROM (Read-Only Memory):
○​ Definition: Non-volatile, stores firmware.
○​ Types:
■​ PROM: Programmed once.
■​ EPROM: Erasable with UV light.
■​ EEPROM: Electrically erasable (e.g., BIOS).
○​ Example: EEPROM in USB drives.
 ●​ Exam Tip: For “List types of main memory” (2–3 marks), write: “Main memory
includes RAM (SRAM, DRAM) and ROM (PROM, EPROM, EEPROM).” Add one
example each.

4. Difference Between SRAM and DRAM

Feature SRAM (Static RAM) DRAM (Dynamic RAM)

Storage Flip-flops (6 transistors/bit) Capacitors (1 transistor + capacitor/bit)

Speed Faster (no refresh) Slower (needs refreshing)

Power Lower Higher (refresh cycles)

Cost Expensive Cheaper

Use Cache, registers Main memory (e.g., DDR4)

Stability Stable Less stable (refreshes every ms)

●​ Exam Tip: For “Compare SRAM and DRAM” (5 marks), use a table (100 words).
Mention: SRAM for cache, DRAM for main memory. Past paper may test this
indirectly via cache questions (Q10).

5. Cache Memory

●​ Definition: Fast SRAM-based memory near the CPU, storing frequently accessed
data to reduce main memory access time.
●​ Key Points:
○​ Levels: L1 (smallest, fastest), L2, L3 (shared in multi-core CPUs).
○​ Principle: Locality (temporal: recently used; spatial: nearby data).
○​ Example: 256 KB L1 cache in a CPU.
●​ Exam Tip: For “Explain cache memory” (5 marks), write 100 words: Define, mention
levels, explain locality. Past paper Q10 directly relates.

6. Cache Memory Mapping

●​ Direct Mapping:
○​ Each main memory block maps to one cache line (index = block % lines).
○​ Address: Tag + Index + Offset.
○​ Pros: Simple, fast hardware.
○​ Cons: High miss rate.
○​ Diagram: Show blocks (B0, B4) mapped to specific cache lines.
●​ Associative Mapping:
○​ Any block can go to any cache line.
○​ Address: Tag + Offset.
○​ Pros: Flexible, low miss rate.
○​ Cons: Slow, complex search.
○​ Diagram: Show blocks freely placed in cache.
●​ Set Associative Mapping:
 ○​ Blocks map to a set of lines (e.g., 2-way set associative).
○​ Address: Tag + Set + Offset.
○​ Pros: Balances speed and flexibility.
○​ Cons: More complex than direct.
○​ Diagram: Show cache divided into sets, each with multiple lines.
●​ Exam Tip: For Q10 (15 marks), write 150 words per mapping, include a diagram, and
list 1–2 pros/cons. Practice drawing all three mappings.

7. CAM (Content Addressable Memory)

●​ Definition: Memory that searches by content, not address, used in cache for tag
matching.
●​ Key Points:
○​ Operation: Compares input data to all stored data, returns matching address.
○​ Use: Associative mapping (Q10), networking (e.g., MAC tables).
○​ Hardware: Storage cells, comparison logic, match lines.
●​ Exam Tip: For “Explain CAM” (3–5 marks), write 50–100 words: Define, mention use
in cache, give example (tag matching).

8. Virtual Memory

●​ Definition: Creates an illusion of large memory by using auxiliary storage (e.g.,

HDD) as an extension of RAM.
●​ Key Points:
○​ Purpose: Runs large programs, enables multitasking.
○​ Mechanism: Virtual addresses mapped to physical via page table.
○​ Example: 4 GB program on 2 GB RAM using disk swap space.
●​ Exam Tip: For “Explain virtual memory” (5–7 marks), write 150 words, mention
paging/segmentation, draw address mapping.

9. Mapping Using Pages

●​ Definition: Divides memory into fixed-size pages (virtual) and frames (physical),
mapped via a page table.
●​ Key Points:
○​ Virtual address: Page number + Offset.
○​ Page table: Maps page to frame.
○​ Example: 4 KB page, address 8192 = page 2, offset 0.
●​ Diagram: Show virtual address → Page table → Physical address.
●​ Exam Tip: For “Explain paging” (5 marks), write 100 words, include diagram.

10. Page Fault

●​ Definition: Occurs when a requested page is not in RAM, requiring OS to fetch it

from disk.
●​ Key Points:
○​ Process: CPU detects missing page, OS retrieves it, updates page table.
○​ Types: Minor (page in memory, not mapped), Major (page on disk).
○​ Example: Program accesses page on HDD, causing delay.
 ●​ Exam Tip: For “Define page fault” (2–3 marks), write 50 words, mention OS role.

11. Mapping Using Segments

●​ Definition: Divides memory into variable-sized segments (e.g., code, data) mapped
via a segment table.
●​ Key Points:
○​ Address: Segment number + Offset.
○​ Segment table: Stores base address and length.
○​ Pros: Logical division.
○​ Cons: Fragmentation.
●​ Diagram: Show segment table with base/length.
●​ Exam Tip: For “Compare paging and segmentation” (5 marks), write 100 words,
contrast fixed vs. variable size.

12. TLB (Translation Lookaside Buffer)

●​ Definition: Cache for recent page table entries to speed up address translation.
●​ Key Points:
○​ Operation: Stores page-to-frame mappings.
○​ Hit/Miss: TLB hit (fast), TLB miss (access page table).
○​ Example: 64-entry TLB reduces translation time.
●​ Exam Tip: For “Explain TLB” (3–5 marks), write 50–100 words, mention hit/miss.

13. Auxiliary Memory

●​ Definition: Non-volatile, large-capacity storage (e.g., HDD, SSD) for permanent

data.
●​ Key Points:
○​ Types: Magnetic disk (HDD), SSD, optical disk.
○​ Example: 1 TB HDD stores OS and files.
●​ Exam Tip: For “Define auxiliary memory” (2 marks), write 50 words, contrast with
main memory.

14. Diagrammatic Representation of Magnetic Disk & Hard Disk Drive

●​ Structure:
○​ Platters: Magnetic disks storing data.
○​ Tracks: Concentric circles.
○​ Sectors: Smallest storage unit.
○​ Read/Write Head: Reads/writes data.
○​ Actuator Arm: Moves head to track.
●​ Diagram: Draw a platter with tracks/sectors, label head and arm.
●​ Exam Tip: For “Draw HDD structure” (5 marks), sketch and label components,
mention spinning (5400–7200 RPM).

15. Disk Performance Metrics

●​ Seek Time: Time to move head to track (5–10 ms).

●​ Rotational Delay (Latency): Time for sector to rotate under head (4–8 ms, e.g.,
7200 RPM = 8.33 ms/rotation).
●​ Access Time: Seek Time + Rotational Delay (9–18 ms).
●​ Transfer Time: Time to read/write data (depends on MB/s).
●​ Latency: Same as rotational delay in this context.
●​ Exam Tip: For Q1(iii) (“Time to locate data on disk”), answer: Access Time. Write 50
words: “Access time is seek time (head to track) plus rotational delay (sector to
head).”