MID SEM

Harcourt Butler Technical

University Kanpur
B.Tech
Br£nch, Electrical Engineeriug Program
Semester IV
Course Name VLSI Design
2023-24
Course Eode EET 354 Year
Maximum Marks 15
Time: 1:00Hr Answer All Questions
Knowledge K1:Remembering K3:Applying K5:Evaluating
Level(KL) K2:Understanding K4:Analysing K6:Creating
Note: Attempt all questions.
Q.No Questions Marks COs KL
1. .hat are the quality metrics of a digital design? Explain Moore's law in 3+2 COi K3
detail.
Draw the small signal model of diode. Derive the expression of Drift K2
2. CO2
resistance, Drift capacitance and Junction Capacitance.
3. Which Universal Gate is preferred for realization of Boolean expression?
3+2 CO3 K2
Realize given expression by CMOS toplogy.
Y= ABC+B'E'(D+AC)
 UNIVERSITY, KANPUR
HARCOURT BUTLER TECHNICAL
B.Tech.

Mid Semester Examination

Even Semester (VI), 2021-22

EET-354 VLSI Design
Time: 1:30 Hours Max. Marks: 30

Note: 1. Attempt allquestions. Allquestions carry marks, as shown

against them.

Q.1 Assume a wafer size of 12 inches, a die size of 2cm,1 defects /cm and a
=3.Determine the die yield of this process run. [5]

Q.2 (1) Plot andexplain Voltage Transfer Curve (VTC) of a CMOS inverter.

(i) Label VoH. VoL, VH., Vn., VM on the plot . alsoexplain significance
of these parameters.

(ii) What is Noise Margin High and Noise Margin Low.

(iv) Write code for obtaining VTC of CMOS Inverter with NMOS (L= 0.25 u
W= 10 u, PMOS (L= 0.25 u W= 30 u) Vdd= 2.5 V (2]
Q.3 Draw layout of NMOS transistor observing lambda based design rules and the
colour coding. [10]
Q.4 Explain CMOS process with the help of the cross sectional view. [10]
 END SEM
C tRutler Technical 2023-24
nversity Kanpur
Branch Eleconies k.ngineering Program B.Tech
Course Name VLSI Design Semester VI
Course Code EET 354 Year 2023-24

Time: 2:30Hr Answer All Questions Maximum Marks 50

Knowledge KI:Remembering K3:Applying K5:Evaluating

Level(KL) K2:Understanding K4:Analysing K6:Creating
Note: Attempt all questions.

Q.No Questions Marks COs KL

la What are the quality metrics of a digital design? Explain it in detail. 4 CO1 K2

Explain the variation of m point with respect to W/L ratio; take CMOS 4 CO1 K2
inverter as an example.
2a Draw multiplexer based positive latch for Master Slave configuration.
4 C04 K2

2bExplain dynamicCMOS design and its integrity issues in digital circuits. 4 CO2 K4

Realize, draw the logic graph and Euler path for the given logical
3a
equation, and also verify it in IC layout diagram. 4 C02 K5

YkAB+BC+DA)'
3bmplement the given logical equation with PAL, PLA and PROM.
4
f(a, b, c, d)=X(0, 2, 4, 79, 12) C02 K4

4 Explain Sequential and Random access memory. Obtain a 2048 x8

memory using 256x8 memory chips. CO5 K3
4

4b Biscuss the timing issues of digital IC design. If setup-Ins. thold=Ins find 4 CO4 K3, K4
the minimum clock period required for the proper operation of the circuit.

2ns
Ip
D

clk
 working
of
CMOS based SR latch schematic
explain
the
and
5a Draw CO4 K2
diagram.
NAND gate

layout design
ofTwo input
4
5 Drawthe IC
Wrte the VHDL code to implement Four Bit Full Adder using structural
CO5
K3
methodology. CO3 K4
two input NAND gate
Wrie the AIM SPICE code of for
6h
transient and DC sweep
analysis. determining CO3 K4
hWntethe VHDL code to implement 4xl multiplexor
2
CO3 K3
Demonstrate a clear
technology scaling. understanding of (CMOS fabrication
COI

CO2 Design Complementary flow and

MOSFET based logic circuit
CO3 Synthesis of digital
Course in hardware design VLSI systems from
Outcomes C04 (Get the basic
detail
languages. Realize logicregister-transfer or higher level
cos Learm about the for designing of Sequentialcircuits with different design descriptions
designing of different circuits. styles.
arithmetic building blocks.
 KANPUR
UNIVERSITY,
TECHNICAL
HARCoURT BUTLER
B. Tech.
IMID SEM.Examination
2022-23
Even Semester (VI),
EET-354 VLSI Design
Time: 1Hour Max. Marks: 15
Note: asshown
against them. Attempt all questions. AIl questions carry marks,
Q.1 Explain how can you calculate, simulate and measure propagation delay of a CMOS
inverter. [5]
2 Explain fabrication process of (wo input CMOS NAND gate with the help of
cross
sectional view and the mask layout, observing lambda based design rules.
[5]
0.3 Assume that the diameter of awafer is 30 cm and dies area is 2.5 mm X2.5 mm. The
defect
density D, =0.6 defect cm and the manufacturing complexity a=4.The wafer price is
1500S. Calculate the cost of each die without considering the fixed cost