CST202 Computer Organization and

Architecture
Module 1
 Module I
Basic Structure of computers – functional units - basic operational
concepts - bus structures.
Memory locations and addresses - memory operations,Instructions
and instruction sequencing , addressing modes.
Basic processing unit – fundamental concepts – instruction cycle –
execution of a complete instruction - single bus and multiple bus
organization
CO1 : Recognize and express the relevance of basic components,
I/O organization and pipelining schemes in a digital computer
(Cognitive knowledge: Understand)
FUNCTIONAL UNITS
FUNCTIONAL UNITS
● Information can be categorized as either instructions or data
● Instructions, or machine instructions are explicit commands that
○ Governs the transfer of information within a computer as
well as between the computer and its I/O devices
○ Specify the arithmetic and logic operations to be performed.
● A list of instructions that performs a task is called a program
● Programs are stored in memory.
● Processor then fetches instructions from memory one after
another, and perform the desired operations
● The computer is completely controlled by the stored program
FUNCTIONAL UNITS
● Data are numbers and encoded characters that are used as
operands by the instructions.
● An entire program may be considered as data if it is to be
processed by another program.(eg. compiler)
● There are two classes of storage, called primary and secondary.
● Primary storage - fast memory that operates at electronic speed.
● The memory contains a large number of semiconductor storage
cells, each capable of storing one bit of information.
● These cells are rarely read or written as individual cells but
instead are processed in groups of fixed size called words.
FUNCTIONAL UNITS
● Memory is organized so that the contents of one word,
containing n bits, can be stored and retrieved in one basic
operation.
● To access every word a distinct address is associated with each
word location.
● A word can be accessed by specifying its address and issuing a
control command.
● The number of bits in each word is often referred to as the word
length of the computer.
● When operands are brought in to the processor, they are stored in
high speed storage elements called registers.
BASIC OPERATIONAL CONCEPTS
● Any activity in a computer is governed by instructions
● To perform a task, an appropriate program consisting of a list of
instructions is stored in memory.
● A typical instruction may be
● Add LOCA,R0
● First instruction is fetched from memory into the processor.
● Next the operand at LOCA is fetched and added to R0
● Finally sum is stored at R0 ( Architecture dependent)
BASIC OPERATIONAL CONCEPTS
BASIC OPERATIONAL CONCEPTS
● Individual instructions are brought to processor, which executes
the specific operations.
● The processor contains registers used for different purposes
● There are n general purpose registers R0 to Rn-1
● The instruction register (IR) holds the instruction that is
currently being executed.
● The Program Counter (PC) contains the memory address of the
next instruction to be fetched and executed
BASIC OPERATIONAL CONCEPTS
● Programs are fed into memory through the input unit.
● Execution of program starts when PC points to the first
instruction of program.
● The contents of PC are transferred to MAR and a read control
signal is send to memory
● The addressed instruction is read out of memory and loaded into
MDR.
● Next the contents of MDR are transferred to IR. Now, the
instruction is decoded and executed
BASIC OPERATIONAL CONCEPTS
● If the instruction involves an operation to be performed by the
ALU, it is necessary to obtain the required operands.
● If the operand resides in the memory, it has to be fetched by
sending its address to the MAR and initiating a Read cycle.
● Once the operand is read to MDR, it is then transferred to ALU.
● If the result of an operation is to be stored in the memory, then
the result is sent to the MDR.
● The address of the location, where the result is to be stored is
sent to MDR and a Write cycle is initiated.
BASIC OPERATIONAL CONCEPTS
● At some point during the execution of the current instruction, the
content of the PC are incremented so that the PC points to the
next instruction to be executed.
● As soon as the execution of the current instruction is completed,
a new instruction fetch may be started.
● Normal execution of programs may be preempted if some device
requires urgent servicing.
Bus Structures
● To form an operational system, the parts of the computer must be
connected together in some way.
● When a word of data is transferred between units, the bits are
transferred simultaneously over many wires or lines, one bit per
line.
● A group of wires which act as a connecting path between several
devices is called a bus.
● The bus has separate lines for carrying data, address and control
information.
Bus Structures
● Simplest way to interconnect functional units is to use a single
bus
● Only one transfer at a time.
● Only two units can actively use the bus at any given time.
● Low cost
● Multiple bus organization allows two or more transfers to be
carried out at the same time.
● Better performance at an increased cost.
PROCESSOR CLOCK
● Processor circuits are controlled by a timing signal called a
clock.
● The clock defines regular time intervals, called clock cycles.
● To execute an instruction, the processor divides the action to be
performed into a sequence of basic steps, each to be completed
in one clock cycle.
● Let P be the length of a clock cycle.
● Its inverse, R=1/P, is called the clock rate, which is measured in
cycles per second or hertz(Hz).
PROCESSOR CLOCK
● Let T be the processor time required to execute a program that
contains N machine language instructions.
● Let S be the average number of basic steps required to execute
one instruction, where each step is completed in one clock cycle.
● If the clock rate is R cycles per second, the program execution
time is given by, T = (N x S) / R
Memory Organization
● The data and instructions are stored in the memory of a
computer.
● Memory consists of many million storage cells, each of which
can store a single bit.
● Random access memory (RAM) is the best known form of
computer memory
● DRAM
● SRAM
DRAM
DRAM
● In dynamic random access memory (DRAM), a transistor and a
capacitor are paired to create a memory cell, which represents a
single bit of data.
● The capacitor holds the bit of information - 0 or 1
● The transistor acts as a switch that lets the control circuitry on
the memory chip read the capacitor or change its state.
● The charge stored in the capacitor degrades over time, so its
value must be refreshed (read and rewritten) periodically.
● It’s a drawback of Dynamic RAM.
SRAM
● In static RAM, a form of flip-flop holds each bit of memory.

● A flip-flop for a memory cell takes four or six transistors, but

these never has to be refreshed.

● This makes static RAM significantly faster than dynamic RAM,

but more expensive.
SRAM
Memory Organization
● Usually the cells are handled in groups of n bits, such that a
group of bits can be stored or retrieved in a single basic
operation
● A basic unit of 8 bits is called a byte.
● Each group of n bits is called a word and n is referred to as
word length.
● Modern computers have word lengths ranging from 16 to 64 bits
and more.
● If the word length of a computer is 32 bits, a single word can
store 4 bytes of data.
● Within the memory, each location has a distinct address, so that
its contents can be accessed without ambiguity.
Memory Organization
● Usually the numbers 0 to 2k-1, for some suitable value of k , is
used as addresses of successive locations in memory.
● These 2k addresses constitute the address space of the computer
and we have a k – bit address.
● For example, if k=24, we have a 24 bit address and an address
space of 224 locations.
● In memory, successive addresses usually refer to successive byte
locations.
● Such a memory is called a byte addressable memory.
● If the machine has a word length of 32 bits, successive words are
located at addresses 0,4,8,... with each word containing 4 bytes
Memory Organization
Memory
BYTE ADDRESS ASSIGNMENT
● There are two ways in which byte addresses can be assigned
across words – big endian and little endian assignments

● In big endian assignment, the lower addresses are used for more
significant bytes (leftmost bytes) of the word.

● In little endian assignment, lower addresses are used for less

significant (rightmost ) bytes of the word.
MEMORY OPERATIONS
● The two basic operations involving memory are the Read (Load
or Fetch) and Write (Store).
● During Read operation, a copy of the contents of the memory
location is transferred to processor.
● Memory contents remains unchanged.
● Store operation transfers information from processor to a
specific memory location.
● This destroys the former contents of that location.
● A data item of size 1 byte or 1 word can be transferred between
processor and memory in a single operation
INSTRUCTIONS
● Computer instructions are a set of machine language commands
that a particular processor understands and executes.
● A computer performs tasks on the basis of the instructions
provided
● An instruction comprises of different parts, called fields.
● Operation code (Opcode) field specifies the operation to be
performed.
● Operand /Address field contains either the operand itself or the
location of the operands, i.e., register or memory location.
● Mode field specifies how the operand will be located
INSTRUCTIONS
General Instruction Format
INSTRUCTIONS
● A computer must have an instruction set with instructions
capable of performing four types of operations:
■ Data transfer
■ Arithmetic & logic Operations
■ Program sequencing and control
■ I/O transfers
Representing Instructions
● Instructions can be represented in two ways, using either:
● Register Transfer Notation
● The right hand side of an RTN expression always denotes a
value, and the left hand side is the name of the location
where the value is to be placed, overwriting the old content
● eg: R1<-- [LOC]
● R3<-- [R1]+[R2]
● Assembly Language Notation
● eg: Move LOC,R1
Add R1,R2,R3
Instruction Types
● Instructions are of the following types based on number of
operands or addresses they use. (Eg. C =A+B)
● Three Address Instruction
● General format is:
● Opcode Source1, Source2, Destination
○ eg: Add A,B,C
○ A and B are the source operands and C is the destination
operand.
○ Instruction size is too large to fit in to an average word size
(3k bits for addressing purposes, if k bits are needed to
specify memory address of each operand)
Instruction Types
● Two Address Instruction
● General format is:
● Opcode Source, Destination
● Eg: Add A, B, which performs B<--[A]+[B]
Move B,C - C<- [B]
● Here the old contents of B will be replaced once the operation is
complete
● If we don't want to destroy the contents of B, one more
instruction should be used.
Move B, C C <-- [B]
Add A,C C <--[A]+[C]
Instruction Types
● One Address Instruction
○ The machine instructions specify only one memory operand
○ When a second operand is needed, it is understood to be
implicitly present in an unique location.
○ A special processor register, called Accumulator is used as
this unique location
Instruction Types
● One Address Instruction
Eg: Add L1
This instruction means to add the contents of memory location L1 to content
of accumulator register.
The two address instruction, C<--[A]+[B] , can be performed by the
following one address instructions:
Load A // Copy contents of location A to Acc
Add B // Add contents of B to Acc
Store C // Write contents of Acc to location C
Instruction Types
● Zero Address Instruction
Eg: Add
All operands are defined implicitly
Operands are stored in pushdown stack
Instruction Sequencing
● Executing a given instruction is a two phase procedure.
● First phase is called instruction fetch, and here the instruction to
be executed is fetched from memory
● The second phase is instruction execute, where the required
operations are done by the processor.
● At some point during these two phases, the content of PC is
updated to point to the next instruction
● If the content of PC is updated in order of increasing addresses,
it is called straight line sequencing.
● Here the instructions are executed in the same order as they
appear in the program
Instruction Sequencing
Branching
● Branching involves a deviation from the straight line execution.
● A branch instruction loads a new value, other than the next
sequential address into the PC.
● As a result, the processor fetches and executes the instruction at
this new address instead of the next instruction in sequence.
● A conditional branch instruction causes a branch to happen only
if a specific condition is satisfied.
● If condition is not satisfied, the PC is incremented in the normal
way and the next instruction in sequential order is fetched and
executed.
Instruction Sequencing
Condition Codes
● The processor keeps track of information about the result of
various operations for use by subsequent conditional
branch instructions.
● This is accomplished by recording the required information
in individual bits called, conditional code flags.
● These flags are often grouped together in a special
processor register called the conditional code register or
status register.
● Individual flag bits are set to 1 or cleared to 0 depending on
the outcome of the operation performed.
Condition Codes
● Four commonly used flags are
● N (negative) - set to 1 if the result is negative, otherwise
cleared to 0
● Z (Zero) - set to 1 if result is zero, otherwise cleared to 0
● V (Overflow) - set to 1 if arithmetic overflow occurs,
otherwise cleared to 0 .
● C (carry) - set to 1 if carry out results from the operation,
otherwise cleared to 0
ADDRESSING MODES
● The address of an operand can be specified in
different ways in an instruction – need not always be
given directly.
● These different ways in which the address of an
operand is specified in an instruction are called
addressing modes.
● Provides flexible means of accessing operands.
Addressing Modes for Variables and Constants

● Variables and constants are simplest data types.

1) Register Mode
● The operand is placed in a processor register.
● The name of this register is given in the instruction.
Eg: Add R2, R1
 2) Absolute Mode
● The operand is in a memory location.
● The address of this location is given explicitly in the
instruction.
● Eg: Add LOC
Let LOC represent the memory address 1008.
Then, Add LOC means to add contents of 1008 to
accumulator.
● To represent constants another addressing mode is used
3) Immediate Mode
● The operand value is given directly in the instruction.
● Used only to specify the value of a source operand.

Eg: Move #5, R0, places the value 5 in register R0.

Add #6, R1 adds 6 to contents of R1 and store result in
R1
Addressing Modes for Pointers

● In this case, the instruction does not give the

operand value or its address explicitly.
● Instead it provides information from which the
memory address of the operand can be
determined.
● This calculated address is called the Effective
Address (EA) of the operand.
 4) Indirect Mode
● The effective address of the operand is the content of a
register or memory location, whose address is given in
the instruction.

● This register or memory location that contains the

address of operand is called a pointer.
Indirect Mode
Indirect Mode
Indirect Mode

● Indirect addressing mode corresponds to high level language

statements using pointers.
● The C language statement, A = *B, where B is a pointer
variable, can be represented in assembly language notation
as:
○ Move (B), A
● The contents of address in B will be moved to A.
Addressing Modes for Indexing
● Used to access individual elements from an array
● Very often, a chunk of data is stored as a complete block
in memory.
● For example, it makes sense to store arrays as contiguous
blocks in memory.
● The array has a 'base address' which is the location of the
first element.
● Then an 'index' is used , that adds an offset to the base
address in order to fetch any other element within the
array
5) Index Mode
● The effective address of the operand is generated by
adding a constant value (offset) to the contents of a register

● The register used for this purpose is called a index register.

● Symbolically represented as X(Ri), where X denotes the
constant value and Ri is the index register.
● EA = X+[Ri]

● The index register can contain either the address of a

memory location or the offset value.
Base Address is in Index register
● In general, the index mode facilitates access to an
operand whose location is defined relative to a reference
point within the data structure where the operand
appears.
● Index mode can also be accomplished using two
registers, represented as (Ri,Rj) or using two registers
and an offset, X(Ri,Rj)

● EA=[Ri]+[Rj] or EA = X+Ri+Rj
6) Relative Addressing Mode
● A version of index mode, where PC is used as the index
register
● Represented as X(PC) and it represents a memory location
that is X bytes away from the location pointed to by PC
○ EA = X+[PC]
● Most common use is to specify target address in branch
instructions.
● Eg . Branch>0 LOOP
■ Assembler creates -16(PC), assuming branch target
address 16 bytes backward.
● During the fetching and execution of an instruction, the
content of PC is updated.
● This updated value will be used for calculating the
effective address
● In case of relative addressing, X is often called the
displacement.
 7) Auto Increment Mode

● The Effective Address of the operand is the content of a

register specified in the instruction.
● After accessing the operand, the contents of this register
are automatically incremented to point to next item in a
list.
● The increment value corresponds to size of accessed
operand. (1 for byte operands, 4 for word operands in case
of 32 bit address)

● Represented as (Ri)+
● Let register R2 contain the address 1004 which holds a 1 word
data (32 - word length).

● The instruction Add (R2)+,R0 adds the contents of 1004 to the

contents of register R0 and increments the contents of R2 by 4.

● New content of R2 after the operation is 1008.

● Example program using auto increment mode
● To find sum of N numbers, which are stored in
contiguous memory locations.
● N is placed in register R1
● R2 contains NUM, which is the starting address of
numbers in memory.
●
8) Autodecrement Mode
● The contents of register specified in the instruction are
first automatically decremented and then used as the
effective address of operand.
● Denoted by -(Ri)
● The operands are accessed in decreasing address order.
● Let register R2 contain the address 1008 which holds a 1
word data

● The instruction Add -(R2),R0 decrements the contents of R2

to 1004 and adds the data at this location to content of
register R0.

● New content of R2 after the operation is 1004.

INSTRUCTION EXECUTION
Two phases for instruction execution -fetch phase and
execute phase
1. Fetch the contents of memory location pointed by PC
and load to IR.
i. IR ← [[PC]]
2. Increment PC, ie, PC ← [PC]+ 4 (assuming byte
addressable memory and word length 32 bits)
3. Carry out the actions as per the instruction in IR.
INSTRUCTION EXECUTION

● First two steps refer to the fetch phase

● Last step constitutes the execute phase

● In case an instruction occupies more than one

word, steps 1 and 2 must be repeated to fetch the
complete instruction
PROCESSOR ORGANIZATION USING SINGLE BUS

● Simplest organization
● ALU and all registers are interconnected via a
single common bus.
● The bus is a group of wires which act as a
connecting path between ALU and the registers.
● This bus is internal to the processor
PROCESSOR ORGANIZATION USING SINGLE BUS

● Data and address lines of external memory are connected to

processor bus through the MDR and MAR, respectively
● MDR has two inputs and two outputs
● Data may be loaded to MDR either from memory or from
internal processor bus
● Input of MAR is connected to processor bus and output to
memory.
PROCESSOR ORGANIZATION USING SINGLE BUS
● Instruction decoder and control logic unit issues signals that
control and coordinate operations of all units within the
processor

● It also interacts with memory bus by issuing the required read

or write signals.

● The registers R0 through R(n-1) are general purpose registers.

PROCESSOR ORGANIZATION USING SINGLE BUS
● Three registers Y, Z and TEMP are used for temporary storage
during ALU operations.

● They are never referenced explicitly by any instruction.

● The ALU has 2 inputs – one coming from the processor bus
and another the output of a multiplexer.
PROCESSOR ORGANIZATION USING SINGLE BUS

● A multiplexer (MUX) selects either the content of register Y

or a constant 4 as the input A of ALU.
● The two values of select line are referred to as Select 4 and
Select Y
● The constant 4 is used for incrementing the contents of
Program Counter, i.e. to do [PC]+4.
● The output of ALU is temporarily held in Z.
PROCESSOR ORGANIZATION USING SINGLE BUS

● As instruction execution progresses, data are transferred

from one register to another, often passing through ALU.
● The instruction decoder and control logic unit carries out
the actions specified by the instruction in IR by issuing
proper control signals.
● The registers, ALU and bus collectively form the data
path
PROCESSOR ORGANIZATION USING SINGLE BUS
● Most of the instructions can be executed by performing one
or more of the following operations is some sequence:
○ Transfer a word from one processor register to another or to the ALU
(Register Transfer).
○ Perform an arithmetic or logic operation and store result in a register
(ALU operation)
○ Fetch the contents of a given memory location and load to a processor
register (Memory read).
○ Store a word of data from a processor register into a given memory
location (Memory Write).
Register Transfers
● If a register wants to transfer data to another register, it
can be done via the bus only.

● For each register, two control signals are used.

● These either load the contents of register on the

processor bus or load data on the bus into the register
Register Transfers
● The input and output of register Ri is connected to bus
via switches and are controlled using signals Riin and
Riout.
● Riin = 1 --> Data on bus loaded to Ri.
● Riout = 1 --> Data in Ri placed in to bus.
● When Riout is 0, the bus can be used for transferring
data from other registers.
● The control signals that govern a particular transfer are asserted
at the start of the clock cycle.
● The registers consist of edge triggered flip flops.
● When Riin is 1, multiplexer selects the data on the bus.
● The data will be loaded into the flip flop at the rising edge of the
clock.
● The output of the flip flop is connected to the bus via a tri-state
gate.
Example
● Suppose we want to transfer contents of register
R1 to R4. This can be done by following steps.

● Enable R1out by setting R1out to 1. This places

contents of R1 to processor bus.

● Enable R4inby setting it to 1. This loads contents

of processor bus to R4.
ALU Operations

● ALU is a combinational circuit with no internal storage.

● It performs operations on the two operands applied at
inputs A and B.
● One of the operands is the output of a MUX and the
other is applied directly from the bus.
● Result is temporarily stored in Z.
 To perform the operation R3 = R1 + R2, the
required signals are:
1. R1out, Yin
2. R2out, Select Y, Add, Zin
3. Zout, R3in
● Step 1 - R1out places the contents of R1 in bus

● Since Yin is enabled, the contents of bus are

loaded to Y, thus loading first operand to Y.
● In step2, contents of R2 (second operand) are placed
in bus and added to first operand
● R2out places contents of R2 to bus
● Select Y is the selection signal for MUX
● When it is enabled, the contents of Y will be given as
input A of ALU.
● Y already contains content of R1, so this become
input A of ALU
● The contents of bus (R2) are available at input B of
ALU.
● When the Add signal is given, ALU performs
addition of the operands at the two inputs.
● Zin is enabled, thereby placing result from ALU to Z.
● In step 3, contents of Z are transferred to
R3
● Zout puts the contents of Z into the bus.
● R3in is enabled, thereby loading contents
of bus to register R3.
MEMORY READ

● To fetch a word from memory, the processor has to first

specify the address of the memory location where this
information is stored.
● Then a read operation is requested.
● The processor transfers the required address to MAR.
● At the same time the processor uses the control lines of
memory bus to indicate a Read operation is needed.
● Once the read operation is completed, the requested
data received from memory is stored in MDR.
● From MDR it is transferred to other registers in the
processor.
● Input of MAR is connected to processor bus and it’s
output to the address lines of memory bus.
● It has two control signals
● MDR register has has two way connections to both
processor and memory bus.
● Correspondingly it has 4 control signals:
● MDRin and MDRout control the connection to
processor bus.
● MDRinE and MDRoutE control connection to the
external bus (memory bus).
● The processor completes one internal data transfer in
one clock cycle.
● The speed of operation of memory is slower than that
of processor.
● It means once a memory read or write operation is
initiated, the processor has to wait until it is completed.
● To accommodate this variability in response time,
the processor waits until it receives an indication
that the requested memory operation has been
completed.
● A control signal called MFC (Memory Function
Completed) is used to give this indication to the
processor.
1. Consider the operation: Move (R1),R2
2. We need to get the data in the address specified in register R1
and place it in register R2.
3. This consists of following steps
3.1. First the address in R1 is loaded to MAR.
3.2. A read operation is initiated and processor waits for MFC
response.
3.3. MDR is loaded with the fetched data.
3.4. Data is transferred to R2.
● Corresponding control signals are:

1. R1out, MARin, Read

2. MDRinE, WMFC

3. MDRout, R2in

● It is assumed that the MARout is always enabled.

● Content of MAR are always available on address lines of
the memory bus.
● WMFC – Wait for MFC signal to arrive
Memory Write

● The address for write operation is first loaded to

MAR.
● Then the data to be written to memory is loaded to
MDR and a write command is issued.
● Processor then waits for the MFC signal.
● Move R2, (R1) – Moves the contents of register R2 to
the location in memory whose address is held in
register R1
● Steps needed are:
● Move address in R1 to MAR
● Load content of R2 to MDR
● Issue Write control signal
● Wait for MFC signal
 Control signals are:
1. R1out, MARin
2. R2out, MDRin, Write
3. MDRoutE, WMFC
Execution of a Complete Instruction
● Consider the instruction Add (R3), R1 or R1 ←R1+(R3)
● This instruction adds the contents of a memory location
pointed to by register R3 to the contents of register R1
● Following steps are required:
1. Fetch the instruction
2. Fetch first operand from memory
3. Perform addition
4. Load result into R1
Control signals issued for this operation are:
Execution of a Complete Instruction
● Step 1 is for instruction fetch.
● Instruction fetch is initiated by loading contents of PC to
MAR and sending a read request to memory.
● Next we want to increment PC
● For this, Select signal of MUX is set to Select 4, so that the
constant 4 is selected as input A of ALU.
● This value is added to operand B which contains the current
data in bus,i.e, the contents of PC and result is stored in Z.
Execution of a Complete Instruction
● In step 2, the updated value is moved from Z to PC.
● For this the output control signal of Z (Zout) and input
control signal of PC (PCin) are activated.
● The new value of PC is also copied to Y for calculation of
target address in case of branch instructions.
● This is done by activating Yin
● WMFC indicates that the processor is now waiting for the
read operation to complete
Execution of a Complete Instruction
● In step 3 , the instruction fetched from memory is
transferred from MDR to IR.
● MDRout and IRin are activated
● The instruction decoding circuit interprets the contents of IR
during the beginning of step 4 and appropriate control
signals are activated.
Execution of a Complete Instruction
● Step 4 initiates the read operation for second operand –
ie, to fetch the contents of memory location whose
address is present in R3
● Contents of R3 is transferred to MAR
● For this, R3out and MARin are activated
● Now a Read control signal is generated for initiating the
fetching of operand from memory.
Execution of a Complete Instruction
● In step 5, the first operand, ie, the content of register
R1 is placed into bus and loaded to Y
● This can be done while waiting for read operation to
complete.
● R1out and Yin are activated and contents of R1 copied to
Y
● Now the processor waits for read operation to complete
Execution of a Complete Instruction
● In step 6 the addition operation takes place
● Once the read is completed, second operand is there at
MDR
● Data in MDR is placed into the processor bus by setting
MDRout to high.
● The select Y signal is applied to MUX to get the first
operand from Y at input A of ALU and Add signal is
given.
● Zin is activated so that result after addition is loaded to Z
Execution of a Complete Instruction
● In step 7, the result is moved from Z to the
destination register R1
● This is done by activating Zout and R1in
● End signal causes a new instruction cycle to start.
 BRANCH INSTRUCTIONS

● A branch instruction replaces contents of PC with

branch target address.
● This address is obtained by adding an offset X, given
in the branch instruction, to the updated value of PC.
● The offset value is extracted from IR by the
instruction decoding circuit.
 BRANCH INSTRUCTIONS

● Since the updated value of PC is available in

register Y, the offset value is placed in the bus
and an add operation is performed.
● This new address is then loaded to PC.
● After this a new instruction cycle begins.
BRANCH INSTRUCTIONS
● In case of a conditional branch, we need to check the status of
condition codes before loading the new value to PC.
● If the condition is not true, the calculated value is not loaded to
PC and the execution of next instruction in sequence starts
● For example for a branch on negative (Branch<0) instruction,
step 4 can be replaced with
● Offset-field-of-IRout, Add, Zin, If N=0 then End
● Thus if N=0 the processor return to step 1 immediately after
step 4.
● If N=1 step 5 is performed to load new value to PC, thus
performing branching.
Multiple Bus Organization

● In a single bus, the control sequences are quite long

since only one data transfer can take place over the
bus in a clock cycle.
● To reduce the number of steps, most commercial
processors use multiple bus, which provides multiple
internal paths for parallel data transfers.
Multiple Bus Organization

● The figure shows a three bus structure.

● All general purpose registers are combined into a
single block called a register file.
● Buses A and B are used to transfer source operands
to ALU and bus C transfers result to destination.
●An incrementer unit is used to increment the PC
● The constant 4 input to the ALU is still used to
increment other addresses. ( Eg. Loadmultiple or
Storemltiple instructions)
● Consider the instruction
● Add R4, R5, R6 or (R6← [R4] + [R5])
● The sequence of control signals for executing his
instruction using the given 3 bus structure is:

1. PCout, R=B, MARin, Read, IncPC

2. WMFC
3. MDRoutB, R=B, IRin
4. R4outA, R5outB, SelectA, Add, R6in, End
● Add R4, R5, R6

1. PCout, R=B, MARin, Read, IncPC

2. WMFC
3. MDRoutB, R=B, IRin
4. R4outA, R5outB, SelectA, Add, R6in, End
● In step1, the contents of PC are placed in the B bus and
passed as such to C bus through the ALU, using R=B

● This is loaded into MAR and a read operation is initiated.

IncPC increments contents of PC.

● Step 2 waits for the read operation to complete.

● Once the instruction is read from memory, it is
moved to IR through ALU using the R=B
instruction.
● In step 4, the contents of register R4 and R5 are
placed in buses A and B.
● The ALU adds the operands and result is loaded
to R6
The full sequence of control signals for performing the same
operation using a single bus would be:
1. PCout, MARin, Read, Select 4, Add, Zin
2. Zout, PCin, Yin, WMFC
3. MDRout, IRin
4. R4out, Yin
5. R5out, Select Y, Add, Zin
6. Zout, R6in