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EECS3611 Analog Integrated Circuit Design

Chapter 1

Introduction

EECS3611 Analog Integrated Circuit Design

 Instructor: Prof. Ebrahim Ghafar-Zadeh,
Prof. Peter Lian
email: egz@cse.yorku.ca
peterlian@cse.yorku.ca
 Course Web
https://wiki.eecs.yorku.ca/course_archive/2016-17/W/3611/
 Schedule:
 Lectures: PSE321, Mon. & Wed. 4:00pm – 5:30pm
 Labs@BEL 334, Thur. 6:30pm-9:30pm,
 Office hours:
Wed. 2:00-3:30pm@LAS1012C (starting Feb. 1, 2017)

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EECS3611 Analog Integrated Circuit Design

 Textbook
Design of Analog CMOS Integrated Circuits
2nd Edition, Copyright: 2017
By: Behzad Razavi
McGraw Hill Education
ISBN-10: 0072524936
ISBN-13: 9780072524932
Available at York Bookstore

Grade Components
 Assignment: 10%
 Quiz: 15% (3 quizzes in class)
 Lab: 25%
 8 lab sessions
 Starts on Jan. 26 (week 4, tentative)
 Assessment based on lab report and design project.
 Midterm 20%
 Final 30%

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LAB
 Lab will be at BEL 334
 Lab contains two parts
 Part 1 is for learning of EDA tool (i.e. Cadence), circuit
simulation, and layout.
 Part 2 is for a design project.
 Maintain a laboratory book or journal for all lab
sessions. It must be signed by the TA before you
leave the lab.

Topics covered
 Introduction to analog design
 Basic MOS device physics
 Single state amplifiers
 Layout and design rules
 Differential amplifiers
 Passive and active current mirrors
 Frequency response of amplifiers
 Noise
 Feedback
 Operational amplifiers

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Learning Outcomes
 After successful completion of the course,
students are expected to be able to:
 To analyze the characteristics of basic analog
integrated circuits
 To formulate the behavior of basic analog circuits by
inspection
 To perform circuit simulation using computer-aided
tool
 To draw layout based on given design rules

EECS3611 Analog Integrated Circuit Design

Introduction

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Discrete Component and Integrated Circuits

 Discrete component circuit (in EECS2210) consists of
different active components (transistors) and passive
components (capacitors, resistors and inductors).
 Integrated circuit (this course) is a monolithic circuit
fabricated on a semiconductor substrate. It mainly
consists of transistors with limited number of resistors
and small value capacitors.

Discrete Component and Integrated Circuits

 Discrete component circuit:

 Both active and passive components are available.
 Most are AC coupled circuit to isolate the DC biasing
points of different devices.
 Low device density, high power consumption.
 Integrated circuit:
 Mainly transistors, as resistors and capacitors occupy
larger chip area.
 Most are DC coupled circuit.
 High device density, low power consumption.
 High speed.

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Analog and Digital

 Analog signal: Continuous in time and amplitude
 Digital signal: discrete in time and amplitude

Analog signal Digital signal

Design of Analog and Digital Circuits

noise linearity
speed

power gain

I/O supply
impedance voltage

speed voltage
power
swing

Analog circuit Digital circuit

Multi trade-offs in analog design make it very complex.

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Why Analog?
 Most of the physical signals are analog in nature
 Need analog circuits to interface with physical
world

Why CMOS?
 CMOS is now dominate the digital IC market:
 Simple device structure, low fabrication cost.
 Simple circuit for digital gates.
 Advancement in CMOS technology.
 Scalable and high integration density.
 The demands for smaller and cheaper device, i.e.
monolithic circuit and System-on-Chip (SOC), drive
analog IC to CMOS technology.
 To integrate analog and digital circuits into one chip.
 To reduce the cost.
 Analog IC is moving to CMOS technologies,
especially for low voltage and low power
applications.

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Passive Devices in CMOS

 Resistor in CMOS:
 Diffusion resistor: sheet resistance 100 Ω/ to
200Ω/
 Poly silicon resistor: sheet resistance 20 Ω/ to
80Ω/
 Well resistor: ~10kΩ/

 Capacitor in CMOS:
 PIP (poly-insulator-poly) capacitance: high linearity,
unit capacitance <1fF/µm2
 MIM (metal-insulator-metal) capacitance: high linearity,
unit capacitance ~1fF/µm2
 MOS capacitance: Use CG as capacitance– voltage
dependence
 Large process variation: 20%.
 Passive devices occupy larger silicon area

Analog IC Design Flow

System specifications

Tools Topology selection

Matlab Behavioral simulation

Hspice Circuit design & simulation

Virtuso Physical implementation (Layout)

Calibre Physical verification (DRC&LVS)

GDSII data out

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EECS3611 Analog Integrated Circuit Design

Review of MOSFET

MOSFET
 MOSFET stands for Metal-Oxide-Semiconductor Field-
Effect Transistor.
 A MOSFET comprises a Metal-Oxide-Semiconductor
stack

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MOSFET: 3D Structure

MOSFET Symbols
 Two types of MOSFETs

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NMOS: Cutoff or Turned-Off

NMOS: Linear Region

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NMOS: Pinch-Off [VDS=VGS-Vth]

NMOS: Saturation [VDS൒VGS-Vth]

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NMOS Operation

NMOS: ID-VDS Characteristics

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NMOS: ID-VGS Characteristics

Body Effect

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Summary: Region of Operation

• Cut off region: VGS  VTH

• Linear region: VGS  VTH , VDS  VGS -VTH

• Saturation region: VGS  VTH , VDS  VGS -VTH

Saturation region H

H
VTHN
L H
L H

L H
L H L
|VTHP|
Saturation region L
Linear region
Linear region

MOSFET: CMOS
 CMOS stands for Complementary Metal-Oxide-
Semiconductor
 Containing PMOS and NMOS transistors
 P-channel device has opposite relative voltages,
has P+ source drains, and n-type substrate. Both
NMOS and PMOS devices are used in CMOS
technology.
 P-channel device produces less
transconductance for similar dimension and
current compared to n-channel due to lower
mobility of holes.

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MOSFET: CMOS
 Cross section of a NMOS and a PMOS FET in a CMOS
technology.

NMOS PMOS

EECS3611 Analog Integrated Circuit Design

Circuit Models

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Models for Design

 Transistor is modeled using basic circuit
components.
 Two types of models: large signal model and
small signal model
 Large signal model – large signal low frequency,
such as DC bias points.
 Small signal model – small signal and parameters
such as gain and frequency response of an analog
circuit.

MOSFET Model for Design

CGD
G D

CGS gmvgs gmbvbs ro

CGB
S CDB

CSB

B
A transistor is modeled by using four major components:
• A voltage controlled current source to model the
transconductance gm.
• Output resistance ro.
• A voltage controlled current source to model the back
gate transconductance gmb.
• Parasitic capacitance Cxx.

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Transistor DC Modeling
ID  0 for VGS  VTH

W
I D  μ Cox   VGS - VTH VDS  1 VDS2  for VGS  VTH , VDS  VGS -VTH
L 2 

1 W
ID  μ Cox  VGS - VTH  2 1  VDS  for VGS  VTH , VDS  VGS -VTH
2 L

G D
where VGS - VTH  VOD  VDSAT .
ID ro

V TH = V TH 0   [ 2  F + V SB  2  F ]

Small Signal (AC) Model for Circuit Analysis

 The model shown earlier is good for transistor

DC bias point calculation.
 For AC analysis, a simple small signal model is
developed. In this analysis, a small AC signal v
is superimposed on normal DC biases.
 In notation, AC signals will use all small letters,
DC all capitals and total voltage with AC and DC
components added will use mixed case
throughout this course. For example, VOUT is a
DC voltage, vout is an AC voltage and Vout is the
total voltage .

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Transconductance
 The effect of gate voltage controlling the drain
current is modeled by transconductance
I D
gm 
VGS

 Hence this gm models how drain current will

change with change in gate voltage.
 The transconductance is the most important
parameter of a transistor in analog circuit design.
 This effect is modeled as a voltage controlled
current source between drain and source.

Transconductance
 In the linear region, the transconductance of a MOSFET
is
W
g m  Cox VDS
L

clearly indicating a drop with decreasing VDS.

 In the saturation region
W W 2I D
g m  Cox (VGS  VTH )  2 Cox I D 
L L VGS  VTH

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Output Conductance
 The effect of the drain voltage is modeled using the output conductance

I D
gd 
VDS
 This models how ID changes when the VDS changes. Since we want only
input voltage to control ID and not the output voltage, ideally, this should
be zero.
 Hence in saturation region using ID expression:
1 W I
I D  Cox  VGS - VTH  (1  λVDS )  g d  D  I D
2

2 L VDS
 This effect is captured as a resistance called output resistance:

1 1
ro  
g d I D

Back Gate Transconductance

 The effect of body bias or bulk voltage is modeled using
body or back gate transconductance.
I
g mb  D
VBS
 Hence this value is mainly determined by γ. This effect is
captured as a dependent current source circuit element
between drain and source.
I D 
g mb   gm  g m
VBS 2 2 F  VSB

 Normally the back gate transconductance is 20% of the

front gate transconductance, i.e. η=0.2.

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MOSFET Capacitance
 The fundamental mode of MOSFET operation is through
charge which is modeled through 3 non-linear bias
dependent capacitances CGS, CGD and CGB .
 In addition, there are three linear overlap capacitances.
 CGSO : Gate to source overlap capacitance per meter

of channel width. This and drain overlap capacitance

are independent of length L as they are associated
with edge effects.
 CGDO : Similar to drain counterpart.

 CGBO : Gate to bulk overlap capacitance per meter of

channel length and is associated with edge effects at

the width ends of the gate area.

MOS Structure Overlap Capacitance

lateral diffusion
Poly Gate

Source Drain
Top view n+ xd xd
W n+

Ldrawn
Gate
capacitance

S D

Depletion CGDO
CGSO
capacitance

Overlap capacitance (linear): CGSO  CGDO  COV  W

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Total Gate Capacitance

 Total gate capacitance in cut-off region: CGS  CGSO
 CGB is WLCox in series with Cd CGD  CGDO
 Cd is the depletion region capacitance (WLCox )Cd
CGB 
(WLCox )  Cd
q si N A
Cd  WL
4 F CGD

1
 In linear region: CGS  CGSO  WLCox CDB
2
1
CGD  CGDO  WLCox
2
CGB  0
CGS
CSB
2
 In saturation region: CGS  CGSO  WLCox
3
CGD  CGDO CGB
CGB  0

Total Gate Capacitance

Cut off Saturation Linear

Total gate capacitance change in different

operation region.

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Junction Capacitance
 CSB and CDB are capacitances between the
sidewalls and the bottom regions of the S and D
junctions.

S, D junction
S D E
W

CSB CDB
side wall bottom

Parasitic Capacitances
 Since source – drain doping profiles are normally the same. We take drain
capacitance as an example.
 For certain bias voltage VBD the drain-bulk capacitance is:
C DB 0
C DB  MJ
 VBD 
1 - 
 PB 
 MJ Bulk junction sidewall capacitance grading coefficient
 PB Bulk junction built-in potential
 Zero bias drain capacitance CDB0 is:

C DB 0  Cbottom 0  Csidewall 0  AD C J  W  2 E  C JSW

 CJ Zero bias bulk junction bottom capacitance per unit area

 CJSW Zero bias bulk junction sidewall capacitance per meter of junction perimeter
 E Drain width
 AD Drain area from the layout

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Parasitic Resistances
 RS and RD are the source and drain resistances
due to which inside source and drain voltages
applied to actual inversion layer will change for
high drain current.
 In addition, there are noise coefficients which
may add some noise to ID.
 This model ignores many parasitic resistances,
bipolar devices and PNPN devices.

Lumped Small Signal (AC) Model

 The complete representation for NMOS and PMOS
devices is captured in the following figures.
 All capacitors are lumped together.
 For analytic calculations, this simple model is adequate.
Computer simulation tools like SPICE use more
sophisticated models that including hundreds of
parameters.
 For low frequency analysis of the circuits, all capacitors
can be removed from the small signal model of the
transistor.
 For full AC analysis, all elements are included in the
small signal model.
 CGB and CGD can be removed as they are very small
compared to others in saturation region.

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Lumped Small Signal (AC) Model

CGD
G D
D

CGS
G gmvgs gmbvbs ro
CGB
S CDB
S
NMOS FET CSB

B
CGD
G D
D

CGS
G gmvgs gmbvbs ro
CGB
S CDB
S
PMOS FET CSB
B

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