ASSESSMENT AND EVALUATION

• Labs: 25 (20%)
• Midterm Exam & activities : 35 (28%)
• Final Exam: 65 ( 52% )
COURSE TEXT-REFERENCE BOOKS AND
OTHER MATERIAL
• W. Stallings, Computer Organization and Architecture: Designing for Performance, 10th Edition,
Prentice- Hall, 2016.

• D. A. Patterson and J. L. Hennessy, Computer Organization and Design: The Hardware/Software

Interface, 5th Edition, Elsevier, 2013.
+ Course contents

n Structure and behavior of digital computers at several levels of abstraction.

n Functional organization of computer hardware.
n The classic components of a computer.
n Moore's law.
n Measuring and defining performance: the CPU performance equation
n measuring performance using benchmarks, measuring performance using SPEC
n Instruction set architecture: operations, operands, registers, memory organization, data transfer
instructions
n CPU organization: implementation of the different instruction types, data and control paths, control
units, different organizations with their advantages and inefficiencies.
+ High level language to machine
+
Organization of a computer
+
 CPU – controls the operation of
the computer and performs its
There are four data processing functions
main structural
components  Main Memory – stores data
of the computer:  I/O – moves data between the
computer and its external
environment

 System Interconnection –
some mechanism that provides
for communication among CPU,
main memory, and I/O

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

+
Function
n There are four basic functions that a computer can perform:
n Data processing
n Data may take a wide variety of forms and the range of
processing requirements is broad
n Data storage
n Short-term
n Long-term
n Data movement
n Input-output (I/O) - when data are received from or delivered to
a device (peripheral) that is directly connected to the computer
n Data communications – when data are moved over longer
distances, to or from a remote device
n Control
n A control unit manages the computer’s resources and
orchestrates the performance of its functional parts in response
to instructions
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
 COMPUTE R

I/O Main
memory

System
Bus

CPU

CPU

Registers AL U

Internal
Bus

Control
Unit

CONTROL
UNIT
Sequencing
L ogic

Control Unit
Registers and
Decoders

Control
Memory

Figure 1.1 A Top-Down View of a Computer

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

 MOTHE RBOARD
Main memory chips

Processor
I/O chips chip

PROCE SSOR CHIP

Core Core Core Core

L 3 cache L 3 cache

Core Core Core Core

CORE
Arithmetic
Instruction and logic L oad/
logic unit (AL U) store logic

L 1 I-cache L 1 data cache

L 2 instruction L 2 data
cache cache

Figure 1.2 Simplified View of Major E lements of a Multicore Computer

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

+ n Control Unit
CPU
n Controls the operation of the CPU
and hence the computer
Major structural
n Arithmetic and Logic Unit (ALU)
components:
n Performs the computer’s data
processing function

n Registers
n Provide storage internal to the CPU

n CPU Interconnection
n Some mechanism that provides for
communication among the control
unit, ALU, and registers

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

+
Multicore Computer Structure

n Central processing unit (CPU)

n Portion of the computer that fetches and executes instructions
n Consists of an ALU, a control unit, and registers
n Referred to as a processor in a system with a single processing unit

n Core
n An individual processing unit on a processor chip
n May be equivalent in functionality to a CPU on a single-CPU system
n Specialized processing units are also referred to as cores

n Processor
n A physical piece of silicon containing one or more cores
n Is the computer component that interprets and executes instructions
n Referred to as a multicore processor if it contains multiple cores

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

+
Cache Memory

n Multiple layers of memory between the processor and main memory

n Is smaller and faster than main memory

n Used to speed up memory access by placing in the cache data from main memory
that is likely to be used in the near future

n A greater performance improvement may be obtained by using multiple levels of

cache, with level 1 (L1) closest to the core and additional levels (L2, L3, etc.)
progressively farther from the core

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

 15
Microprocessor Performance

Source: H&P Textbook

50% improvement every year!!
What contributes to this improvement?
Why the lower improvement?
 16
Microprocessor Performance

Source: karlrupp.net
 17
Power Consumption Trends
• Dyn power a activity x capacitance x voltage2 x frequency
• Voltage and frequency are somewhat constant now,
while capacitance per transistor is decreasing and number
of transistors (activity) is increasing
• Leakage power is also rising (function of #trans and voltage)

Source: H&P Textbook

 18
Important Trends

• Running out of ideas to improve single thread performance

• Power wall makes it harder to add complex features

• Power wall makes it harder to increase frequency

• Additional performance provided by: more cores, occasional

spikes in frequency, accelerators
 The pace slowed to a
doubling every 18
months in the 1970’s The cost of The electrical Computer
but has sustained computer logic path length is becomes smaller Reduction in
that rate ever since Fewer
and memory shortened, and is more power and
interchip
circuitry has increasing convenient to use cooling
in a variety of connections
fallen at a operating requirements
dramatic rate speed environments

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

 20
Important Trends

• Historical contributions to performance:

1. Better processes (faster devices) ~20%
2. Better circuits/pipelines ~15%
3. Better organization/architecture ~15%

In the future, bullet-2 will help little and bullet-1 will eventually
disappear!

Pentium P-Pro P-II P-III P-4 Itanium Montecito

Year 1993 95 97 99 2000 2002 2005
Transistors 3.1M 5.5M 7.5M 9.5M 42M 300M 1720M
Clock Speed 60M 200M 300M 500M 1500M 800M 1800M

Moore’s Law in action At this point, adding transistors

to a core yields little benefit
 Wafer

Chip

Gate

Packaged
chip

Figure 1.11 Relationship Among Wafer, Chip, and Gate

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
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( DR AM m e m ory )

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