DRV8412, DRV8432

SLES242H – DECEMBER 2009 – REVISED JULY 2024

DRV84x2 Dual Full-Bridge PWM Motor Driver

1 Features The DRV841x2 requires two power supplies, one at
12V for GVDD and VDD, and another up to 50 V for
• High-efficiency power stage (up to 97%) with low
PVDD. The DRV841x2 can operate at up to 500kHz
RDS(on) MOSFETs (110mΩ at TJ = 25°C)
switching frequency while still maintaining precise
• Operating supply voltage up to 52V
control and high efficiency. The devices also have an
• DRV8412 (Power pad down): up to 2 × 3A
innovative protection system safeguarding the device
continuous output current (2 × 6A peak) in dual
against a wide range of fault conditions that could
full-bridge mode or 6A continuous current in
damage the system. These safeguards are short-
parallel mode (12A peak)
circuit protection, overcurrent protection, undervoltage
• DRV8432 (Power pad up): up to 2 × 7A continuous
protection, and two-stage thermal protection. The
output current (2 × 12A peak) in dual full-bridge
DRV841x2 has a current-limiting circuit that prevents
mode or 14A continuous current in parallel mode
device shutdown during load transients such as motor
(24A peak)
start-up. A programmable overcurrent detector allows
• PWM operating frequency up to 500kHz
adjustable current limit and protection level to meet
• Integrated self-protection circuits including
different motor requirements.
undervoltage, overtemperature, overload, and
short circuit The DRV841x2 has unique independent supply and
• Programmable cycle-by-cycle current limit ground pins for each half-bridge. These pins make
protection it possible to provide current measurement through
• Independent supply and ground pins for each half external shunt resistor and support multiple motors
bridge with different power supply voltage requirements.
• Intelligent gate drive and cross conduction
Package Information
prevention
PART NUMBER PACKAGE(1) PACKAGE SIZE(2)
• No external snubber or schottky diode is required
DRV8412 HTSSOP (44) 14 mm x 8.1mm
2 Applications DRV8432 HSSOP (36) 15.9mm x 14.2mm
• Brushed DC and stepper motors (1) For more information, see Section 9.
• Three-phase permanent magnet synchronous (2) The package size (length × width) is a nominal value and
motors includes pins, where applicable.
• Robotic and Haptic control system
GVDD
• Actuators and pumps PVDD
GVDD_A
• Precision instruments
GVDD_B

OTW BST_A
• TEC drivers FAULT PVDD_A
• LED lighting drivers PWM_A OUT_A

3 Description RESET_AB

PWM_B
GND_A
M
GND_B

The DRV841x2 are high-performance, integrated dual Controller OC_ADJ OUT_B

full-bridge motor driver with an advanced protection GND PVDD_B

system. AGND BST_B

VREG BST_C
Because of the low RDS(on) of the H-Bridge MOSFETs M3 PVDD_C

and intelligent gate drive design, the efficiency of M2 OUT_C

these motor drivers can be up to 97%. This high M1 GND_C

M
efficiency enables the use of smaller power supplies PWM_C GND_D

and heatsinks, and the devices are good candidates RESET_CD OUT_D

for energy-efficient applications. PWM_D PVDD_D PVDD

GVDD VDD BST_D

GVDD_C GVDD_D

Simplified Application Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV8412, DRV8432
SLES242H – DECEMBER 2009 – REVISED JULY 2024 www.ti.com

Table of Contents
1 Features............................................................................1 6 Detailed Description........................................................9
2 Applications..................................................................... 1 6.1 Overview..................................................................... 9
3 Description.......................................................................1 6.2 Functional Block Diagram......................................... 10
4 Pin Configuration and Functions...................................3 6.3 Feature Description...................................................11
5 Specifications.................................................................. 5 6.4 Device Functional Modes..........................................14
5.1 Absolute Maximum Ratings........................................ 5 7 Device and Documentation Support............................29
5.2 ESD Ratings............................................................... 5 7.1 Receiving Notification of Documentation Updates....29
5.3 Recommended Operating Conditions.........................5 7.2 Support Resources................................................... 29
5.4 Thermal Information....................................................6 7.3 Trademarks............................................................... 29
5.5 Package Heat Dissipation Ratings..............................6 7.4 Electrostatic Discharge Caution................................29
5.6 Package Power Deratings (DRV8412)(1) ................... 6 7.5 Glossary....................................................................29
5.7 Electrical Characteristics.............................................7 8 Revision History............................................................ 29
5.8 Typical Characteristics................................................ 8 9 Mechanical, Packaging, and Orderable Information.. 30

2 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: DRV8412 DRV8432

 DRV8412, DRV8432
www.ti.com SLES242H – DECEMBER 2009 – REVISED JULY 2024

4 Pin Configuration and Functions

DRV8412 DRV8432
DDW Package DKD Package
(Top View) (Top View)

GVDD_C 1 44 GVDD_D
VDD 2 43 BST_D
NC 3 42 NC
NC 4 41 PVDD_D GVDD_B 1 36 GVDD_A
PWM_D 5 40 PVDD_D 2 35 BST_A
OTW
RESET_CD 6 39 OUT_D 3 34 PVDD_A
FAULT
PWM_C 7 38 GND_D PWM_A OUT_A
4 33
M1 8 37 GND_C
RESET_AB 5 32 GND_A
M2 9 36 OUT_C
PWM_B 6 31 GND_B
M3 10 35 PVDD_C
OC_ADJ 7 30 OUT_B
VREG 11 34 BST_C
GND 8 29 PVDD_B
AGND 12 33 BST_B
AGND 9 28 BST_B
GND 13 32 PVDD_B
VREG 10 27 BST_C
OC_ADJ 14 31 OUT_B
M3 11 26 PVDD_C
PWM_B 15 30 GND_B
M2 12 25 OUT_C
RESET_AB 16 29 GND_A
M1 13 24 GND_C
PWM_A 17 28 OUT_A
PWM_C 14 23 GND_D
FAULT 18 27 PVDD_A
PVDD_A RESET_CD 15 22 OUT_D
NC 19 26
PWM_D 16 21 PVDD_D
NC 20 25 NC
21 24 BST_A VDD 17 20 BST_D
OTW
GVDD_B 22 23 GVDD_A GVDD_C 18 19 GVDD_D

Table 4-1. Pin Functions

PIN
I/O TYPE (1) DESCRIPTION
NAME DRV8412 DRV8432
AGND 12 9 P Analog ground
BST_A 24 35 P High side bootstrap supply (BST), external capacitor to OUT_A required
BST_B 33 28 P High side bootstrap supply (BST), external capacitor to OUT_B required
BST_C 34 27 P High side bootstrap supply (BST), external capacitor to OUT_C required
BST_D 43 20 P High side bootstrap supply (BST), external capacitor to OUT_D required
GND 13 8 P Ground
GND_A 29 32 P Power ground for half-bridge A
GND_B 30 31 P Power ground for half-bridge B
GND_C 37 24 P Power ground for half-bridge C
GND_D 38 23 P Power ground for half-bridge D
GVDD_A 23 36 P Gate-drive voltage supply
GVDD_B 22 1 P Gate-drive voltage supply
GVDD_C 1 18 P Gate-drive voltage supply
GVDD_D 44 19 P Gate-drive voltage supply
M1 8 13 I Mode selection pin
M2 9 12 I Mode selection pin
M3 10 11 I Reserved mode selection pin, AGND connection is recommended
NC 3, 4, 19, 20, 25, 42 — — No connection pin. Ground connection is recommended
OC_ADJ 14 7 O Analog overcurrent programming pin, requires resistor to AGND
OTW 21 2 O Overtemperature warning signal, open-drain, active-low. An internal pullup resistor
to VREG (3.3 V) is provided on output. Level compliance for 5-V logic can be
obtained by adding external pullup resistor to 5 V
OUT_A 28 33 O Output, half-bridge A
OUT_B 31 30 O Output, half-bridge B
OUT_C 36 25 O Output, half-bridge C

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3

Product Folder Links: DRV8412 DRV8432
DRV8412, DRV8432
SLES242H – DECEMBER 2009 – REVISED JULY 2024 www.ti.com

Table 4-1. Pin Functions (continued)

PIN
I/O TYPE (1) DESCRIPTION
NAME DRV8412 DRV8432
OUT_D 39 22 O Output, half-bridge D
PVDD_A 26, 27 34 P Power supply input for half-bridge A requires close decoupling capacitor to ground.
PVDD_B 32 29 P Power supply input for half-bridge B requires close decoupling capacitor to gound.
PVDD_C 35 26 P Power supply input for half-bridge C requires close decoupling capacitor to ground.
PVDD_D 40, 41 21 P Power supply input for half-bridge D requires close decoupling capacitor to ground.
PWM_A 17 4 I Input signal for half-bridge A
PWM_B 15 6 I Input signal for half-bridge B
PWM_C 7 14 I Input signal for half-bridge C
PWM_D 5 16 I Input signal for half-bridge D
RESET_AB 16 5 I Reset signal for half-bridge A and half-bridge B, active-low
RESET_CD 6 15 I Reset signal for half-bridge C and half-bridge D, active-low
FAULT 18 3 O Fault signal, open-drain, active-low. An internal pullup resistor to VREG (3.3 V)
is provided on output. Level compliance for 5-V logic can be obtained by adding
external pullup resistor to 5 V
VDD 2 17 P Power supply for digital voltage regulator requires capacitor to ground for
decoupling.
VREG 11 10 P Digital regulator supply filter pin requires 0.1-μF capacitor to AGND.
THERMAL PAD — N/A T Solder the exposed thermal pad to the landing pad on the pcb. Connect landing pad
to bottom side of pcb through via for better thermal dissipation. This pad should be
connected to GND.
HEAT SLUG N/A — T Mount heat sink with thermal interface on top of the heat slug for best thermal
performance.

(1) I = input, O = output, P = power, T = thermal

Table 4-2. Mode Selection Pins

MODE PINS OUTPUT
DESCRIPTION
M3 M2 M1 CONFIGURATION

Dual full bridges (two PWM inputs each full bridge) or four half bridges with
0 0 0 2 FB or 4 HB
cycle-by-cycle current limit
Dual full bridges (two PWM inputs each full bridge) or four half bridges with
0 0 1 2 FB or 4 HB
OC latching shutdown (no cycle-by-cycle current limit)
0 1 0 1 PFB Parallel full bridge with cycle-by-cycle current limit
Dual full bridges (one PWM input each full bridge with complementary PWM
0 1 1 2 FB
on second half bridge) with cycle-by-cycle current limit
1 x x Reserved

4 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: DRV8412 DRV8432

 DRV8412, DRV8432
www.ti.com SLES242H – DECEMBER 2009 – REVISED JULY 2024

5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VDD to GND –0.3 13.2 V
GVDD_X to GND –0.3 13.2 V
PVDD_X to GND_X (2) –0.3 70 V
OUT_X to GND_X (2) –0.3 70 V
BST_X to GND_X (2) –0.3 80 V
Transient peak output current (per pin), pulse width limited by 16 A
internal overcurrent protection circuit
Transient peak output current for latch shut down (per pin) 20 A
VREG to AGND –0.3 4.2 V
GND_X to GND –0.3 0.3 V
GND to AGND –0.3 0.3 V
PWM_X to GND –0.3 VREG + 0.5 V
OC_ADJ, M1, M2, M3 to AGND –0.3 4.2 V
RESET_X, FAULT, OTW to GND –0.3 7 V
Continuous sink current ( FAULT, OTW) 9 mA
Operating junction temperature, TJ –40 150
°C
Storage temperature, Tstg –55 150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Section 5.3.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) These are the maximum allowed voltages for transient spikes. Absolute maximum DC voltages are lower.

5.2 ESD Ratings

VALUE UNIT
Charged device model (CDM), per JEDEC specification JESD22-C101,
V(ESD) Electrostatic discharge ±1500 V
all pins(1)

(1) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
PVDD_X Half bridge X (A, B, C, or D) DC supply voltage 0 50 52.5
GVDD_X Supply for logic regulators and gate-drive circuitry 10.8 12 13.2 V
VDD Digital regulator supply voltage 10.8 12 13.2
IO_PULSE Pulsed peak current per output pin (could be limited by thermal) 15 A
IO Continuous current per output pin (DRV8432) 9 mA
FSW PWM switching frequency 500 kHz
ROCP_CBC OC programming resistor range in cycle-by-cycle current limit modes 24 200
kΩ
ROCP_OCL OC programming resistor range in OC latching shutdown modes 22 200
CBST Bootstrap capacitor range 33 220 nF
tON_MIN Minimum PWM pulse duration, low side, for charging the Bootstrap capacitor 50 ns
TA Operating ambient temperature –40 85 °C

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5

Product Folder Links: DRV8412 DRV8432
DRV8412, DRV8432
SLES242H – DECEMBER 2009 – REVISED JULY 2024 www.ti.com

5.4 Thermal Information

DRV8412 DRV8432
DDW DKD
THERMAL METRIC(1) UNIT
PACKAGE PACKAGE
44 PINS 36 PINS
13.3
RθJA Junction-to-ambient thermal resistance 24.5
(with heat sink)
RθJC(top) Junction-to-case (top) thermal resistance 7.8 0.4
RθJB Junction-to-board thermal resistance 5.5 13.3 °C/W
ψJT Junction-to-top characterization parameter 0.1 0.4
ψJB Junction-to-board characterization parameter 5.4 13.3
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.2 N/A

(1) for more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

5.5 Package Heat Dissipation Ratings

PARAMETER DRV8412 DRV8432
RθJC, junction-to-case (power pad / heat slug) thermal
1.1 °C/W 0.9 °C/W
resistance
This device is not intended to be used without a
RθJA, junction-to-ambient thermal resistance 25 °C/W heatsink. Therefore, RθJA is not specified. See the
Thermal Information section.
Exposed power pad / heat slug area 34 mm2 80 mm2

5.6 Package Power Deratings (DRV8412)(1)

DERATING
TA = 25°C
FACTOR TA = 70°C POWER TA = 85°C POWER TA = 125°C POWER
PACKAGE POWER
ABOVE TA = RATING RATING RATING
RATING
25°C
44-PIN TSSOP (DDW) 5.0 W 40.0 mW/°C 3.2 W 2.6 W 1.0 W

(1) Based on EVM board layout

6 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: DRV8412 DRV8432

 DRV8412, DRV8432
www.ti.com SLES242H – DECEMBER 2009 – REVISED JULY 2024

5.7 Electrical Characteristics

TA = 25°C, PVDD = 50V, GVDD = VDD = 12V, fSw = 400kHz, unless otherwise noted. All performance is in accordance with
recommended operating conditions unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
VREG Voltage regulator, only used as a reference node VDD = 12 V 2.95 3.3 3.65 V
Idle, reset mode 9 12 mA
IVDD VDD supply current
Operating, 50% duty cycle 10.5
Reset mode 1.7 2.5 mA
IGVDD_X Gate supply current per half-bridge
Operating, 50% duty cycle 8
IPVDD_X Half-bridge X (A, B, C, or D) idle current Reset mode 0.7 1 mA
OUTPUT STAGE
TJ = 25°C, GVDD = 12 V, Includes metallization
MOSFET drain-to-source resistance, low side (LS) 110
bond wire and pin resistance
RDS(on) mΩ
TJ = 25°C, GVDD = 12 V, Includes metallization
MOSFET drain-to-source resistance, high side (HS) 110
bond wire and pin resistance
VF Diode forward voltage drop TJ = 25°C - 125°C, IO = 5 A 1 V
tR Output rise time Resistive load, IO = 5 A 14
tF Output fall time Resistive load, IO = 5 A 14
tPD_ON Propagation delay when FET is on Resistive load, IO = 5 A 38 ns
tPD_OFF Propagation delay when FET is off Resistive load, IO = 5 A 38
tDT Dead time between HS and LS FETs Resistive load, IO = 5 A 5.5
I/O PROTECTION
Gate supply voltage GVDD_X undervoltage
Vuvp,G 8.5
protection threshold V
Vuvp,hyst (1) Hysteresis for gate supply undervoltage event 0.8
OTW(1) Overtemperature warning 115 125 135
OTWhyst (1) Hysteresis temperature to reset OTW event 25
OTSD(1) Overtemperature shut down 150
°C
OTE- OTE-OTW overtemperature detect temperature
25
OTWdifferential (1) difference
Hysteresis temperature for FAULT to be released
OTSDHYST (1) 25
following an OTSD event
IOC Overcurrent limit protection Resistor—programmable, nominal, ROCP = 27 kΩ 9.7 A
Time from application of short condition to Hi-Z of
IOCT Overcurrent response time 250 ns
affected FET(s)
Internal pulldown resistor at the output of each half- Connected when RESET_AB or RESET_CD is
RPD 1 kΩ
bridge active to provide bootstrap capacitor charge
STATIC DIGITAL SPECIFICATIONS
VIH High-level input voltage PWM_A, PWM_B, PWM_C, PWM_D, M1, M2, M3 2 3.6
VIH High-level input voltage RESET_AB, RESET_CD 2 5.5
V
PWM_A, PWM_B, PWM_C, PWM_D, M1, M2,
VIL Low-level input voltage 0.8
M3, RESET_AB, RESET_CD
llkg Input leakage current –100 100 μA
OTW / FAULT
Internal pullup resistance, OTW to VREG, FAULT to
RINT_PU 20 26 35 kΩ
VREG
Internal pullup resistor only 2.95 3.3 3.65
VOH High-level output voltage
External pullup of 4.7 kΩ to 5 V 4.5 5 V
VOL Low-level output voltage IO = 4 mA 0.2 0.4

(1) Specified by design

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7

Product Folder Links: DRV8412 DRV8432
DRV8412, DRV8432
SLES242H – DECEMBER 2009 – REVISED JULY 2024 www.ti.com

5.8 Typical Characteristics

100 1.10

Normalized RDS(on) / (RDS(on) at 12 V)

90
1.08
80
70 1.06
Efficiency (%)

60 1.04
50
1.02
40
30 1.00
20
0.98
10
0 0.96
0 50 100 150 200 250 300 350 400 450 500 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12
Switching Frequency (kHz) Gate Drive (V)
Full Bridge Load = 5A PVDD = 50V Tc = 75°C TJ = 25°C
Figure 5-1. Efficiency vs Switching Frequency (DRV8432) Figure 5-2. Normalized RDS(On) vs Gate Drive
Normalized RDS(on) / (RDS(on) at 25oC)

1.6 6

1.4 5

4
1.2
Current (A)

3
1.0
2
0.8
1
0.6 0

0.4 –1
–40 –20 0 20 40 60 80 100 120 140 0 0.2 0.4 0.6 0.8 1 1.2
o
TJ – Junction Temperature – C Voltage (V)
GVDD = 12V TJ = 25°C
Figure 5-3. Normalized Rds(On) vs Junction Temperature Figure 5-4. Drain To Source Diode Forward On Characteristics
100
90
80
Output Duty Cycle (%)

70
60
50
40
30
20
10
0
0 10 20 30 40 50 60 70 80 90 100
Input Duty Cycle (%)
fs = 500kHz TC = 25°C
Figure 5-5. Output Duty Cycle vs Input Duty Cycle

8 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: DRV8412 DRV8432

 DRV8412, DRV8432
www.ti.com SLES242H – DECEMBER 2009 – REVISED JULY 2024

6 Detailed Description
6.1 Overview
The DRV841x2 is a high performance, integrated dual full bridge motor driver with an advanced protection
system.
Because of the low RDS(on) of the H-Bridge MOSFETs and intelligent gate drive design, the efficiency of these
motor drivers can be up to 97%, which enables the use of smaller power supplies and heatsinks, and are good
candidates for energy efficient applications.

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9

Product Folder Links: DRV8412 DRV8432
DRV8412, DRV8432
SLES242H – DECEMBER 2009 – REVISED JULY 2024 www.ti.com

6.2 Functional Block Diagram

4 VDD
Under-
OTW voltage 4
Protection
Internal Pullup VREG VREG
Resistors to VREG

FAULT
Power
On
M1
Reset AGND
Protection
M2 and
I/O Logic
M3 Temp.
Sense GND

RESET_AB
Overload
RESET_CD Isense OC_ADJ
Protection

GVDD_D
BST_D
PVDD_D
PWM Gate
PWM_D Ctrl. Timing OUT_D
Rcv. Drive
FB/PFB−Configuration
Pulldown Resistor

GND_D
GVDD_C
BST_C
PVDD_C
PWM Gate
PWM_C Ctrl. Timing OUT_C
Rcv. Drive
FB/PFB−Configuration
Pulldown Resistor

GND_C
GVDD_B
BST_B
PVDD_B
PWM Gate
PWM_B Ctrl. Timing OUT_B
Rcv. Drive
FB/PFB−Configuration
Pulldown Resistor

GND_B
GVDD_A
BST_A
PVDD_A
PWM Gate
PWM_A Ctrl. Timing OUT_A
Rcv. Drive
FB/PFB−Configuration
Pulldown Resistor

GND_A

10 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: DRV8412 DRV8432

 DRV8412, DRV8432
www.ti.com SLES242H – DECEMBER 2009 – REVISED JULY 2024

6.3 Feature Description

6.3.1 Error Reporting
The FAULT and OTW pins are both active-low, open-drain outputs. Their function is for protection-mode
signaling to a PWM controller or other system-control device.
Any fault resulting in device shutdown, such as overtemperatue shutdown, overcurrent shutdown, or
undervoltage protection, is signaled by the FAULT pin going low. Also, OTW goes low when the device junction
temperature exceeds 125°C (see Table 6-1).
Table 6-1. Protection Mode Signal Descriptions
FAULT OTW DESCRIPTION
0 0 Overtemperature warning and (overtemperature shut-down or overcurrent shut-down or undervoltage
protection) occurred
0 1 Overcurrent shut-down or GVDD undervoltage protection occurred
1 0 Overtemperature warning
1 1 Device under normal operation

TI recommends monitoring the OTW signal using the system microcontroller and responding to an OTW
signal by reducing the load current to prevent further heating of the device resulting in device overtemperature
shutdown (OTSD).
To reduce external component count, an internal pullup resistor to VREG (3.3V) is provided on both FAULT and
OTW outputs. Level compliance for 5V logic can be obtained by adding external pullup resistors to 5V (see the
Electrical Characteristics section of this data sheet for further specifications).
6.3.2 Device Protection System
The DRV841x2 contains advanced protection circuitry carefully designed to facilitate system integration and
ease of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions
such as short circuits, overcurrent, overtemperature, and undervoltage. The DRV841x2 responds to a fault by
immediately setting the half bridge outputs in a high-impedance (Hi-Z) state and asserting the FAULT pin low. In
situations other than overcurrent or overtemperature, the device automatically recovers when the fault condition
has been removed or the gate supply voltage has increased. For highest possible reliability, reset the device
externally no sooner than 1 second after the shutdown when recovering from an overcurrent shut down (OCSD)
or OTSD fault.
6.3.2.1 Bootstrap Capacitor Undervoltage Protection
When the device runs at a low switching frequency (for example, less than 10 kHz with a 100-nF bootstrap
capacitor), the bootstrap capacitor voltage might not be able to maintain a proper voltage level for the high-
side gate driver. A bootstrap capacitor undervoltage protection circuit (BST_UVP) prevents potential failure
of the high-side MOSFET. When the voltage on the bootstrap capacitors is less than the required value for
safe operation, the DRV841x2 initiates bootstrap capacitor recharge sequences (turn off high side FET for a
short period) until the bootstrap capacitors are properly charged for safe operation. This function may also be
activated when PWM duty cycle is too high (for example, less than 20ns off time at 10kHz). Note that bootstrap
capacitor might not be able to be charged if no load or extremely light load is presented at output during
BST_UVP operation, so it is recommended to turn on the low side FET for at least 50 ns for each PWM cycle to
avoid BST_UVP operation if possible.
For applications with lower than 10-kHz switching frequency and not to trigger BST_UVP protection, a larger
bootstrap capacitor can be used (for example, 1-µF capacitor for 800-Hz operation). When using a bootstrap cap
larger than 220 nF, it is recommended to add 5-Ω resistors between 12-V GVDD power supply and GVDD_X
pins to limit the inrush current on the internal bootstrap circuitry.

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11

Product Folder Links: DRV8412 DRV8432
DRV8412, DRV8432
SLES242H – DECEMBER 2009 – REVISED JULY 2024 www.ti.com

6.3.2.2 Overcurrent (OC) Protection

The DRV841x2 has independent, fast-reacting current detectors with programmable trip threshold (OC
threshold) on all high-side and low-side power-stage FETs. There are two settings for OC protection through
mode selection pins: cycle-by-cycle (CBC) current limiting mode and OC latching (OCL) shut down mode.
In CBC current limiting mode, the detector outputs are monitored by two protection systems. The first protection
system controls the power stage to prevent the output current from further increasing, that is, performing as a
CBC current-limiting function rather than prematurely shutting down the device. This feature could effectively
limit the inrush current during motor start-up or transient without damaging the device. During short to power and
short to ground conditions, the current limit circuitry might not be able to control the current to a proper level,
a second protection system triggers a latching shutdown, resulting in the related half bridge being set in the
high-impedance (Hi-Z) state. Current limiting and overcurrent protection are independent for half-bridges A, B, C,
and, D, respectively.
Figure 6-1 illustrates cycle-by-cycle operation with high side OC event and Figure 6-2 shows cycle-by-cycle
operation with low side OC. Dashed lines are the operation waveforms when no CBC event is triggered and solid
lines show the waveforms when CBC event is triggered. In CBC current limiting mode, when low side FET OC is
detected, the device turns off the affected low side FET and keep the high side FET at the same half bridge off
until the next PWM cycle. When high side FET OC is detected, the device turns off the affected high side FET
and turn on the low side FET at the half bridge until next PWM cycle.
It is important to note that if the input to a half bridge is held to a constant value when an over current event
occurs in CBC, then the associated half bridge will be in a HI-Z state upon the over current event ending. Cycling
IN_X allows OUT_X to resume normal operation.
In OC latching shut down mode, the CBC current limit and error recovery circuits are disabled and an
overcurrent condition will cause the device to shutdown immediately. After shutdown, RESET_AB and/or
RESET_CD must be asserted to restore normal operation after the overcurrent condition is removed.
For added flexibility, the OC threshold is programmable using a single external resistor connected between the
OC_ADJ pin and GND pin. See Table 6-2 for information on the correlation between programming-resistor value
and the OC threshold. The values in Table 6-2 show typical OC thresholds for a given resistor. Assuming a
fixed resistance on the OC_ADJ pin across multiple devices, a 20% device-to-device variation in OC threshold
measurements is possible. Therefore, this feature is designed for system protection and not for precise current
control. Noter that a properly functioning overcurrent detector assumes the presence of a proper inductor or
power ferrite bead at the power-stage output. Short-circuit protection is not guaranteed with direct short at the
output pins of the power stage.
For normal operation, inductance in motor (assume larger than 10µH) is sufficient to provide low di/dt output
(for example, for EMI) and proper protection during overload condition (CBC current limiting feature). So no
additional output inductors are needed during normal operation.
However, during a short condition, the motor (or other load) is shorted, so the load inductance is not present in
the system anymore; the current in the device can reach such a high level that may exceed the abs max current
rating due to extremely low impenitence in the short circuit path and high di/dt before oc detection circuit kicks in.
So, a ferrite bead or inductor is recommended to use the short-circuit protection feature in DRV841x2. With an
external inductance or ferrite bead, the current rises at a much slower rate and reach a lower current level before
oc protection starts. The device then either operates CBC current limit or OC shut down automatically (when
current is well above the current limit threshold) to protect the system.
For a system that has limited space, a power ferrite bead can be used instead of an inductor. The current rating
of ferrite bead has to be higher than the RMS current of the system at normal operation. A ferrite bead designed
for very high frequency is NOT recommended. A minimum impedance of 10Ω or higher is recommended at
10MHz or lower frequency to effectively limit the current rising rate during short circuit condition.
The TDK MPZ2012S300A (with size of 0805 inch type) have been tested in our system to meet a short circuit
condition in the DRV8412. But other ferrite beads that have similar frequency characteristics can be used as
well.

12 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: DRV8412 DRV8432

 DRV8412, DRV8432
www.ti.com SLES242H – DECEMBER 2009 – REVISED JULY 2024

For higher power applications, such as in the DRV8432, there might be limited options to select suitable ferrite
bead with high current rating. If an adequate ferrite bead cannot be found, an inductor can be used.
The inductance can be calculated as:

PVDD × Toc _ delay

Loc _ min =
Ipeak - Iave (1)

where
• Toc_delay = 250nS
• Ipeak = 15A (below abs max rating)
Because an inductor usually saturates after reaching the current rating, the recommendation is to use an
inductor with a doubled value or an inductor with a current rating well above the operating condition.
Table 6-2. Programming-Resistor Values and OC
Threshold
OC-ADJUST RESISTOR MAXIMUM CURRENT BEFORE
VALUES (kΩ) OC OCCURS (A)
22(1) 11.6
24 10.7
27 9.7
30 8.8
36 7.4

(1) Recommended to use in OC Latching Mode Only

6.3.2.3 Overtemperature Protection

The DRV841x2 has a two-level temperature-protection system that asserts an active-low warning signal ( OTW)
when the device junction temperature exceeds 125°C (nominal) and, if the device junction temperature exceeds
150°C (nominal), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the
high-impedance (Hi-Z) state and FAULT being asserted low. OTSD is latched in this case and RESET_AB and
RESET_CD must be asserted low to clear the latch.
6.3.2.4 Undervoltage Protection (UVP) and Power-On Reset (POR)
The UVP and POR circuits of the DRV841x2 fully protect the device in any power-up/down and brownout
situation. While powering up, the POR circuit resets the overcurrent circuit and ensures that all circuits are fully
operational when the GVDD_X and VDD supply voltages reach 9.8 V (typical). Although GVDD_X and VDD are
independently monitored, a supply voltage drop below the UVP threshold on any VDD or GVDD_X pin results in
all half-bridge outputs immediately being set in the high-impedance (Hi-Z) state and FAULT being asserted low.
The device automatically resumes operation when all supply voltage on the bootstrap capacitors have increased
above the UVP threshold.
6.3.3 Device Reset
Two reset pins are provided for independent control of half-bridges A/B and C/D. When RESET_AB is asserted
low, all four power-stage FETs in half-bridges A and B are forced into a high-impedance (Hi-Z) state. Likewise,
asserting RESET_CD low forces all four power-stage FETs in half-bridges C and D into a high- impedance
state. To accommodate bootstrap charging prior to switching start, asserting the reset inputs low enables weak
pulldown of the half-bridge outputs.
A rising-edge transition on reset input allows the device to resume operation after a shut-down fault. For
example, when either or both half-bridge A and B have OC shutdown, a low to high transition of RESET_AB
pin clears the fault and FAULT pin; when either or both half-bridge C and D have OC shutdown, a low to high
transition of RESET_CD pin will clear the fault and FAULT pin as well. When an OTSD occurs, both RESET_AB
and RESET_CD need to have a low to high transition to clear the fault and FAULT signal.

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13

Product Folder Links: DRV8412 DRV8432
DRV8412, DRV8432
SLES242H – DECEMBER 2009 – REVISED JULY 2024 www.ti.com

6.4 Device Functional Modes

The DRV841x2 supports four different modes of operation:
1. Dual full bridges (FB) (two PWM inputs each full bridge) or four half bridges (HB) with CBC current limit
2. Dual full bridges (two PWM inputs each full bridge) or four half bridges with OC latching shutdown (no CBC
current limit)
3. Parallel full bridge (PFB) with CBC current limit
4. Dual full bridges (one PWM input each full bridge) with CBC current limit
In mode 1 and 2, PWM_A controls half bridge A, PWM_B controls half bridge B, and so forth Figure 7-1 shows
an application example for full bridge mode operation.
In parallel full bridge mode (mode 3), PWM_A controls both half bridges A and B, and PWM_B controls both half
bridges C and D, while PWM_C and PWM_D pins are not used (recommended to connect to ground). Bridges
A and B are synchronized internally (even during CBC), and so are bridges C and D. OUT_A and OUT_B
should be connected together and OUT_C and OUT_D should be connected together after the output inductor or
ferrite bead. If RESET_AB or RESET_CD are low, all four outputs become high-impedance. Figure 7-8 shows an
example of parallel full bridge mode connection.
In mode 4, one PWM signal controls one full bridge to relieve some I/O resource from MCU, that is, PWM_A
controls half bridges A and B and PWM_C controls half bridges C and D. In this mode, the operation of half
bridge B is complementary to half bridge A, and the operation of half bridge D is complementary to half bridge C.
For example, when PWM_A is high, high side FET in half bridge A and low side FET in half bridge B will be on
and low side FET in half bridge A and high side FET in half bridge B will be off. Since PWM_B and PWM_D pins
are not used in this mode, it is recommended to connect them to ground.
In operation modes 1, 2, and 4 (CBC current limit is used), once the CBC current limit is hit, the driver will be
deactivated until the next PWM cycle starts. However, in order for the output to be recovered, the PWM input
corresponding to that driver in CBC must be toggled. Because of this, CBC mode does not support operation
when one half-bridge PWM input is tied to dc logic level.
Because each half bridge has independent supply and ground pins, a shunt sensing resistor can be inserted
between PVDD to PVDD_X or GND_X to GND (ground plane). A high side shunt resistor between PVDD and
PVDD_X is recommended for differential current sensing because a high bias voltage on the low side sensing
could affect device operation. If low side sensing has to be used, a shunt resistor value of 10 mΩ or less or
sense voltage 100mV or less is recommended.
During T_OC Period CBC with High Side OC

PVDD
Current Limit
Load
PWM_HS Current

Load PWM_HS

PWM_LS
PWM_LS
GND_X

T_HS T_OC T_LS

Dashed line: normal operation; solid line: CBC event

Figure 6-1. Cycle-by-Cycle Operation With High-Side OC

14 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: DRV8412 DRV8432

 DRV8412, DRV8432
www.ti.com SLES242H – DECEMBER 2009 – REVISED JULY 2024

During T_OC Period CBC with Low Side OC

PVDD
Current Limit
Load
PWM_HS Current

PWM_HS
Load

PWM_LS PWM_LS

GND_X T_LS T_OC T_HS

Dashed line: normal operation; solid line: CBC event

Figure 6-2. Cycle-by-Cycle Operation With Low-Side OC

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 15

Product Folder Links: DRV8412 DRV8432
DRV8412, DRV8432
SLES242H – DECEMBER 2009 – REVISED JULY 2024 www.ti.com

Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.

1 Application Information
The DRV841x2 devices are typically used to drive 2 brushed DC or 1 stepper motor.
The DRV841x2 can be used for stepper motor applications as illustrated in Figure 7-9; the devices can be
also used in three phase permanent magnet synchronous motor (PMSM) and sinewave brushless DC motor
applications.
Figure 7-10 shows an example of a TEC driver application. The same configuration can also be used for DC
output applications.
2 Typical Applications
2.1 Full Bridge Mode Operation
GVDD 1uF
PVDD
330 uF 3.3
1000 uF
1uF GVDD_B GVDD_A 10 nF

OTW BST_A
100 nF
FAULT PVDD_A
Rsense_AB (option)
PWM_A OUT_A
100nF
RESET_AB GND_A
M
Controller PWM_B GND_B
Roc_adj 100nF
(MSP430
OC_ADJ OUT_B
C2000 or 1
Stellaris MCU) GND PVDD_B

AGND BST_B 100 nF

100 nF 100 nF
VREG BST_C

M3 PVDD_C
Rsense_CD (option)
M2 OUT_C
100nF
M1 GND_C
M
PWM_C GND_D
100nF
RESET_CD OUT_D

PWM_D PVDD_D
100 nF
GVDD VDD BST_D
1uF PVDD
47 uF GVDD_C GVDD_D

1uF 1uF

Figure 7-1. Application Diagram Example for Full Bridge Mode Operation Schematic

16 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: DRV8412 DRV8432

 DRV8412, DRV8432
www.ti.com SLES242H – DECEMBER 2009 – REVISED JULY 2024

2.1.1 Design Requirements

This section describes design considerations.
Table 7-1. Design Parameters
DESIGN PARAMETER REFERENCE EXAMPLE VALUE
Motor voltage PVDD_x 24V
Motor current (peak and RMS) IPVDD 6A peak, 3A RMS
Overcurrent threshold OCTH OC_ADJ = 27kΩ, 9.7A
Bridge mode M1M2 Parallel full bridge

2.1.2 Detailed Design Procedure

2.1.2.1 Motor Voltage
Higher voltages generally have the advantage of causing current to change faster through the inductive
windings, which allows for higher RPMs. Lower voltages allow for more accurate control of phase currents.
2.1.2.2 Current Requirement of 12V Power Supply
The DRV83x2 requires a 12V power supply for GVDD and VDD pins. The total supply current is relatively low
at room temperature (less than 50mA), but the current could increase significantly when the device temperature
goes too high (for example, above 125°C), especially at heavy load conditions due to substrate current collection
by 12V guard rings. TI recommends designing the 12V power supply with a current capability at least 5-10% of
the load current, and no less than 100mA for the device performance across all temperature ranges.
2.1.2.3 Voltage of Decoupling Capacitor
The voltage of the decoupling capacitors should be selected in accordance with good design practices.
Temperature, ripple current, and voltage overshoot must be considered. The high frequency decoupling
capacitor should use ceramic capacitor with X5R or better rating. For a 50V application, a minimum voltage
rating of 63V is recommended.
2.1.2.4 Overcurrent Threshold
When choosing the resistor value for OC_ADJ, consider the peak current allowed under normal system
behavior, the resistor tolerance, and that Table 6-2 currents have a ±10% tolerance. For example, if 6A is
the highest system current allowed across all normal behavior, a 27kΩ OC_ADJ resistor with 10% tolerance is a
reasonable choice, as it would set the OCTH to approximately 8A to 12A.
2.1.2.5 Sense Resistor
For optimal performance, the sense resistor must be:
• Surface-mount
• Low inductance
• Rated for high enough power
• Placed closely to the motor driver
The power dissipated by the sense resistor equals IRMS 2 x R. For example, if peak motor current is 3A, RMS
motor current is 2A, and a 0.05Ω sense resistor is used, the resistor will dissipate 2A² × 0.05Ω = 0.2W. The
power increases quickly with higher current levels.
Resistors typically have a rated power within some ambient temperature range, along with a de-rated power
curve for high ambient temperatures. When a PCB is shared with other components generating heat, margin
should be added. Always measure the actual sense resistor temperature in a final system, along with the power
MOSFETs, as those are often the hottest components.
Because power resistors are larger and more expensive than standard resistors, use multiple standard resistors
in parallel, between the sense node and ground. This distributes the current and heat dissipation.

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 17

Product Folder Links: DRV8412 DRV8432
DRV8412, DRV8432
SLES242H – DECEMBER 2009 – REVISED JULY 2024 www.ti.com

2.1.3 Application Curves

Figure 7-2. Brushed DC Driving Figure 7-3. Stepper Control, Full Stepping, 24V

Figure 7-4. Stepper Control, Full Stepping, 12V Figure 7-5. Stepper Control, Half Stepping, 12V

Figure 7-6. Stepper Control, 128 Microstepping, 12V Figure 7-7. PWM_A to OUTA

18 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: DRV8412 DRV8432

 DRV8412, DRV8432
www.ti.com SLES242H – DECEMBER 2009 – REVISED JULY 2024

2.2 Parallel Full Bridge Mode Operation

GVDD 1uF
PVDD
330 uF
3.3
1000 uF
1uF GVDD_B GVDD_A 10 nF

OTW BST_A
100 nF
FAULT PVDD_A Rsense_AB
(option)
PWM_A OUT_A
100nF Loc
RESET_AB GND_A

Controller PWM_B GND_B

Roc_adj 100nF Loc
(MSP430
OC_ADJ OUT_B
C2000 or 1
Stellaris MCU) GND PVDD_B M
AGND BST_B
100 nF
100 nF 100 nF
VREG BST_C

M3 PVDD_C Rsense_CD
(option)
M2 OUT_C
100nF Loc
M1 GND_C

PWM_C GND_D
100nF Loc
RESET_CD OUT_D

PWM_D PVDD_D
100 nF
GVDD VDD BST_D
1uF PVDD
47 uF GVDD_C GVDD_D

1uF 1uF

PWM_A controls OUT_A and OUT_B; PWM_B controls OUT_C and OUT_D.

Figure 7-8. Application Diagram Example for Parallel Full Bridge Mode Operation Schematic

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 19

Product Folder Links: DRV8412 DRV8432
DRV8412, DRV8432
SLES242H – DECEMBER 2009 – REVISED JULY 2024 www.ti.com

2.3 Stepper Motor Operation

GVDD 1uF
PVDD
330 uF 3.3
1000 uF
1uF GVDD_B GVDD_A 10 nF

OTW BST_A
100 nF
FAULT PVDD_A

PWM_A OUT_A
100nF
RESET_AB GND_A
M
Controller PWM_B GND_B
Roc_adj
(MSP430 100nF
OC_ADJ OUT_B
C2000 or 1
Stellaris MCU) GND PVDD_B

AGND BST_B
100 nF 100 nF
100 nF
VREG BST_C

M3 PVDD_C

M2 OUT_C
100nF
M1 GND_C

PWM_C GND_D
100nF
RESET_CD OUT_D

PWM_D PVDD_D
100 nF
GVDD VDD BST_D
1uF PVDD
47 uF GVDD_C GVDD_D

1uF 1uF

Figure 7-9. Application Diagram Example for Stepper Motor Operation Schematic

20 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: DRV8412 DRV8432

 DRV8412, DRV8432
www.ti.com SLES242H – DECEMBER 2009 – REVISED JULY 2024

2.4 TEC Driver

GVDD 1uF
PVDD
330 uF 3.3
1000 uF
1uF GVDD_B GVDD_A 10 nF

OTW BST_A
100 nF
FAULT PVDD_A

PWM_A OUT_A
4.7 uH
100nF 47 uF
RESET_AB GND_A

PWM_B GND_B
Roc_adj 4.7 uH
TEC OC_ADJ OUT_B
100nF
Controller 1
GND PVDD_B 47 uF

AGND

TEC
BST_B
100 nF 100 nF
VREG BST_C 100 nF 47 uF

M3 PVDD_C

M2 OUT_C
100nF 4.7 uH
M1 GND_C 47 uF

PWM_C GND_D
4.7 uH
100nF
RESET_CD OUT_D

PWM_D PVDD_D 47 uF
100 nF
GVDD VDD BST_D
1uF PVDD
47 uF GVDD_C GVDD_D

1uF 1uF

Figure 7-10. Application Diagram Example for TEC Driver Schematic

2.5 LED Lighting Driver

VIN
12V Up to 50V
GVDD_B

GVDD_C

GVDD_D

VDD
GVDD_A

RESET_AB PVDD_A

RESET_CD PVDD_B

PWM_A PVDD_C

PWM_B PVDD_D

PWM_C BST_A
VLED
PWM_D OUT_A

BST_B
FAULT

OTW
DRV8412 OUT_B

BST_C
OC_ADJ
OUT_C

BST_D

OUT_D
M1
M2 VREG
GND_A

GND_B

GND_C

GND_D
AGND

GND

M3

Figure 7-11. Application Diagram Example for LED Lighting Driver Schematic

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 21

Product Folder Links: DRV8412 DRV8432
DRV8412, DRV8432
SLES242H – DECEMBER 2009 – REVISED JULY 2024 www.ti.com

3 Power Supply Recommendations

3.1 Bulk Capacitance
Having an appropriate local bulk capacitance is an important factor in motor drive system design. It is generally
beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size.
The amount of local capacitance needed depends on a variety of factors, including:
• The highest current required by the motor system
• The power supply capacitance and ability to source current
• The amount of parasitic inductance between the power supply and motor system
• The acceptable voltage ripple
• The type of motor used (Brushed DC, Brushless DC, Stepper)
• The motor braking method
The inductance between the power supply and the motor drive system limits the rate current can change from
the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands
or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage
remains stable and high current can be quickly supplied.
The data sheet provides a recommended value, but system-level testing is required to determine the appropriate
sized bulk capacitor.

Parasitic Wire
Inductance
Power Supply Motor Drive System

VM

+ + Motor
± Driver

GND

Local IC Bypass
Bulk Capacitor Capacitor

Figure 7-12. Example Setup of Motor Drive System With External Power Supply

The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases
when the motor transfers energy to the supply.
3.2 Power Supplies
To facilitate system design, the DRV841x2 needs only a 12V supply in addition to H-Bridge power supply
(PVDD). An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog
circuitry. Additionally, the high-side gate drive requires a floating voltage supply, which is accommodated by
built-in bootstrap circuitry requiring external bootstrap capacitor.
To provide symmetrical electrical characteristics, the PWM signal path, including gate drive and output stage,
is designed as identical, independent half-bridges. For this reason, each half-bridge has a separate gate
drive supply (GVDD_X), a bootstrap pin (BST_X), and a power-stage supply pin (PVDD_X). Furthermore, an
additional pin (VDD) is provided as supply for all common circuits. Special attention should be paid to place
all decoupling capacitors as close to their associated pins as possible. In general, inductance between the
power supply pins and decoupling capacitors must be avoided. Furthermore, decoupling capacitors need a short
ground path back to the device.

22 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: DRV8412 DRV8432

 DRV8412, DRV8432
www.ti.com SLES242H – DECEMBER 2009 – REVISED JULY 2024

For a properly functioning bootstrap circuit, a small ceramic capacitor (an X5R or better) must be connected
from each bootstrap pin (BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low,
the bootstrap capacitor is charged through an internal diode connected between the gate-drive power-supply
pin (GVDD_X) and the bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is
shifted above the output potential and thus provides a suitable voltage supply for the high-side gate driver. In
an application with PWM switching frequencies in the range from 10kHz to 500kHz, the use of 100-nF ceramic
capacitors (X5R or better), size 0603 or 0805, is recommended for the bootstrap supply. These 100nF capacitors
ensure sufficient energy storage, even during minimal PWM duty cycles, to keep the high-side power stage FET
fully turned on during the remaining part of the PWM cycle. In an application running at a switching frequency
lower than 10 kHz, the bootstrap capacitor might need to be increased in value.
Special attention should be paid to the power-stage power supply; this includes component selection, PCB
placement, and routing. As indicated, each half-bridge has independent power-stage supply pin (PVDD_X). For
optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X pin
is decoupled with a ceramic capacitor (X5R or better) placed as close as possible to each supply pin. It is
recommended to follow the PCB layout of the DRV841x2 EVM board.
The 12V supply should be from a low-noise, low-output-impedance voltage regulator. Likewise, the 50V power-
stage supply is assumed to have low output impedance and low noise. The power-supply sequence is not critical
as facilitated by the internal power-on-reset circuit. Moreover, the DRV841x2 is fully protected against erroneous
power-stage turn-on due to parasitic gate charging. Thus, voltage-supply ramp rates (dv/dt) are non-critical
within the specified voltage range (see Section 5.3 of this data sheet).
3.3 System Power-Up and Power-Down Sequence
3.3.1 Powering Up
The DRV841x2 does not require a power-up sequence. The outputs of the H-bridges remain in a high
impedance state until the gate-drive supply voltage GVDD_X and VDD voltage are above the undervoltage
protection (UVP) voltage threshold (see the Electrical Characteristics section of this data sheet). Although
not specifically required, holding RESET_AB and RESET_CD in a low state while powering up the device is
recommended. This allows an internal circuit to charge the external bootstrap capacitors by enabling a weak
pulldown of the half-bridge output.
3.3.2 Powering Down
The DRV841x2 does not require a power-down sequence. The device remains fully operational as long as the
gate-drive supply (GVDD_X) voltage and VDD voltage are above the UVP voltage threshold (see the Electrical
Characteristics section of this data sheet). Although not specifically required, it is a good practice to hold
RESET_AB and RESET_CD low during power down to prevent any unknown state during this transition.
3.4 System Design Recommendations
3.4.1 VREG Pin
The VREG pin is used for internal logic and not recommended to be used as a voltage source for external
circuitry.
3.4.2 VDD Pin
The transient current in VDD pin could be significantly higher than average current through that pin. A low
resistive path to GVDD should be used. A 22µF to 47µF capacitor should be placed on VDD pin beside the
100nF to 1µF decoupling capacitor to provide a constant voltage during transient.
3.4.3 OTW Pin
OTW reporting indicates the device approaching high junction temperature. This signal can be used with MCU to
decrease system power when OTW is low in order to prevent OT shut down at a higher temperature.

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 23

Product Folder Links: DRV8412 DRV8432
DRV8412, DRV8432
SLES242H – DECEMBER 2009 – REVISED JULY 2024 www.ti.com

3.4.4 Mode Select Pin

Mode select pins (M1, M2, and M3) should be connected to either VREG (for logic high) or AGND for logic low.
The recommendation is to not connect mode pins to board ground if 1Ω resistor is used between AGND and
GND.
3.4.5 Parallel Mode Operation
For a device operated in parallel mode, a minimum of 30 nH to 100 nH inductance or a ferrite bead is required
after the output pins (for example, OUT_A and OUT_B) before connecting the two channels together. This helps
to prevent any shoot through between two paralleled channels during switching transient due to mismatch of
paralleled channels (for example, processor variation, unsymmetrical PCB layout, and so on).
3.4.6 TEC Driver Application
For TEC driver or other non-motor related applications (for example, resistive load or dc output), a low-pass LC
filter can be used to meet the requirement.
4 Layout
4.1 Layout Guidelines
4.1.1 PCB Material Recommendation
FR-4 Glass Epoxy material with 2oz. copper on both top and bottom layer is recommended for improved thermal
performance (better heat sinking) and less noise susceptibility (lower PCB trace inductance).
4.1.2 Ground Plane
Because of the power level of these devices, it is recommended to use a big unbroken single ground plane
for the whole system / board. The ground plane can be easily made at bottom PCB layer. In order to minimize
the impedance and inductance of ground traces, the traces from ground pins should keep as short and wide
as possible before connected to bottom ground plane through vias. Multiple vias are suggested to reduce the
impedance of vias. Try to clear the space around the device as much as possible especially at bottom PCB side
to improve the heat spreading.
4.1.3 Decoupling Capacitor
High frequency decoupling capacitors (100 nF) on PVDD_X pins should be placed close to these pins and with a
short ground return path to minimize the inductance on the PCB trace.
4.1.4 AGND
AGND is a localized internal ground for logic signals. A 1Ω resistor is recommended to be connected between
GND and AGND to isolate the noise from board ground to AGND. There are other two components are
connected to this local ground: 0.1µF capacitor between VREG to AGND and Roc_adj resistor between
OC_ADJ and AGND. Capacitor for VREG should be placed close to VREG and AGND pin and connected
without vias.
4.2 Layout Example
4.2.1 Current Shunt Resistor
If current shunt resistor is connected between GND_X to GND or PVDD_X to PVDD, make sure there is only
one single path to connect each GND_X or PVDD_X pin to shunt resistor, and the path is short and symmetrical
on each sense path to minimize the measurement error due to additional resistance on the trace.
An example of the schematic and PCB layout of DRV8412 are shown in Figure 7-13, Figure 7-14, and Figure
7-15.

24 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: DRV8412 DRV8432

 DRV8412, DRV8432
www.ti.com SLES242H – DECEMBER 2009 – REVISED JULY 2024

GVDD
C14
1.0ufd/16V
0603

GND U1
1 44

43
C13
42
1.0ufd/16V
0603 41
PVDD
40
GND C15 C16
2
0.1ufd/100V 0.1ufd/100V
+ 3 0805 0805
C11 C12
4
47ufd/16V 0.1ufd/16V GND
FC 0603
39
OUTD
GND GND Orange
5 38

37
6
GVDD
J2 GND
1 36
2
OUTC
+ Orange
GRAY C4 C5 7 35
6A/250V
PVDD
330ufd/16V 0.1ufd/16V
M 0603 C18 C19
8
0.1ufd/100V 0.1ufd/100V PVDD
GVDD = 12V 9 0805 0805
GND
10 PVDD
GND Red
J1 34 +
11 C1
1 33
1000ufd/63V
2 C10 VZ
3 0.1ufd/16V
32 GND
0603 PVDD Black
4 12
C20 C21 GND
5
R7 13 0.1ufd/100V 0.1ufd/100V
6 0805 0805
1.0 1/4W
7 0805

8
GND GND
R5 14 31
OUTB
47K 0603 Orange
15 30

29

GND
28
16 OUTA
Orange
17 27
PVDD
26
18 C23 C24
0.1ufd/100V 0.1ufd/100V
0805 U1
19 0805
PowerPad
20
25 GND
21
24
GND
22 23 GVDD
GVDD
C9 DRV8412DDW C8
HTSSOP44-DDW
1.0ufd/16V 1.0ufd/16V
0603 0603

GND GND

Figure 7-13. DRV8412 Schematic Example

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 25

Product Folder Links: DRV8412 DRV8432
DRV8412, DRV8432
SLES242H – DECEMBER 2009 – REVISED JULY 2024 www.ti.com

T1: PVDD decoupling capacitors C16, C19, C21, and C24 should be placed very close to PVDD_X pins and ground return path.
T2: VREG decoupling capacitor C10 should be placed very close to VREG abd AGND pins.
T3: Clear the space above and below the device as much as possible to improve the thermal spreading.
T4: Add many vias to reduce the impedance of ground path through top to bottom side. Make traces as wide as possible for ground
path such as GND_X path.

Figure 7-14. Printed Circuit Board – Top Layer

26 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: DRV8412 DRV8432

 DRV8412, DRV8432
www.ti.com SLES242H – DECEMBER 2009 – REVISED JULY 2024

B1: Do not block the heat transfer path at bottom side. Clear as much space as possible for better heat spreading.

Figure 7-15. Printed Circuit Board – Bottom Layer

4.3 Thermal Considerations

The thermally enhanced package provided with the DRV8432 is designed to interface directly to heat sink using
a thermal interface compound, (for example, Ceramique from Arctic Silver, TIMTronics 413, and so on). The heat
sink then absorbs heat from the ICs and couples to the local air. A good practice is to connect the heatsink to
system ground on the PCB board to reduce the ground noise.
RθJA is a system thermal resistance from junction to ambient air. The system parameters have the following
components:
• RθJC (the thermal resistance from junction to case, or in this example the power pad or heat slug)
• Thermal grease thermal resistance
• Heat sink thermal resistance

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 27

Product Folder Links: DRV8412 DRV8432
DRV8412, DRV8432
SLES242H – DECEMBER 2009 – REVISED JULY 2024 www.ti.com

The thermal grease thermal resistance can be calculated from the exposed power pad or heat slug area and the
thermal grease manufacturer's area thermal resistance (expressed in °C-in2/W or °C-mm2/W). The approximate
exposed heat slug size is as follows:
• DRV8432, 36-pin PSOP3 …… 0.124 in2 (80mm2)
The thermal resistance of thermal pads is considered higher than a thin thermal grease layer and is not
recommended. Thermal tape has an even higher thermal resistance and should not be used at all. Heat sink
thermal resistance is predicted by the heat sink vendor, modeled using a continuous flow dynamics (CFD)
model, or measured.
Thus the system RθJA = RθJC + thermal grease resistance + heat sink resistance.
See the TI application report, IC Package Thermal Metrics (SPRA953), for more thermal information.
4.3.1 DRV8412 Thermal Via Design Recommendation
Thermal pad of the DRV8412 is attached at bottom of device to improve the thermal capability of the device. The
thermal pad has to be soldered with a very good coverage on PCB to deliver the power specified in the data
sheet. Figure 7-16 shows the recommended thermal via and land pattern design for the DRV8412. For additional
information, see TI application report, PowerPad™ Made Easy (SLMA004) and PowerPad Layout Guidelines
(SOLA120).

Figure 7-16. DRV8412 Thermal Via Footprint

28 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: DRV8412 DRV8432

 DRV8412, DRV8432
www.ti.com SLES242H – DECEMBER 2009 – REVISED JULY 2024

7 Device and Documentation Support

7.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
7.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
7.3 Trademarks
PowerPad™ and TI E2E™ are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
7.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

7.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

8 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (July 2014) to Revision H (July 2024) Page
• Changed the Device Information table to the Package Information table.......................................................... 1
• Deleted values in 39 to 200 in Table 6-2 ......................................................................................................... 12

Changes from Revision F (January 2014) to Revision G (July 2014) Page

• Added ESD Ratingstable, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................. 1

Changes from Revision E (October 2013) to Revision F (January 2014) Page

• Changed GND_A, GND_B, GND_C, and GND_D pins description to remove text "requires close decoupling
capacitor to ground"............................................................................................................................................3
• Changed the tON_MIN description to include "for charging the Bootstrap capacitor"........................................... 5
• Added text to the Overcurrent (OC) Protection section - "It is important to note..." .........................................12

Changes from Revision D (July 2011) to Revision E (October 2013) Page

• Added last sentence in description of Thermal Pad in Pin Functions table........................................................3
• Added THERMAL INFORMATION table............................................................................................................ 6

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 29

Product Folder Links: DRV8412 DRV8432
DRV8412, DRV8432
SLES242H – DECEMBER 2009 – REVISED JULY 2024 www.ti.com

• Added a new paragraph in DIFFERENT OPERATIONAL MODES section: In operation modes.....DC logic
level.................................................................................................................................................................. 14

Changes from Revision C (May 2010) to Revision D (July 2011) Page

• Changed from 80mΩ to 110mΩ in first Feature..................................................................................................1
• Changed from 50V to 52V in second Feature.................................................................................................... 1
• Deleted (70V Absolute Maximum) from second Feature....................................................................................1
• Added LED Lighting Drivers to Applications.......................................................................................................1
• Added Includes metallization bond wire and pin resistance to RDS(on) test conditions.......................................7
• Changed RDS(on) typ from 80 mΩ to 110 mΩ......................................................................................................7
• Added text to 5th paragraph of Overcurrent (OC) Protection section...............................................................12
• Deleted Output Inductor Selection section and moved information into Overcurrent (OC) Protection section.12
• Changed Figure 7-1 .........................................................................................................................................16
• Changed Figure 7-9 .........................................................................................................................................20
• Deleted Application Diagram Example for Three Phase PMSM PVDD Sense Operation and Application
Diagram Example for Three Phase PMSM GND Sense Operation figures......................................................21
• Added Figure 7-11 ........................................................................................................................................... 21
• Changed Figure 7-13 .......................................................................................................................................24

Changes from Revision B (Jan 2010) to Revision C () Page

• Deleted all DRV8422 related descriptions from this data sheet......................................................................... 1
• Changed the DRV8432 pinout............................................................................................................................3
• Added Thermal Pad and Heat slug rows to end of Pin Functions table. Also added T=thermal in note............ 3
• Added second paragraph to Bootstrap Capacitor....section..............................................................................11
• Deleted or GVDD undervoltage from DEVICE RESET section second paragraph..........................................13

Changes from Revision A (December 2009) to Revision B () Page

• Added TA = 125°C power rating of 1.0 W to package power deratings table.....................................................6

9 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

30 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: DRV8412 DRV8432

 PACKAGE OPTION ADDENDUM

www.ti.com 14-May-2025

PACKAGING INFORMATION

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

DRV8412DDW Obsolete Production HTSSOP (DDW) | 44 - - Call TI Call TI -40 to 85 DRV8412

DRV8412DDWR Active Production HTSSOP (DDW) | 44 2000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 DRV8412
DRV8412DDWR.Z Active Production HTSSOP (DDW) | 44 2000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 DRV8412
DRV8412DDWRG4.Z Active Production HTSSOP (DDW) | 44 2000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 DRV8412

(1)
Status: For more details on status, see our product life cycle.

(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without
limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available
for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the
finish value exceeds the maximum column width.

(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per
JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the
previous line and the two combined represent the entire part marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 21-Mar-2025

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRV8412DDWR HTSSOP DDW 44 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 21-Mar-2025

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DRV8412DDWR HTSSOP DDW 44 2000 350.0 350.0 43.0

Pack Materials-Page 2
 GENERIC PACKAGE VIEW
DDW 44 PowerPAD TSSOP - 1.2 mm max height
6.1 x 14, 0.635 mm pitch PLASTIC SMALL OUTLINE

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4224876/A

www.ti.com
 PACKAGE OUTLINE
DDW0044B SCALE 1.250
PowerPAD TM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE

8.3
TYP
7.9
A PIN 1 ID
AREA 42X 0.635
44
1

14.1
13.9 2X
NOTE 3
13.335

22
23 0.27
6.2 44X
B 0.17 0.1 C
6.0 0.08 C A B
SEATING PLANE
C
(0.15) TYP

SEE DETAIL A 4.31

3.45
22 23

EXPOSED
THERMAL PAD

8.26 0.25
7.40 45 GAGE PLANE 1.2 MAX

0.75 0.15
0 -8 0.50 0.05
2X (0.6)
2X (0.45) MAX DETAIL A
NOTE 5
NOTE 5 TYPICAL
1 44

4218832/A 03/2019

NOTES: PowerPAD is a trademark of Texas Instruments.

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Features may differ or may not be present.

www.ti.com
 EXAMPLE BOARD LAYOUT
DDW0044B PowerPAD TM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE

(5.2)
NOTE 9 SOLDER MASK
(4.31) DEFINED PAD
44X (1.45) SYMM SEE DETAILS

1
44

44X (0.4)

42X (0.635) (14)

NOTE 9

SYMM 45 (1.1) TYP

(8.26)

(R0.05) TYP

( 0.2) TYP
VIA

22 23

METAL COVERED
BY SOLDER MASK (1.15)
TYP
(7.5)

LAND PATTERN EXAMPLE

SCALE:6X

SOLDER MASK METAL UNDER

SOLDER MASK METAL
OPENING SOLDER MASK
OPENING

0.05 MAX 0.05 MIN

AROUND AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

NOT TO SCALE
4218832/A 03/2019
NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
7. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
8. Size of metal pad may vary due to creepage requirement.

www.ti.com
 EXAMPLE STENCIL DESIGN
DDW0044B PowerPAD TM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE

(4.31)
BASED ON
44X (1.45) 0.125 THICK
STENCIL
1
44

44X (0.4)

42X (0.635)

SYMM 45 (8.26)
BASED ON
0.125 THICK
STENCIL

SEE TABLE FOR

DIFFERENT OPENINGS
22 23 FOR OTHER STENCIL
THICKNESSES
METAL COVERED SYMM
BY SOLDER MASK

(7.5)

SOLDER PASTE EXAMPLE

PAD 45:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:6X

STENCIL SOLDER STENCIL

THICKNESS OPENING
0.1 4.82 X 9.23
0.125 4.31 X 8.26 (SHOWN)
0.15 3.93 X 7.54
0.175 3.64 X 6.98

4218832/A 03/2019

NOTES: (continued)

9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
10. Board assembly site may have different recommendations for stencil design.

www.ti.com
 IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2025, Texas Instruments Incorporated