What is DMA?

• Direct Memory Access (DMA) allows data to transfer between an external device and main
memory without constant CPU involvement.

• Used for fast, large data transfers, freeing up the CPU to perform other tasks.

DMA Operation (Step-by-Step)

1. Processor Initiates:

o Processor sets up DMA by writing to the DMA controller’s registers (starting address,
word count, etc.).

2. DMA Controller Manages Transfer:

o The DMA controller takes control and moves data between memory and the device.

o It automatically increments the memory address for each word transferred.

3. CPU Free to Work:

o While the DMA is active, the CPU can perform other operations, increasing
efficiency.

4. DMA Completion:

o When the data transfer is complete, the DMA controller sends an interrupt to notify
the CPU.

DMA Controller Registers

1. Starting Address Register: Stores the memory address for where the transfer begins.

2. Word Count Register: Tracks how many words (or bytes) need to be transferred.

3. Status and Control Register:

o R/W Bit: Determines transfer direction (read/write).

o Done Flag: Signals when transfer is complete.

o Interrupt Enable (IE) Flag: Enables an interrupt when the transfer finishes.

o IRQ Bit: Indicates interrupt request.

• Exceptions are events that interrupt the normal execution of a program.

• They can be caused by errors, debugging, or system protection rules.

• The processor handles exceptions by executing an exception-service routine.

Types of Exceptions:

1. I/O Interrupts:

o Occur during input/output operations when a device needs the CPU’s attention.

2. Error Exceptions:

o Hardware Errors: Triggered by errors like memory corruption or hardware failure.

o Software Errors: Caused by issues such as illegal instructions or division by zero.

3. Debugging Exceptions:

o Trace Exception: Happens after every instruction when debugging to monitor

o Breakpoint Exception: Occurs at specific points set by the programmer to pause and
examine the program.

4. Privilege Exceptions:

o Triggered when a user program tries to execute restricted (privileged) instructions.

o Protects the system by switching to supervisor mode to handle the exception.

• A signal that pauses the current program to handle an urgent task.

• The processor stops its task, executes the Interrupt Service Routine (ISR), and then resumes
its original task.

Interrupt Service Routine (ISR):

• A special function that runs when an interrupt occurs.

• Performs necessary actions (like reading data or handling errors).

• Control is returned to the main program after the ISR finishes.

Interrupt Enabling:

• Allows the CPU to respond to interrupt signals during program execution.

• Ensures that external devices or internal events can notify the CPU.

• After handling the interrupt, the CPU resumes the original task.

Interrupt Disabling:

• Temporarily prevents the CPU from responding to interrupts.

• Used during critical sections of code to avoid conflicts or errors.

• Once the critical task is complete, interrupts are re-enabled to allow normal processing.

Vectored Interrupts:

• Device Identification: The device identifies itself to the processor.

• Special Code: Sends a special code to the processor over the bus.

• Single Interrupt Line: Multiple devices can share one interrupt line and still be recognized.

• ISR Address: The code may indicate the starting address of its interrupt service routine (ISR).

• Code Length: Typically 4 to 8 bits long.

• Processor's Role: The processor adds the remaining address from its memory area for ISRs.

Interrupt Nesting:

• Execution Continuity: Once an ISR starts, it runs to completion before accepting another
interrupt.

• Preventing Delays: Avoids long delays that could lead to errors.

o Example: Important for accurate timekeeping by a real-time clock.

• Priority Structure: Devices are organized by priority levels.

o High-Priority Handling: High-priority interrupts can interrupt lower-priority tasks.

Accessing I/O devices involves connecting them to the processor and memory via a bus

# Bus Structure - *Bus Components:* - *Address Lines:* Identify the I/O device.

- *Data Lines:* Transfer data to/from the device. - *Control Lines:* Manage the operations.

Steps to Access I/O Devices:

• Step 1: The CPU puts the address of the I/O device on the address lines.

• Step 2: The specific device that recognizes that address will respond.

• Step 3: The CPU sends a command through the control lines to either read data from or
write data to the device.

• Step 4: The actual data is transferred through the data lines.

Example:

• Imagine you want to print a document:

1. The CPU puts the printer's address on the address lines.

2. The printer sees its address and knows it's being called.

3. The CPU sends a command to the printer to start printing.

4. The document data is sent over the data lines to the printer.
Isolated I/O:

• Separate Control Lines: Has distinct read/write control lines for I/O operations, in addition to
those for memory.

• Separate Address Spaces: I/O devices and memory have different address spaces, meaning
they use different ranges of addresses.

• Distinct Instructions: Uses specific input and output instructions (e.g., IN and OUT) for I/O
operations.

Memory-Mapped I/O:

• Single Control Lines: Uses a single set of read/write control lines for both memory and I/O
operations, meaning no distinction between them.

• Shared Address Space: Memory and I/O devices share the same address space, which can
reduce the available memory address range.

• No Special Instructions: The same instructions used for memory access (like MOV) are also
used for I/O transfers.

Key Points of Memory-Mapped I/O:

• Flexibility: Provides considerable flexibility in handling I/O operations since any machine
instruction that accesses memory can also access I/O devices.

• Example:

o If DATAIN is the address of the keyboard input buffer, the instruction Move DATAIN,
R0 reads data from the keyboard and stores it in register R0.

o The instruction Move R0, DATAOUT sends data from register R0 to DATAOUT, which
could be a display unit or printer's output buffer.

Comparison Summary:

• Isolated I/O:

o Uses separate control lines and addresses for I/O.

o Requires distinct instructions for I/O operations.

• Memory-Mapped I/O:

o Uses shared control lines and addresses.

o Allows the same instructions for both memory and I/O operations.