ADVANCED INTEGRATED CIRCUITS - BUILT ON SUN JUN 8 16:43:19 UTC 2025 FROM A53266D730C2B7FE4FD6BA90E9C2B3586E43F3E2 1

Switched-Capacitor Circuits
Carsten Wulff, carsten@wulff.no

Keywords: SC DAC, SC FUND, DT, Alias, Subsample, Z We cannot physically change an IC, every single one of the 100
Domain, FIR, IIR, SC MDAC, SC INT, Switch, Non-Overlap, million copies of an IC is from the same Mask set. That’s why
VBE SC, Nyquist ICs are cheap. To make the Mask set is incredibility expensive
(think 5 million dollars), but a copy made from the Mask set
I. ACTIVE -RC can cost one dollar or less. To calibrate we need additional
circuits.
A general purpose Active-RC bi-quadratic (two-quadratic
equations) filter is shown below
Imagine we need a resistor of 1 kOhm. We could create that
Gy by parallel connection of larger resistors, or series connection
G Gs
of smaller resistors. Since we know the maximum variation is
or 0.02, then we need to be able to calibrate away +- 20 Ohms.
Ca
L
CB We could have a 980 kOhm resistor, and then add ten 4 Ohm
resistors in series that we can short with a transistor switch.
Vi G
63
Vo
But is a resolution of 4 Ohms accurate enough? What if we need
a precision of 0.1%? Then we would need to tune the resistor
within +-1 Ohm, so we might need 80 0.5 Ohm resistors.

If you want to spend a bit of time, then try and calculate the
transfer function below. But how large is the on-resistance of the transistor switch?
Would that also affect our precision?
h i
C1 2 G2
CB s + + ( CGA1 C
CB s
G3
B
)
H(s) = h i
2 G5 G3 G4
s + CB s + CA CB But is the calibration step linear with addition of the transistors?
If we have a non-linear calibration step, then we cannot use
gradient decent calibration algorithms, nor can we use binary
Active resistor capacitor filters are made with OTAs (high
search.
output impedance) or OPAMP (low output impedance). Active
amplifiers will consume current, and in Active-RC the ampli-
fiers are always on, so there is no opportunity to reduce the
Analog designers need to deal with an almost infinite series of
current consumption by duty-cycling (turning on and off).
“But”.
Both resistors and capacitors vary on an integrated circuit, and
the 3-sigma variation can easily be 20 %.
The experienced designer will know when to stop, when is the
The pole or zero frequency of an Active-RC filter is proportional
“But what if” not a problem anymore.
to the inverse of the product between R and C

G 1 The most common error in analog integrated circuit design is

ωp|z ∝ =
C RC a “I did not imagine that my circuit could fail in this manner”
type of problem. Or, not following the line of “But”’s far
As a result, the total variation of the pole or zero frequency is enough.
can have a 3-sigma value of

q p But if we follow all the “But”’s we will never tapeout!

σRC = 2 + σ2 =
σR 0.022 + 0.022 = 0.028 = 28 %
C

On an IC we sometimes need to calibrate the R or C in Active-RC filters are great for linearity, but if we need accurate
production to get an accurate RC time constant. time constant, there are better alternatives.
 63
Vo

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II. G M -C For SC circuits, we need to consider the charge on the

capacitors, and how they change with time.
1
The charge on the capacitor at the end of phase 2 is

Gmt Gul Gms Vout

ca c
Qϕ2$ = C1 VGN D = 0

20
while at the end of phase 1
Guy Gms
Vin
Qϕ1$ = C1 VI
20

The impedance, from Ohm’s law is

h i
s2 CXC+C
X
B
+ s Gm5
CX +CB + Gm2 Gm4
CA (CX +CB )
H(s) = h i
G G m1 Gm2
s2 + s CX +C
m2
B
+ CA (CX +CB )
ZI = (VI − VGN D )/II

The pole and zero frequency of a Gm-C filter is

And from SI units units we can see current is
Gm
ωp|z ∝
C
Q
The transconductance accuracy depends on the circuit, and the II = = Qfϕ
dt
bias circuit, so we can’t give a general, applies for all circuits,
sigma number. Capacitors do have 3-sigma 20 % variation,
usually. Charge cannot disappear, charge is conserved. As such, the
charge going out from the input must be equal to the difference
Same as Active-RC, Gm-C need calibration to get accurate
of charge at the end of phase 1 and phase 2.
pole or zero frequency.

III. S WITCHED CAPACITOR

VI − VGN D
The first time you encounter Switched Capacitor (SC) circuits, ZI =

Qϕ1$ − Qϕ2$ fϕ
they do require some brain training. So let’s start simple.
Consider the circuit below. Assume that the two transistors are
ideal (no-charge injection, no resistance). Inserting for the charges, we can see that the impedance is

Vi ZI =
VI
=
1
(VI C − 0) fϕ C1 fϕ
zi 0
A common confusion with SC circuits is to confuse the
impedance of a capacitor Z = 1/sC with the impedance
of a SC circuit Z = 1/f C. The impedance of a capacitor is
complex (varies with frequency and time), while the SC circuit

C impedance is real (a resistance).

Q The main difference between the two is that the impedance

of a capacitor is continuous in time, while the SC circuit is a
Vgud discrete time circuit, and has a discrete time impedance.

The circuit below is drawn slightly differently, but the same

equation applies.

1I use the $ to mark the end of the period. It comes from Regular Expressions.
 zi 0
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Qϕ2$ = C1 VO

C
Q
Inserted into the impedance we get the same result.

Vgud V0 ZI =
VI − VO
=
1
(C1 VI − C1 VO )) fϕ
Vi
C1 fϕ

The first time I saw the circuit above it was not obvious to
zi C me that the impedance still was Z = 1/Cf . It’s one of the
cases where mathematics is a useful tool. I could follow a
set of rules (charge conservation), and as long as I did the
mathematics right, then from the equations, I could see how it
worked.

9
If we compute the impedance. a A. An example SC circuit
An example use of an SC circuit is
VI − VO
ZI = A pipelined 5-Msample/s 9-bit analog-to-digital converter
Vo


Qϕ1$ − Qϕ2$ fϕ
Vi Shown in the figure below. You should think of the switched
capacitor circuit as similar to a an amplifier with constant
Zi C
Qϕ1$ = C1 (VI − VO )
gain. We can use two resistors and an opamp to create a gain.

V
Imagine we create a circuit without the switches, and with
a resistor0of R from input to virtual ground, and 4R in the
Qϕ2$ = 0
Vi
feedback. Our Active-R would have a gain of A = 4.
The switches disconnect the OTA and capacitors for half the
VI − VO 1 time, but for the other half, at least for the latter parts of ϕ2
zi ZI =
(C1 (VI − VO )) fϕ
=
C 1 fϕ C the gain is four.

Which should not be surprising, as all I’ve done is to rotate

the circuit and call VGN D = V0 .
Let’s try the circuit below.

9 a

Vi Vo
Zi C

The output is only correct for a finite, but periodic, time interval.
The circuit is discrete time. As long as all circuits afterwards
also have a discrete-time input, then it’s fine. An ADC can
VI − VO sample the output from the amplifier at the right time, and
ZI =

Qϕ1$ − Qϕ2$ fϕ never notice that the output is shorted to a DC voltage in ϕ1
We charge the capacitor 4C to the differential input voltage in
Qϕ1$ = C1 VI ) ϕ1
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IV. D ISCRETE -T IME S IGNALS

Q1 = 4CVin An random, Gaussian, continuous time, continuous value, signal
has infinite information. The frequency can be anywhere from
zero to infinity, the value have infinite levels, and the time
Then we turn off ϕ1 , which opens all switches. The charge on
division is infinitely small. We cannot store such a signal. We
4C will still be Q1 (except for higher order effects like charge
have to quantize.
injection from switches).
If we quantize time to T = 1 ns, such that we only record the
After a short time (non-overlap), we turn on ϕ2 , closing some value of the signal every 1 ns, what happens to all the other
of the switches. The OTA will start to force its two inputs to information? The stuff that changes at 0.5 ns or 0.1 ns, or 1
be the same voltage, and we short the left side of 4C. After ns.
some time we would have the same voltage on the left side
of 4C for the two capacitors, and another voltage on the right We can always guess, but it helps to know, as in absolutely
side of the 4C capacitors. The two capacitors must now have know, what happens. That’s where mathematics come in. With
the same charge, so the difference in charge, or differential mathematics we can prove things, and know we’re correct.
charge must be zero.
Physics tell us that charge is conserved, so our differential A. The mathematics
charge Q1 cannot vanish into thin air. The difference in Define
electrons that made Q1 must be somewhere in our circuit. xc
Assume the designer of the circuit has done a proper job, then as a continuous time, continuous value signal
the Q1 charge will be found on the feedback capacitors.
Define (
We now have a Q1 charge on smaller capacitors, so the 1 if t ≥ 0
ℓ(t) =
differential output voltage must be 0 if t < 0

Define
Q1 = 4CVin = Q2 = CVout
xc (nT )
xsn (t) = [ℓ(t − nT ) − ℓ(t − nT − τ )]
τ
The gain is
where xsn (t) is a function of the continuous time signal at the
time interval nT .
Vout
A= =4 Define
Vin ∞
X
xs (t) = xsn (t)
Why would we go to all this trouble to get a gain of 4? n=−∞

In general, we can sum up with the following equation. where xs (t) is the sampled, continuous time, signal.
Think of a sampled version of an analog signal as an infinite
C1 sum of pulse trains where the area under the pulse train is
ωp|z ∝
C2 equal to the analog signal.
Why do this?
We can use these “switched capacitor resistors” to get pole or
zero frequency or gain proportional to a the relative size of With a exact definition of a sampled signal in the time-domain
capacitors, which is a fantastic feature. Assume we make two it’s sometimes possible to find the Laplace transform, and see
identical capacitors in our layout. We won’t know the absolute how the frequency spectrum looks.
size of the capacitors on the integrated circuit, whether the C1 If
is 100 fF or 80 fF, but we can be certain that if C1 = 80 fF, ∞
X
then C2 = 80 fF to a precision of around 0.1 %. xs (t) = xsn (t)
n=−∞
With switched capacitor amplifiers we can set an accurate gain,
and we can set an accurate pole and zero frequency (as long Then
as we have an accurate clock and a high DC gain OTA). 1 1 − e−sτ
Xsn (s) = xc (nT )e−snT
τ s
The switched capacitor circuits do have a drawback. They are
discrete time circuits. As such, we must treat them with caution, And
∞
and they will always need some analog filter before to avoid a 1 1 − e−sτ X
Xs (s) = xc (nT )e−snT
phenomena we call aliasing. τ s n=−∞
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Thus ∞
#- "sinusoidal signals and some noise
X f1 = 233/N
−snT
lim → Xs (s) = xc (nT )e fd = 1/N*119
τ →0 x_s = np.sin(2*np.pi*f1*t) + 1/1024*np.random.randn(N) + \
n=−∞
0.5*np.sin(2*np.pi*(f1-fd)*t) + 0.5*np.sin(2*np.pi*(f1+fd)*t)

Or ∞   #- Create the sampling vector, and the sampled signal

1 X jk2π t_s_unit = [1,1,0,0,0,0,0,0]
Xs (jω) = Xc jω − t_s = np.tile(t_s_unit,int(N/len(t_s_unit)))
T T x_sn = x_s*t_s
k=−∞
#- Convert to frequency domain with a hanning window to avoid FFT bin
#- energy spread
The spectrum of a sampled signal is an infinite sum of Hann = True
frequency shifted spectra if(Hann):
w = np.hanning(N+1)
or equivalently else:
w = np.ones(N+1)
X_s = np.fft.fftshift(np.fft.fft(np.multiply(w[0:N],x_s)))
When you sample a signal, then there will be copies of the X_sn = np.fft.fftshift(np.fft.fft(np.multiply(w[0:N],x_sn)))
input spectrum at every
Try to play with the code, and see if you can understand what
nfs it does.
However, if you do an FFT of a sampled signal, then all those Below are the plots. On the left side is the “continuous value,
infinite spectra will fold down between continuous time” emulation, on the right side “discrete time,
continuous value”.
0 → fs1 /2
The top plots are the time domain, while the bottom plots is
or
frequency domain.
−fs1 /2 → fs1 /2
The FFT is complex, so that’s why there are six sinusoids
for a complex FFT
bottom left. The “0 Hz” would be at x-axis index 4096 (213 /2).

B. Python discrete time example The spectral copies can be seen bottom right. How many
spectral copies, and the distance between them will depend
If your signal processing skills are a bit thin, now might be
on the sample rate (length of t_s_unit). Try to play around
a good time to read up on FFT, Laplace transform and But
with the code and see what happens.
what is the Fourier Transform?
2.0 2.0
In python we can create a demo and see what happens when we 1.5 1.5
“sample” an “continuous time” signal. Hopefully it’s obvious 1.0 1.0
0.5 0.5
Time Domain

that it’s impossible to emulate a “continuous time” signal on a 0.0 0.0

digital computer. After all, it’s digital (ones and zeros), and it 0.5 0.5
1.0 1.0
has a clock!
1.5 1.5
2.0 2.0
We can, however, emulate to any precision we want. 0 2000 4000 6000 8000 0 2000 4000 6000 8000
60
The code below has four main sections. First is the time vector. 60
40
I use Numpy, which has a bunch of useful features for creating 40
20
Frequency Domain

20
ranges, and arrays. 0
0
20
Secondly, I create continuous time signal. The time vector can 20
40
40
be used in numpy functions, like np.sin(), and I combine 60
60
three sinusoid plus some noise. The sampling vector is a 80
0 2000 4000 6000 8000 0 2000 4000 6000 8000
repeating pattern of 11001100, so our sample rate should be Continuous time, continuous value Discrete time, continuous value

1/2’th of the input sample rate. FFT’s can be unwieldy beasts.

I like to use coherent sampling, however, with multiple signals
and samplerates I did not bother to figure out whether it was
possible. C. Aliasing, bandwidth and sample rate theory
The alternative to coherent sampling is to apply a window I want you to internalize that the spectral copies are real. They
function before the FFT, that’s the reason for the Hanning are not some “mathematical construct” that we don’t have to
window below. deal with.

dt.py They are what happens when we sample a signal into discrete
#- Create a time vector
time. Imagine a signal with a band of interest as shown below
N = 2**13 in Green. We sample at fs . The pink and red unwanted signals
t = np.linspace(0,N,N)
do not disappear after sampling, even though they are above
#- Create the "continuous time" signal with multiple the Nyquist frequency (fs /2). They fold around fs /2, and in
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As such x t should be band limited before
sampling
may appear in-band. That’s why it’s important to band limit
Before Sampling
analog signals before they are sampled.

Before Saulius AEs p th I I

th Is
M a app ask o

As such
sampling
P T
Es th
N
x t should be band limited before

th
it it
f ask o
A
After sampling

o 1 I p p 1 I f
After sampling Es th

NIii
Before Saulius th f

8 I
P Es T
i f
th itth itIs D. Z-transform
Es th th f ask o Someone got the idea that writing

After sampling

Iii
∞
X
Before Sampling Xs (s) = xc (nT )e−snT
Anti Alias
With an anti-alias filter (yellow) we ensure that the unwanted n=−∞
components
8 I i
are low enough before sampling.
f
As a result, our
wantedEs
th th Is
signal (green) is undisturbed. was cumbersome, and wanted to find something better.
ot I o LP o SH o
Es th it th
∞
f Xs (z) =
X
xc [n]z −n
Before Sampling n=−∞
After sampling Anti Alias
For discrete time signal processing we use Z-transform

8ot I1 I f
o LP o SH o
If you’re unfamiliar with the Z-transform, read the book or
Es th
Es th it thth f f search https://en.wikipedia.org/wiki/Z-transform
The nice thing with the Z-transform is that the exponent of
After sampling the z tell’s you how much delayed the sample xc [n] is. A
block that delays a signal by 1 sample could be described as
xc [n]z −1 , and an accumulator
8 1 I f
Es th th f y[n] = y[n − 1] + x[n]

in the Z domain would be

Assume that we we’re interested in the red signal. We could
still use a sample rate of fs . If we bandpass-filtered all but the Y (z) = z −1 Y (z) + X(z)
red signal the red signal would fold on sampling, as shown in
the figure below. With a Z-domain transfer function of

Remember that the Nyquist-Shannon states that a sufficient Y (z) 1

=
no-loss condition is to sample signals with a sample rate of X(z) 1 − z −1
twice the bandwidth of the signal.
E. Pole-Zero plots
Nyquist-Shannon has been extended for sparse signals, com- If you’re not comfortable with pole/zero plots, have a look at
pressed sensing, and non-uniform sampling to demonstrate
What does the Laplace Transform really tell us
that it’s sufficient for the average sample rate to be twice
the bandwidth. One 2009 paper Blind Multiband Signal Think about the pole/zero plot as a surface your looking down
Reconstruction: Compressed Sensing for Analog Signal is onto. At a = 0 we have the steady state fourier transform. The
a good place to start to delve into the latest on signal “x” shows the complex frequency where the fourier transform
reconstruction. goes to infinity.
 Discrete time
ADVANCED INTEGRATED CIRCUITS - BUILT ON SUN JUN 8 16:43:19 UTC 2025 FROM A53266D730C2B7FE4FD6BA90E9C2B3586E43F3E2 7

Any real circuit will have complex conjugate, or real,

poles/zeros. A combination of two real circuits where one
path is shifted 90 degrees in phase can have non-conjugate Z plane
b
jw
complex poles/zeros.

If the “x” is a < 0, then any perturbation will eventually die Zsa
out. If the “x” is on the a = 0 line, then we have a oscillator g
that will ring forever. If the “x” is a > 0 then the oscillation
x
amplitude will grow without bounds, although, only in Matlab.
In any physical circuit an oscillation cannot grow without x
bounds forever.

Growing without bounds is the same as “being unstable”.

jw s atjw
G. First order filter

a Assume a first order filter given by the discrete time equation.

X

y[n + 1] = bx[n] + ay[n] ⇒ Y z = bX + aY

The “n” index and the “z” exponent can be chosen freely,
poles 440
which sometimes can help the algebra.

O
F.0 Z-domain
Leros ifs y[n] = bx[n − 1] + ay[n − 1] ⇒ Y = bXz −1 + aY z −1
Spectra repeat every

Discrete time 2π The transfer function can be computed as

spectra b
Z plane
As such, it does not make sense to talk about a plane with a
at
H(z) =
a and a jω. Rather web use the complex number z = a + jb. every z−a
jw
As long as the poles (“x”) are within the unitZsa
circle, oscillations From the discrete time equation we can see that the impulse will
g
will die out. If the poles are on the unit-circle, then we have never die out. We’re adding the previous output to the current
an oscillator. Outside the unit circle the oscillation will grow
x words, be unstable.
without bounds, or in other
input. That means the circuit has infinite memory. Accordingly,
filters of this type are known as. Infinite-impulse response (IIR)
x
We can translate between Laplace-domain and Z-domain with
the Bi-linear transform (
k if n < 1
h[n] =
an−1 b + an k if n ≥ 1
g z−1
s=
z+1 Head’s up: Fig 13.12 in AIC is wrong

From the impulse response it can be seen that if a > 1, then

Warning: First-order approximation https://en.wikipedia.org/w the filter is unstable. Same if b > 1. As long as |a + jb| < 1
iki/Bilinear_transform the filter should be stable.
ADVANCED INTEGRATED CIRCUITS - BUILT ON SUN JUN 8 16:43:19 UTC 2025 FROM A53266D730C2B7FE4FD6BA90E9C2B3586E43F3E2 8

FIRFirst order
H. Finite-impulse response(FIR)

Hz Ia
FIR filters are unconditionally stable, since the impulse
stable response will always die out. FIR filters are a linear sum
unstable
Fitt impulse
of delayed inputs.

akestan repose
In my humble opinion, there is nothing wrong with an IIR.

66 ha
Yes, the could become unstable, however, they can be designed
safely. I’m not sure there is a theological feud on IIR vs FIR,

It t
I suspect there could be. Talk to someone that knows digital
filters better than me.
a
H gylate
t E
But be wary of rules like “IIR are always better than FIR”

xD z
or visa versa. Especially if statements are written in books.
Remember that the book was probably written a decade ago,

Aza Staltaya
and based on papers two decades old, which were based on
three decades old state of the art. Our abilities to use computers
for design has improved a bit the last three decades.
yEnt1
2
1 X −1
H(z) = z
3 i=0
FIR
The first order filter can be implemented in python, and it’s
really not hard. See below. The xs n vector is from the previous
python example.
112

Fitt
There are smarter, and faster ways to repose impulse
do IIR filters (and FIR) XE
Infinite inputs

4
in python, see scipy.signal.iirfilter
response
Iya
e
From the plot below we can see the sampled time domain and
spectra on the left, and the filtered time domain and spectra
H t Ea
E
on the right. z Hee
iir.py
43
1.00
0.75
0.50
1.00
0.75
0.50
hlultakestan V. S WITCHED -C APACITOR
0.25 0.25
Time Domain

0.00 0.00 Below is an example of a switched-capacitor circuit during

0.25
XE 0.25 phase 1. Think of the two phases as two different configurations

4
0.50 0.50

Iya
0.75 0.75
of a circuit, each with a specific purpose.
1.00 1.00
1000 1050 1100 1150 1200 1250 1300 1350 1400 1000 1050 1100 1150 1200 1250 1300 1350 1400

40 43 60
40

Cz
20 20
Frequency Domain

0 0
20
t
it
20
40
40

q
60
60 80
0 2000 4000 6000 8000 0 2000 4000 6000 8000
Sampled IIR Filter

#- IIR filter
t c
b = 0.3
a = 0.25
z = a + 1j*b
z_abs = np.abs(z)
print("|z| = " + str(z_abs))
y = np.zeros(N)
y[0] = a

Q
for i in range(1,N):
y[i] = b*x_sn[i-1] + y[i-1] This is the SC circuit during the sampling phase. Imagine that
we somehow have stored a voltage V1 = ℓ on capacitor C1
The IIR filter we implemented above is a low-pass filter, and (the switches for that sampling or storing are not shown). The
the filter partially rejects the copied spectra, as expected. charge on C1 is
Qz
 ADVANCED INTEGRATED CIRCUITS - BUILT ON SUN JUN 8 16:43:19 UTC 2025 FROM A53266D730C2B7FE4FD6BA90E9C2B3586E43F3E2 9

a
thus
Q1ϕ1 $ = C1 V1
V2 C1
=
The C2 capacitor is shorted, as such, V2 = 0, which must V1 C2
mean that the charge on C2 given by

on
A. Switched capacitor gain circuit
ispreviousVicircuit,

if
Vocut
Q2ϕ1 $ = 0 a
Redrawing the
Cg
n and adding a few more switches

H
we can create a switched capacitor gain circuit.
ur
HE
g
The voltage at the negative input of the OTA must be 0 V, as There is now a switch to sample the inputavoltage across C1
Vo
the positive input is 0 V, and we assume the circuit has settled
all transients.
Evi
during phaseZ1 and reset C2 . During phase 2 we configure the
circuit to leverage the OTA to do the charge transfer from C1
Imagine we (very carefully) open the circuit around C2 and to C2 .
close the circuit from the negative side of C1 to the OTA
negative input, as shown below.

Cz
a
Cz
Vien
t
VoEu
Ve un

G
cutis
Vo Vi n
Cg
H The discrete time output from the circuit will be as shown
below. It’s only at the end of the second phase that the output
VoZ
QEvi
HE
ga
It’s the OTA that ensures that the negative input is the same as
signal is valid. As a result, it’s common to use the sampling
phase of the next circuit close to the end of phase 2.
the positive input, but the OTA cannot be infinitely fast. At the For charge to be conserved the clocks for the switch phases
same time, the voltage across C1 cannot change instantaneously. must never be high at the same time.
Qz
Neither can the voltage across C2 . As such, the voltage at the
negative input must immediately go to −V1 (ignoring any
parasitic capacitance at the negative input).
The OTA does not like it’s inputs to be different, so it will
Cz
start to charge C2 to increase the voltage at the negative input
to the OTA. When the negative input reaches 0 V the OTA is
happy again. At that point the charge on C1 is
Vien viii
Q1ϕ2 $ = 0
VoEu
A key point is, that even the voltages now have changed, there
is zero volt across C1 , and thus there cannot be any charge
across C1 the charge that was there cannot have disappeared.
E The negative input of the OTA E is a high impedance node, and
cannot supply charge. The charge must have gone somewhere,
but where?
In process of changing the voltage at the negative input of the
A the voltage across C2 .BThe voltage change
B changed
OTA we’ve
error
must exactly match the charge that was across C1 , as such
The discrete time, Z-domain and transfer function is shown
below. The transfer function tells us that the circuit is equivalent
Q2ϕ2 $ = Q1ϕ1 $ = C1 V1 = C2 V2 to a gain, and a delay of one clock cycle. The cool thing about
c
c

A B
C
 ADVANCED INTEGRATED CIRCUITS - BUILT ON SUN JUN 8 16:43:19 UTC 2025 FROM A53266D730C2B7FE4FD6BA90E9C2B3586E43F3E2 10

switch capacitor circuits is that the precision of the gain is set by

C Cz
the relative size between two capacitors. In most technologies
that relative sizing can be better than 0.1 %.
Vos
Cz
Gain circuits like the one above find use in most Pipelined
ADCs, and are common, with some modifications, in Sigma-
Delta ADCs.

Vith

Nt
a
VoEu
G Vo [n + 1] =
C1
Vi [n]
C2 N
no

C1
arrow
Vo z = Vi
C2 Make sure you read and understand the equations below, it’s
good to realize that discrete time equations, Z-domain and
transfer functions in the Z-domain are actually easy.

C1
Vo [n] = Vo [n − 1] + Vi [n − 1]
VoEn VoEn I C Vicu
r
Et
C2
Vo 1 −1
= H(z) = z
Vi C2
C1 −1
Vo − z −1 Vo = z Vi
ElVo
É zaVi
C2
Vo
Maybe one confusing thing is that multiple transfer functions
HCA E EEE E
B. Switched capacitor integrator can mean the same thing, as below.

Removing one switch we can change the function of the C1 z −1 C1 1

H(z) = =
switched capacitor gain circuit. If we don’t reset C2 then C2 1 − z −1 C2 z − 1
we accumulate the input charge every cycle.
C. Noise
C Cz
Capacitors don’t make noise, but switched-capacitor circuits
Vos
do have noise. The noise comes from the thermal, flicker, burst
Cz noise in the switches and OTA’s. Both phases of the switched
capacitor circuit contribute noise. As such, the output noise of
a SC circuit is usually
Vith

Nt
a
VoEu Vn2 >
2kT
G C
N
I find that sometimes it’s useful with a repeat of mathematics,
andnosince we’re talking about noise.
The mean, or average of a signal is defined as
Mean
arrow
Z +T /2
The output now will grow without bounds, so integrators are 1
x(t) = lim x(t)dt
most often used in filter circuits, or sigma-delta ADCs where T →∞ T −T /2
there is feedback to control the voltage swing at the output of
the OTA. Define

VoEn I
VoEn
EtVicu
r

ElVo
Vo
É zaVi
HCA
ADVANCED INTEGRATED CIRCUITS - BUILT ON SUN JUN 8 16:43:19 UTC 2025 FROM A53266D730C2B7FE4FD6BA90E9C2B3586E43F3E2 11

Mean Square 1) OTA: At the heart of the SC circuit we usually find an OTA.
Maybe a current mirror, folded cascode, recycling cascode,
Z +T /2
1 or my favorite: a fully differential current mirror OTA with
x2 (t) = lim x2 (t)dt
T →∞ T −T /2 cascoded, gain boosted, output stage using a parallel common
mode feedback.
How much a signal varies can be estimated from the Variance
2 Not all SC circuits use OTAs, there are also comparator based
σ 2 = x2 (t) − x(t)
SC circuits.

where
σ Below is a fully-differential two-stage OTA that will work with
most SC circuits. The notation “24F1F25” means “the width
is the standard deviation. If mean is removed, or is zero, then is 24 F” and “length is 1.25 F”, where “F” is the minimum
gate length in that technology.
σ 2 = x2 (t)

Assume two random processes,

x1 (t)

and
x2 (t)

with mean of zero (or removed).

xtot (t) = x1 (t) + x2 (t)

x2tot (t) = x21 (t) + x22 (t) + 2x1 (t)x2 (t)

Variance (assuming mean of zero)

Z +T /2
2 1
σtot = lim x2tot (t)dt As bias circuit to make the voltages the below will work
T →∞ T −T /2

Z +T /2
2 1
σtot = σ12 + σ22 + lim 2x1 (t)x2 (t)dt
T →∞ T −T /2

Assuming uncorrelated processes (covariance is zero), then

2
σtot = σ12 + σ22

In other words, if two noises are uncorrelated, then we can sum

the variances. If the noise sources are correlated, for example,
noise comes from the same transistor, but takes two different
paths through the circuit, then we cannot sum the variances.
We must also add the co-variance.

2) Switches: If your gut reaction is “switches, that’s easy”, then

D. Sub-circuits for SC-circuits
you’re very wrong. Switches can be incredibly complicated.
Switched-capacitor circuits are so common that it’s good All switches will be made of transistors, but usually we don’t
to delve a bit deeper, and understand the variants of the have enough headroom to use a single NMOS or PMOS. We
components that make up SC circuits. may need a transmission gate
ADVANCED INTEGRATED CIRCUITS - BUILT ON SUN JUN 8 16:43:19 UTC 2025 FROM A53266D730C2B7FE4FD6BA90E9C2B3586E43F3E2 12

C E E

A B A B A B

c E
c

A B
c e
C
c e
A c e B c
A B
The challenge with transmission gates is that when the voltage
at the input is in the middle between VDD and ground then
both PMOS and NMOS, although they are on , they might
C
not be that on. Especially in nano-scale CMOS with a 0.8 V
supply and 0.5 V threshold voltage. The resistance mid-rail
might be too large.
For switched-capacitor circuits we must settle the voltages to looks like the one below.
the required accuracy. In general

t > − log(error)τ

For example, for a 10-bit ADC we need t > − log(1/1024)τ =

6.9τ . This means we need to wait at least 6.9 time constants
i
i
for the voltage to settle to 10-bit accuracy in the switched Be
capacitor circuit.
Assume the capacitors are large due to noise, then the switches Ap
must be low resistance for a reasonable time constant. Larger
switches have smaller resistance, however, they also have more
charge in the inversion layer, which leads to charge injection
when the switches are turned of. Accordingly, larger switches
are not always the solution.
E e
Sometimes it may be sufficient to switch the bulks, as shown C E
on the left below. But more often that one would like, we have g
to implement bootstrapped switches as shown on the right. An Bu

E
3) Non-overlapping clocks: The non-overlap generator is
e
standard. Use the one shown below. Make sure you simulate
c
c e
that the non-overlap is sufficient in all corners.
A c e B c
A B

C
on

if
a
ur

The switch I used in my JSSC SAR is a fully differential

boostrapped switch with cross coupled dummy transistors. The
JSSC SAR I’ve also ported to GF130NM, as shown below. a
The switch is at the bottom.
i
i
wulffern/sun_sar9b_sky130nm Be

cutis
Vo Vi n
Ap Cg
H
VoZ
Evi HE
ga
E e
C E
ADVANCED INTEGRATED CIRCUITS - BUILT ON SUN JUN 8 16:43:19 UTC 2025 FROM A53266D730C2B7FE4FD6BA90E9C2B3586E43F3E2 13

E. Example to currently Principle IC Scientist. He’s also an Adjunct

In the circuit below there is an example of a switched capacitor Associate Professor at NTNU. His present research interests
circuit used to increase the ∆VD across the resistor. We can includes analog and mixed-signal CMOS design, design of high-
accurately set the gain, and thus the equation for the differential efficiency analog-to-digital converters and low-power wireless
output will be transceivers. He is the developer of Custom IC Compiler, a
general purpose integrated circuit compiler.
kT
VO (z) = 10 ln(N )z −1
q

n
I 2

TCalooff

VI. WANT TO LEARN MORE ?

Blind Multiband Signal Reconstruction: Compressed Sensing
for Analog Signal
Comparator-based switched-capacitor pipelined analog-to-
digital converter with comparator preset, and comparator delay
compensation
A Compiled 9-bit 20-MS/s 3.5-fJ/conv.step SAR ADC in 28-nm
FDSOI for Bluetooth Low Energy Receivers
A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor
Switching Procedure
Low Voltage, Low Power, Inverter-Based Switched-Capacitor
Delta-Sigma Modulator
Ring Amplifiers for Switched Capacitor Circuits
A Switched-Capacitor RF Power Amplifier
Design of Active N-Path Filters
Carsten Wulff received the M.Sc.
and Ph.D. degrees in electrical
engineering from the Department
of Electronics and Telecommuni-
cation, Norwegian University of
Science and Technology (NTNU),
in 2002 and 2008, respectively.
During his Ph.D. work at NTNU,
he worked on open-loop sigma-
delta modulators and analog-to-digital converters in nanoscale
CMOS technologies. In 2006-2007, he was a Visiting Re-
searcher with the Department of Electrical and Computer
Engineering, University of Toronto, Toronto, ON, Canada.
Since 2008 he’s been with Nordic Semiconductor in various
roles, from analog designer, to Wireless Group Manager,