US 2010.

0020860A1
(19) United States
(12) Patent Application Publication (10) Pub. No.: US 2010/0020860 A1
Dai et al. (43) Pub. Date: Jan. 28, 2010
(54) METHODS AND APPARATUS FOR JOINT Publication Classification
ADAPTATION OF TRANSMITTER (51) Int. Cl
TRANSVERSAL FILTER IN H04L 27/0 (2006.01)
COMMUNICATION DEVICES (52) U.S. Cl. .......................... 375/231; 375/232; 375/233
(57) ABSTRACT
(76) Inventors: Xingdong Dai, Bethlehem, PA
(US); Dwight D. Daugherty, Methods and apparatus are provided for joint adaptation of
Ephrata, PA (US); Max J. Olsen, filter values in two communicating devices, such as a link
Mertztown, PA (US); Geoffrey partner and a link device. The disclosed joint adaptation pro
Zhang Allentown f'A (US) cess initially adapts the filter coefficient values in a first of the
s s two communicating devices until a predefined stopping cri
teria is satisfied. Thereafter, the filter coefficient values in a
Correspondence Address: second of the two communicating devices are adapted once
Ryan, Mason & Lewis, LLP the predefined stopping criteria for the first communicating
Suite 205, 1300 Post Road device is satisfied. The filter coefficient values can comprise
Fairfield, CT 06824 (US) coefficient values of a multi-tap filter. The predefined stop
ping criteria may determine, for example, whether the first of
(21) Appl. No.: the two communicating devices is overequalized. The filter
12/178,301 coefficient values can be determined by including a contribu
tion of only certain cursor tap values of the channel impulse
(22) Filed: Jul. 23, 2008 response.

1020
SICER - 1010 18- vio

PROFILE PROGRAMMABLE 900

SELECT
CURSOR WEIGHTS
(PRE-CURSOR) 1040

SIGN: O = +1, 1 = -1 SUM

1050 (TO ACCUMULATOR) 1045
SE PROGRAMBLE Y1 V2 y V4 V5 v6
CURSOR WEIGHTS - - - - - - - - - - - - -H, ---------------------------
MAIN CURSOR (6) to
SIGN: O = +1, 1 = -1 SUM
1070 (TO ACCUMULATOR) 1065
PROFILE PROGRAMMABLE Y1 V2 y V4 V5 v6
SELECT
CURSORWEIGHTS - - - - - - - - - - - - - -H, --------------------------- 6
(POST-CURSOR) (6) o
SIGN: O = +1, 1 = -1 SUM
(TO ACCUMULATOR) 1085
Patent Application Publication Jan. 28, 2010 Sheet 1 of 8 US 2010/002O860 A1

FIC. 1
PRIOR ART

DATA LINK
XGMI XCMI 10G MEDIA INDEPENDENT INTERFACE
PCS: PHYSICAL CODING SUBLAYER
FEC: FORWARDERROR CORRECTION (OPTIONAL)
PHYSICAL PMA PHYSICAL MEDIUM ATTACHMENT
PMD: PHYSICAL MEDIUM DEPENDENT
AN AUTO-NEGOTIATION
MDI MDI: MEDIUM DEPENDENT INTERFACE
10BASE-KR MEDIUM
Patent Application Publication Jan. 28, 2010 Sheet 3 of 8 US 2010/002O860 A1

FIG. 3
PRIOR ART 300
UI/BIT BYTE a?
52 4
128 16 CONTROL
128 16 CHANNEL
4096 512

FIG. 4

PMD ADAPTATION START 410

PRESET LD RX 420
DFE PARAMETERS

LINK PARTNER TX ADAPT LP TX FIR

FILTER ADAPTATION, COEFFICIENTS WA PMD
CONSTRAINED BY
MAXIMUM TIMER. 440

450
REDUCE LP TX
EQUALIZATION
YES
FREEZE LP TX
LINK DEVICE RX DFE FIR COEFFICIENTS
ADAPTATION ON PMD
DATA FRAME, AS WOULD
IN NORMAL OPERATION. ADAPT LD RX
480
DFE PARAMETERS

PND ADAPTATION ENDS 490

Patent Application Publication Jan. 28, 2010 Sheet 4 of 8 US 2010/002O860 A1

FIG. 6
PRIOR ART
Patent Application Publication Jan. 28, 2010 Sheet 5 of 8 US 2010/002O860 A1

FIG. 6
PRIOR ART

650 ADAPTIVE
TARGET LEVEL
600 \

60

ALE + VGA
Patent Application Publication Jan. 28, 2010 Sheet 6 of 8 US 2010/002O860 A1

FIC 7
PRIOR ART
Patent Application Publication Jan. 28, 2010 Sheet 7 of 8 US 2010/002O860 A1

FIC. 8
800
CURSOR MAPPED PROFILE VALUES OF p
POSITION ALGORITHM - I ALGORITHM - II ALGORTHM - I
PRE-CURSOR 0,1,0,0,0,0,0) 1,1,0,0,0,0,0,1,1,0,0,0,0,0)
MAIN CURSOR 0,0,1,0,0,0,0) | 0,0,1,0,0,0,0,0,0,1,0,0,0,0)
POST-CURSOR 0,0,0,1,0,0,0,0,0,0,0,1,0,0,0,0,0,1,1,1,1)

FIG. 9

DATA 900

VECTOR: V(3) V(2) V(1) V(0)

Patent Application Publication Jan. 28, 2010 Sheet 8 of 8 US 2010/002O860 A1

0(SWO8I1N|W)Œ_DO
US 2010/002O860 A1 Jan. 28, 2010

METHODS AND APPARATUS FOR JOINT second communicating device comprise parameter values of
ADAPTATION OF TRANSMITTER a decision feedback equalizer in a receiver of a link device.
TRANSVERSAL FILTER IN 0008. The predefined stopping criteria may determine, for
COMMUNICATION DEVICES example, whether the first of the two communicating devices
is overequalized. Once the predefined stopping criteria for the
FIELD OF THE INVENTION first communicating device is satisfied, the disclosed process
0001. The present invention relates generally to filter coef can optionally maintain the filter coefficient values in the first
ficient adaptation techniques for digital communications, and communicating device.
more particularly, to techniques for joint adaptation of filter 0009. In exemplary implementations, the filter coefficient
coefficient values in communicating devices, such as a link values are determined by including a contribution of (i) only
partner and a link device. a main-cursor channel impulse response; (ii) only a main
cursor, a first post-cursor and a first pre-cursor channel
BACKGROUND OF THE INVENTION impulse response; and (iii) a main-cursor, a first pre-cursor
and at least one post-cursor channel impulse response. Pro
0002 10 Gigabit Ethernet (10GbE) is a set of Ethernet grammable profile values can optionally be stored in a regis
standards with a nominal data rate of 10.3125 Gbit/s. 10GbE ter or another memory device, wherein the one or more pro
over fiber, copper cabling and twisted pair are specified by the grammable profile values indicate cursor tap values that
IEEE 802.3 standard. IEEE 802.3 is a collection of Standards contribute to the filter coefficient values.
defining the physical layer, and the media access control 0010. A more complete understanding of the present
(MAC) sublayer of the data link layer for wired Ethernet. invention, as well as further features and advantages of the
IEEE 802.3ap, for example, provides a standard for Back present invention, will be obtained by reference to the follow
plane Ethernet over printed circuit boards, with rates of 1.25 ing detailed description and drawings.
and 10.3125 Gbit/s.
0003. The IEEE 802.3ap standard defines the physical BRIEF DESCRIPTION OF THE DRAWINGS
medium dependent sublayer (PMD) control function. The
PMD control function implements the 10GBASE-KR start (0011 FIG. 1 illustrates the ISO OpenSystem Interconnec
up protocol, which provides a joint adaptation mechanism tion reference model for 10GBASE-KR from IEEE draft
through which the local receiver can tune the link-partner P802.3ap:
transmit equalizer to optimize performance over the back 0012 FIG. 2 is a schematic block diagram of a link partner
plane interconnect, and to inform the link partner when train and a link device communicating over a channel to implement
ing is complete and it is ready to receive data. This mechanism a joint adaptive equalization process;
is implemented through the continuous exchange of fixed 0013 FIG.3 illustrates an exemplary training frame struc
length training frames. These training frames are used by the ture in accordance with the IEEF 802.3ap standard;
two physical layer devices to exchange control and status (0014 FIG. 4 is a flow chart of an exemplary PMD joint
information necessary to configure the adaptive equalization adaptation process incorporating features of the present
filters for both devices. invention;
0004. A number of joint equalization adaptation tech 0015 FIG. 5 is a schematic block diagram of an exemplary
niques have been proposed or suggested for use with the TX 3-tap transversal filter pursuant to the 10GBASE-KR
10GBASE-KR standard. These existing techniques, however, standard;
are typically based on a primitive eye diagram visual exami 0016 FIG. 6 is a schematic block diagram of the equal
nation or on an incomplete mathematical derivation, with ization components of a conventional receiver circuit;
inadequate assumptions. Consequently, the resulting imple 0017 FIG. 7 illustrates an impulse response for an exem
mentations are not sufficient or complete. More often, these plary backplane channel;
existing proposals are overly complicated, and may degrade 0018 FIG. 8 is a table summarizing programmable profile
the overall link performance. values for exemplary algorithms in accordance with the
0005. A need therefore exists for improved methods and present invention;
apparatus for joint adaptation of the transmitter transversal 0019 FIG. 9 is a circuit diagram illustrating a 2's comple
filter in Serializer-Deserializer (SerDes) devices. ment vector converter; and
0020 FIG. 10 is a diagram illustrating an exemplary hard
SUMMARY OF THE INVENTION ware implementation of the disclosed unified joint adaptation
algorithm.
0006 Generally, methods and apparatus are provided for
joint adaptation of filter values in two communicating DETAILED DESCRIPTION
devices. Such as a link partner and a link device. The disclosed
joint adaptation process initially adapts the filter coefficient 0021. The present invention provides methods and appa
values in a first of the two communicating devices until a ratus for joint adaptation of the transmitter transversal filter.
predefined stopping criteria is satisfied. Thereafter, the filter According to one aspect of the present invention, the dis
coefficient values in a second of the two communicating closed joint adaptation algorithm provides a means to control
devices are adapted once the predefined stopping criteria for the amount of equalization as well as the transmitter output
the first communicating device is satisfied. amplitude. As a result, (i) link channel equalization is shared
0007. The filter coefficient values can comprise coefficient between the TX and the RX, and the ratio of distribution is
values of a multi-tap filter. For example, the filter coefficient controllable; (ii) the overall system power consumption is
values in the first communicating device may comprise coef reduced; and (iii) the impact of noise and crosstalk on the
ficient values of a finite impulse response filter in a transmitter received signal is minimized, thus permitting a better signal
of a link partner, while the filter coefficient values in the integrity in the system. Among other benefits, the computa
US 2010/002O860 A1 Jan. 28, 2010

tional complexity of the disclosed algorithms is reduced rela The training pattern is required to be a 512 byte pattern of
tive to existing adaptation algorithms, which can directly PRBS11 and 2 Zero bits. As specified, each frame will have
translate into area and cost savings for a hardware implemen 4384 bits of data.
tation. (0027. Through the use of PMD, 10GBASE-KR provides a
0022 FIG. 1 illustrates the ISO OpenSystem Interconnec means for a link device to adjust the TX filter coefficients of
tion (OSI) reference model for 10GBASE-KR from IEEE its link partner. The 10GBASE-KR standard, however, does
draft P802.3ap. As previously indicated, the physical medium not specify how and in what way the TX equalization shall be
dependent (PMD) sub-layer implements the 10GBASE-KR done with respect to the receiver decision feedback equaliza
start-up protocol and brings the physical layer (PHY) from tion (DFE). The only constraint is a maximum time limit of
initialization to a mode in which data may be exchanged with 500 ms. It can be shown that when both RX and TX adaptation
the link partner (LP). The 10GBASE-KR start-up protocol are carried out concurrently, equalization parameters can
provides a joint adaptation mechanism through which the experience very large perturbations, thus may not converge to
local receiver can tune the link-partner transmit equalizer an optimal setting when the timer expires. In corner cases, no
(and vice versa) to optimize performance over the backplane stable state of parameters can be reached. As discussed here
interconnect, and to inform the link partner when training is inafter in conjunction with FIG. 4, the present invention rec
complete and it is ready to receive data. ognizes that serializing the LP TX filter and LD RX DFE
0023 FIG. 2 is a schematic block diagram of a link partner adaptation is a more effective approach.
(LP) 210 and a link device (LD) 230 communicating over a 0028. It is noted that both the TX and RX are equipped
channel 220 to implement a joint adaptive equalization pro with channel equalization capabilities. By separating the two
cess. A 10GBASE-KR PHY is required to transmit and functions, one can spread the equalization cost to both ends,
receive training frames during the startup protocol. The train thus avoid overworking one circuit while keeping the other
ing frames are transmitted and received repeatedly until both one underutilized. This strategy permits maximum usage and
devices (LP and LD) reach an agreement on the control infor extracts most benefits of very limited resources. This can
mation necessary to configure their adaptive equalization fil bring significant advantage to the system level design. An
ters. In general, the receiver indicates the emphasis param overequalized transmitter consumes more power and at the
eters (coefficient values for pre, main, and post cursors in a same time increases the noise contribution through crosstalk.
finite impulse response filter) to the transmitter, in a known For a better performance, one would like to have the trans
a. mitter output properly equalized or slightly under equalized.
0024. As shown in FIG. 2, on the transmit path of the link By isolating the TX adaptation from the RX adaptation, the
partner 210, the transmit data (TXDATA) is applied to a present invention tunes each equalization parameterindividu
multiplexer 240, together with an output from the PMD 244. ally to a desired specification.
As indicated above, PMD 244 and 262 allow a link device 230 (0029 FIG. 4 is a flow chart of an exemplary PMD joint
to adjust the TX filter coefficients of its link partner 210. adaptation process 400 incorporating features of the present
Following equalization 242, the signal is transmitted across invention. Generally, the PMD joint adaptation process 400
the channel 250 to the link device 230. On the receive path of separates the TX adaptation and initially performs the TX
the link device 230, the received signal is processed by an adaptation in an exemplary embodiment to determine if the
analog linear equalizer (ALE) and decision feedback equal waveform is over-equalized before performing RX adapta
izer (DFE) 260 to generate the recovered data RXDATA tion. The exemplary PMD joint adaptation process 400 is
The recovered data RXDATA, is also applied to the PMD implemented by the link device 230. More particularly, the
layer 262 of the link device 230. exemplary PMD joint adaptation process 400 is typically
0025 FIG.3 illustrates an exemplary training frame struc implemented by the PMD 262 of the link device 230. It is
ture 300 in accordance with the IEEE 802.3ap standard. As noted that corresponding steps (not shown) are performed by
shown in FIG. 3, the exemplary training frame structure 300 the link partner 210.
comprises a four octet frame marker, a 16 octet (1 octet=8 0030. The PMD joint adaptation process 400 is initiated
bits) coefficient update (e.g., instructions for FIR coefficient following the auto-negotiation (AN) (FIG. 1) that is per
settings of link partner transmitter), a 16 octet status report formed when a link device 230 is coming out of reset. When
and a 512 octet PN11 training pattern. The four octet frame auto-negotiation ends with an agreed speed (10G only at
marker delimits each frame using a 32-bit pattern, hexadeci present time) with a link partner 210, the auto-negotiation
mal FFFF0000. This pattern is said to provide a unique indi sends a signal to the PMD 262 to start the joint adaptation
cation of the start of a training frame. The next two fields for process 400 as shown in FIG. 4. In one exemplary embodi
the coefficient update and status report (256 bits) are trans ment, Steps 410 to 490 of the PMD joint adaptation process
mitted using Differential Manchester Encoding (DME), as 400 are state machine processes implemented within the
discussed further below in conjunction with FIG. 2. Finally, PMD 262 (and/or on an embedded processor associated with
the 512 octet PN11 training pattern is transmitted. PMD, such as an 8051 processor from Intel Corp.).
0026. A 10GBASE-KR device is often required to trans 0031. As shown in FIG. 4, the PMD joint adaptation pro
mit and receive training frames 300 during the startup proto cess 400 is started during step 410. Thereafter, the LD RX
col. The training frames are transmitted (and received) repeat DFE parameters are preset during step 420. During step 420,
edly until both devices reach an agreement on the control the PMD 262 sends a signal to freeze RX parameters of the
information necessary to configure their adaptive equaliza ALEADFE 26O.
tion filters. Each frame includes 4384 bits of data. These bits 0032 Generally, during steps 430-460, the PMD 262 con
are typically transmitted at the 10G speed (1 bit per Unit tinuously sends control information (e.g., a PMD training
Interval). In 10GBASE-KR, the control channel is signaled frame 300 of FIG. 3) to the link partner 210. The LPTX FIR
using differential Manchester encoding (DME). Every bit of coefficients are then adapted during step 430 via the PMD.
the control channel is transmitted in eight unit intervals (UIs). The PMD 244 of the link partner 210 parses the packet con
US 2010/002O860 A1 Jan. 28, 2010

tent and adjusts the filter coefficients (FIG.5) as the PMD 262 result of joint adaptation. The PMD function completes and
has requested, by incrementing (+1), decrementing (-1), or stops sending the training patterns and normal data traffic
no change (0) for filter coefficients, c, co, c, for the 3 taps. StartS.
Once the PMD 244 completes the required action, the PMD 0039 FIG. 5 is a schematic block diagram of an exemplary
244 updates the status report field of FIG.3 of its next PMD TX3-tap transversal filter 500 pursuant to the 10GBASE-KR
training frame 300 and sends the frame to the link device 230. standard. As shown in FIG. 5, the 3 taps are typically referred
The status can be “completed’ or “not completed reaching to as pre-cursor 550, main-cursor 560 and post-cursor 570.
limit. During the joint equalization adaptation process, the filter
0033. A test is performed during step 440 to determine if coefficients, c, co, c, for the 3 taps (or tap weights) are
adjusted between a pair of 10GBASE-KR-compliant PHY
the TX is overequalized. The link device 230 receiver front Serializer-Deserializer (SerDes) devices (LP and LD). A defi
end (ALE 260) examines the incoming waveform from the ciency in one prior adaptation algorithm is that the main
link partner 210 through channel 250. If ALE 260 determines cursor co has a fixed value and is not adaptive. The disclosed
that the signal is over-equalized during step 440, the ALE 260 algorithm enables full adaptation of all filter coefficients, c.
sends a signal to the PMD 262. The PMD 262 will then co, c. For simplicity, a 3-tap filter is employed as an example
modify the coefficient update field of its next PMD training to illustrate the disclosed algorithm. However, the algorithms
pattern 300 to instruct the link partner 210 during step 450 to and implementations described below, can be easily extended
reduce the TX pre-emphasis. This information is again taken to a transmit FIR filter of arbitrary tap length, as would be
by the PMD 244 of the link partner 210 and translated into a apparent to a person of ordinary skill in the art. Thus, cases
reduced pre-emphasis by equalizer 242. over three taps are considered to be covered by the present
0034 Generally, an ideal signal, when observed in the invention as well.
frequency domain, should have a certain spectrum. When this 0040. As shown in FIG. 5, XIn 510 represents a digital
signal passes through a channel, the output signal will have its signal sampled at instant in A. Therefore, Xn-1 is the signal
spectrum modified by the channel and thus deviates from the at an earlier sampling instant and XI n+1 is a later sample.
ideal spectrum. A mechanism is used to change the signal Since it is a digital signal, the sample is either logic 1 or 0
Such that the final spectrum remains unchanged. This process (sometimes referred to as +1 and -1).
is called equalization. 0041. As shown in FIG. 5, blocks 520 and 530 represent a
0035. For high speed communications, the channel usu unit delays, which is equal to one unit interval (UI) for NRZ
ally has a low-pass characteristic. As a result, high frequency signaling. Thus, the signal through block 590 is one UI earlier
energy is attenuated more than the low frequency compo than that through block 580 and is two UI periods earlier than
nents. In this case, equalization attempts to boost the high that through block 540.
frequency band and/or reduce low frequency band energy. If 0042. Now, the signals at three consecutive sampling
this boost restores the spectrum to its original one, then the blocks are modified by, c, co, and c such that, when com
equalization is called proper. If this boost is not enough, Such bined at the adder 592, the output 595 becomes the pre
that the high frequency energy is under-compensated, the emphasized signal. The signs at the adder are important. In
amount of equalization is then called “under-equalization. If the embodiment of FIG. 5, the low frequency energy is
this boost is too much such that the high frequency energy is reduced, which is equivalent to a relative boost at high fre
over-compensated, then the amount of equalization is called quencies.
“over-equalization'.
0036. If it is determined during step 440 that the TX is not Joint Adaptation Algorithm
overequalized, then a further test is performed during step 0043. As previously indicated, the present invention pro
460 to determine if the equalization limit has been reached. If vides an improved joint adaptation algorithm for the link
the PMD 262 decodes the status field of the received training device RX to determine the optimal filter coefficients, c, of
pattern 300 as “reaching limit” and it is determined during the link partner TX (and, respectively, for the link partner RX
step 440 that there is no overequalization from the ALE/DFE to determine link device TX filter coefficients, c).
260, then there is no further LP TX modification. The PMD 0044 FIG. 6 is a schematic block diagram of the equal
262 will freeze the coefficient update field of remaining train ization components of a conventional receiver circuit 600. As
ing patterns 300 using a code “no change.” and the PMD 262 shown in FIG. 6, the signal is first processed by an Analog
will send a signal to ALE/DFE 260 to start the RX DFE Linear Equalizer and Voltage Gain Amplifier 610, having an
adaptation. output signal, r. The signal r, modified by the output from
0037. If it is determined during step 460 that the equaliza block 650, produces signalyy is then sampled by the slicer
tion limit has not been reached, then program control returns block 630 to get a digital signala (an estimate of what was
to step 430 and continues in the manner described above. If, transmitted). It is noted that randy are analog signals.
however, it is determined during step 460 that the equalization I0045. At block 660, a is modified by h, which is now an
limit has been reached, then the LPTX FIR coefficients are analog signal. This signal is compared with the input at the
fixed during step 470. Thereafter, the LDRX DFE parameters slicer,y. The comparison producese, which is an error term.
are adapted during step 480 and the PMD adaptation ends This error, together with the current decision (a) and some
during step 490. earlier decisions (a,a2, and so on), will be processed by
0038. The PMD joint adaptation process 400 ends when an adaptive algorithm at block 650. The output from the
the receiver is satisfied with the result, usually by means of “adaptive' block 650 is the feedback to block 620. Note, the
internal or external bit error rate test (BERT) measurements description “Target level” is for “h”.
or eye diagram/contour checking, in a known manner. There 0046 r at the output of block 610, can be obtained as a
may also be a maximum time limit, for example, of 500 ms, convolution of the transmit data at the transmit filter c and
for joint adaptation. Thus, the process 400 ends when either the channel p as follows:
the timer expires or the link device 230 is satisfied with the raic pX,(CX, (a sp;)). (1)
US 2010/002O860 A1 Jan. 28, 2010

0047. As shown in FIG. 6, the input signal y to the slicer 0056 Algorithm-II: The adaptation algorithm-I can have
is defined as: the transmit output over-equalized in some cases, thus limit
Jkr-21smseh, di-n). (2) ing the useful range of receiver target level. This can be
corrected by replacing the strong contributor of po with a
0048. The errore, is defined as: weaker p for the post cursor, and extending the precursor
edhoy. (3) contributor to include p .
0049 Taking equations (1) and (2) into equation (3) and C 1-C 1-1+sign(e)sign(d. 2+di- ),
using at as an estimate for a in (1), one can express eas: Co-Co-1+sign (e-)sign(d),
e-CRx-X (CX,(d. sp;)), (4)
C1-C1-1+sign (e-)sign (d. 2). (10)
where:
0057 Equation (10) is still simpler than existing algo
CRx-dihot) 1sms (ha-m). (5)
rithms and provides full adaptation of all TX filter coefficients
of the link partner. It can be shown that with Algorithm-II, the
0050. In FIG.4, the receiver DFE parametersh, Osmsp RX front end VGA gain is -6 dB, -4 dB, -2 dB, 0 dB, 2 dB,
are preset in the link device (LD) for link partner (LP) trans 4 dB, and 6 dB. It has been observed that with Algorithm-II,
mitter filter adaptation. Therefore, C is not a function of no transmitter over-equalization occurred, which is desirable
transmitter filter coefficients c, and: in the system. It is noted that a partially closed eye delivered
to the RX is actually a good thing for the following main
de/dc-X, (a sp;). (6) reasons: (1) the RX often has strong equalization capabilities,
0051 Applying the sign-sign least-mean-square (LMS) but usually cannot re-process an over-equalized signal; (2) for
adaptive algorithm, one can obtain the TX filter coefficients: the same signal amplitude, an under-equalized signal requires
much less signal output from the TX, thus reducing overall
system power consumption; (3) a reduced TX output works as
cik = cik 1 - sign(ek)sign(Öek foci) (7) a weaker crosstalk aggressor, which improves system SNR
(signal-to-noise ratio).
= c k-1 + sign(ek sigr() (a lip) 0.058 Algorithm-III: Algorithm-III improves upon algo
rithm-II by balancing out the strong contributor of po with
weaker contributors of p. p and p for the post cursor.
0.052. In general, one does not process a prior knowledge C 1-C 1-1+sign(e)sign(d. 2+di- ),
of backplane characteristics, and therefore the actual values
of p, Co-Co-1+sign (e-)sign(d),
0053 FIG. 7 illustrates an impulse response for an exem
plary backplane channel. For a practical channel. Such as the C1-C1-1+sign (e-)sign (d. 1+d 2+d 3+d 4). (11)
exemplary channel in FIG. 7, the impulse response is usually 0059. The overall complexity of equation (11) is still sim
dominated by p,-1sis3. With that, the TX filtercoefficients pler than existing designs and it also provides full adaptation
c can be expressed for the precursor, co for the main cursor of all TX filter coefficients of the link partner. It can be shown
and c for the post cursor from equation (7), as shown in that with Algorithm-II, the RX front end VGA gain is -6 dB,
equation (8). It is important to note that a has a value of either -4 dB, -2 dB, 0 dB, 2 dB, 4 dB, and 6 dB.
1 or -1. 0060. It has been observed that Algorithm-III has better
performance with slightly increased complexity compared to
the disclosed algorithm-II. For some cases that use algorithm
II, the channel is under-equalized by the transmitter. It may
require a good receiver equalizer to ensure error-free data
communication. Algorithm-III can work with less efficient
receiver side equalizer and much wider range of target level.
0061. To summarize, for Algorithm-II and Algorithm-III,
on the c coefficient, the first pre-cursor and main cursor are
Adaptation Algorithms employed. For all three algorithms, on the co coefficient, only
0054 Algorithm-I: Frequently po is the most dominant the main cursor is used. For the c coefficient, only the first
value. However, it would be incorrect to assume that all p, post-cursor is used for Algorithm-II and more than one post
have identical values. For the first algorithm, po is assumed to cursor is used for Algorithm-III.
be the main concern on the channel, so po1 and p, Oforiz0. Unified Implementation with Programmable Profile
Thus, equation (8) can be expressed as follows: Selection
C 1-C 1-1+sign(e)sign(d. 1), 0062. Upon examination of equations (9-11), it can be
seen that algorithm I, II and III are variations of equation (8)
Co-Co i+sign(e)sign(d), with different p, values. For hardware and software imple
C1-C1-1+sign(e)sign (d. 1). (9)
mentations, one can store these values in user programmable
registers, further extending the flexibility of the baseline
0055 Equation (9) is much simpler than existing algo architecture. FIG. 8 is a table 800 Summarizing the program
rithms, while providing full adaptation of all TX filter coef mable profile values for algorithm I, II and III as discussed
ficients of the link partner. It can be shown that with Algo further below in conjunction with FIG. 10. In general, each
rithm-I, the RX front end VGA gain is -6 dB, -4 dB, -2 dB, value stored in the table 800 is a vector with each entry in the
0 dB, 2 dB, 4 dB, and 6 dB. vector indicating whether the corresponding filter tap (e.g.,
US 2010/002O860 A1 Jan. 28, 2010

pre-, main and post cursor taps) contribute to the coefficient between the link device and link partner. This load balancing
computation. The value of a in the digital domain is binary permits both ends to operate at or near an optimal perfor
with 0 representing integer -1. mance level.
0063 FIG.9 is a circuit diagram illustrating a 2's comple 0070 The selectivity of tap strength permits the receiver to
ment vector converter 900. The data converter 900 replaces a tune the transmitter output power in order to optimize system
binary value 0 (integer -1) with a 4-bit vector 1111, which is power. In addition, the selectivity of tap strength can be used
a 2's complement representation of -1. Similarly, the data to minimize the crosstalk at the transmitter side, thus enhanc
converter 900 converts a binary value 1 (integer 1) to a 4-bit ing overall system performance.
vector 0001. It should be evident that one can extend the size 0071 While the present invention is illustrated in the con
of the profile to any arbitrary length, as a given application text of the 10GBASE-KR standard, the disclosed algorithms
permits, as would be apparent to a person of ordinary skill in can be extended to other multi-tap filters beyond the scope of
the art.
10GBASE-KR, as would be apparent to a person of ordinary
skill in the art. The implementation also provides a means to
0064. In FIG.9, for the algorithms I, II, III shown, only the adjust the filter coefficients non-sequentially.
sign value is used and the sum is discarded. However, one can 0072 A complete PMD joint adaptation flow is obtained,
easily extend the concept as illustrated here and utilize the where link partner and link device adaptation is serialized to
Sum to create multi-level decision making for coefficients ensure a faster adaptation while minimizing erroneous per
update. This can be considered as an extension to the turbations to filter coefficients.
10GBASE-KR standard, where one can not only incrementor 0073 While exemplary embodiments of the present
decrement the values, i.e., plus one or subtract by one to the invention have been described with respect to digital logic
coefficients, but also increase or decrease the coefficient by blocks, as would be apparent to one skilled in the art, various
more-than-one based upon the sum values of FIG. 10. It may functions may be implemented in the digital domain as pro
allow a fast convergence of filter coefficients, thus speed up cessing steps in a software program, in hardware by circuit
the system start up time. elements or state machines, or in combination of both soft
0065 FIG. 10 is a diagram illustrating an exemplary hard ware and hardware. Such software may be employed in, for
example, a digital signal processor, micro-controller, or gen
ware implementation 1000 of the disclosed unified joint eral-purpose computer. Such hardware and Software may be
adaptation algorithm. As shown in FIG. 10, a received signal embodied within circuits implemented within an integrated
is first applied to a slicer 1010 and is then sampled by a circuit.
plurality of serial latches 1020. The data values d(0) ... d(6) 0074 Thus, the functions of the present invention can be
are then each applied to a corresponding 2's complement embodied in the form of methods and apparatuses for prac
vector converter 900 of FIG. 9. The four bit vectors v0... v6
generated by each 2's complement vector converter 900 are ticing those methods. One or more aspects of the present
then applied to a corresponding AND gate 1040 with the invention can be embodied in the form of program code, for
programmable cursor weights p-1(0) . . . p-1(6) for the pre example, whether stored in a storage medium, loaded into
cursor tap, as obtained from stage 1030. The outputs of the and/or executed by a machine, or transmitted over some trans
AND gates 1040 are then summed by an adder 1045. mission medium, wherein, when the program code is loaded
into and executed by a machine. Such as a computer, the
0.066. Likewise, for the main cursor, the four bit vectors v0 machine becomes an apparatus for practicing the invention.
... v6 generated by each 2's complement vector converter 900 When implemented on a general-purpose processor, the pro
are then applied to a corresponding AND gate 1060 with the gram code segments combine with the processor to provide a
programmable cursor weights p0(0) . . . p0(6) for the main device that operates analogously to specific logic circuits.
cursor tap, as obtained from stage 1050. The outputs of the The invention can also be implemented in one or more of an
AND gates 1060 are then summed by an adder 1065. Finally, integrated circuit, a digital signal processor, a microproces
for the post-cursor, the four bit vectors v0... v6 generated by Sor, and a micro-controller.
each 2's complement vector converter 900 are then applied to 0075. A plurality of identical die are typically formed in a
a corresponding AND gate 1080 with the programmable cur repeated pattern on a surface of the wafer. Each die includes
Sor weights p1(0) ... p1(6) for the post-cursor tap, as obtained a device described herein, and may include other structures or
from stage 1070. The outputs of the AND gates 1080 are then circuits. The individual die are cut or diced from the wafer,
summed by an adder 1085. then packaged as an integrated circuit. One skilled in the art
0067 Conclusion would know how to dice wafers and package die to produce
0068 Among other benefits, the disclosed algorithms pro integrated circuits. Integrated circuits so manufactured are
vide full adaptation of all transmitter filter coefficients of a considered part of this invention.
link partner. In this manner, the disclosed algorithms conform 0076. It is to be understood that the embodiments and
to high data rate interconnect standards. A 3-tap TX filter is variations shown and described herein are merely illustrative
specified by 10GBASE-KR standard. In addition, the dis of the principles of this invention and that various modifica
closed algorithms have a wider range for receiver target level tions may be implemented by those skilled in the art without
(h). Consequently, the disclosed algorithms are able to maxi departing from the scope and spirit of the invention.
mize the signal-to-noise ratio (SNR).
0069. The disclosed algorithms and implementations pro We claim:
vide flexibility to select cursor tap strength. As a result, the 1. A method for joint adaptation of filter coefficient values
disclosed algorithms and implementations can prevent put in two communicating devices, said method comprising:
ting all equalization burdens on the TX side and/or underuti adapting said filter coefficient values in a first of said two
lize the receiver equalizer. A system utilizing the disclosed communicating devices until a predefined stopping cri
algorithms is able to distribute the equalization requirements teria is satisfied; and
US 2010/002O860 A1 Jan. 28, 2010

adapting said filter coefficient values in a second of said a memory; and

two communicating devices once said predefined stop at least one processor, coupled to the memory, operative to:
ping criteria for said first communicating device is sat adapt said filter coefficient values in a first of said two
isfied. communicating devices until a predefined stopping cri
2. The method of claim 1, wherein said filter coefficient teria is satisfied; and
values in said first communicating device comprise coeffi adapt said filter coefficient values in a second of said two
cient values of a finite impulse response filter in a transmitter communicating devices once said predefined stopping
of a link partner. criteria for said first communicating device is satisfied.
14. The apparatus of claim 13, wherein said filter coeffi
3. The method of claim 1, wherein said filter coefficient cient values in said first communicating device comprise
values in said second communicating device comprise coefficient values of a finite impulse response filter in a trans
parameter values of a decision feedback equalizer in a mitter of a link partner.
receiver of a link device. 15. The apparatus of claim 13, wherein said filter coeffi
4. The method of claim 1, wherein said two communicating cient values in said second communicating device comprise
devices comprise a link partner and a link device. parameter values of a decision feedback equalizer in a
receiver of a link device.
5. The method of claim 1, wherein said predefined stopping
criteria determines whether said first of said two communi 16. The apparatus of claim 13, wherein said two commu
cating devices is overequalized. nicating devices comprise a link partner and a link device.
17. The apparatus of claim 13, wherein said predefined
6. The method of claim 1, further comprising the step of stopping criteria determines whether said first of said two
maintaining said filter coefficient values in said first commu communicating devices is overequalized.
nicating device when said predefined stopping criteria for 18. The apparatus of claim 13, wherein said processor is
said first communicating device is satisfied. further configured to maintain said filter coefficient values in
7. The method of claim 1, further comprising the step of said first communicating device when said predefined stop
presetting decision feedback equalization parameters in said ping criteria for said first communicating device is satisfied.
link device. 19. The apparatus of claim 13, wherein said processor is
8. The method of claim 1, wherein said filter coefficient further configured to preset decision feedback equalization
values comprise coefficient values of a multi-tap filter. parameters in said link device.
9. The method of claim 1, wherein said filter coefficient
20. The apparatus of claim 13, wherein said filter coeffi
cient values comprise coefficient values of a multi-tap filter.
values are determined by including a contribution of only a 21. The apparatus of claim 13, wherein said filter coeffi
main-cursor channel impulse response. cient values are determined by including a contribution of
10. The method of claim 1, wherein said filter coefficient only a main-cursor channel impulse response.
values are determined by including a contribution of only a 22. The apparatus of claim 13, wherein said filter coeffi
main-cursor, a first post-cursor and a first pre-cursor channel cient values are determined by including a contribution of
impulse response. only a main-cursor, a first post-cursor and a first pre-cursor
11. The method of claim 1, wherein said filter coefficient channel impulse response.
values are determined by including a contribution of a main 23. The apparatus of claim 13, wherein said filter coeffi
cursor, a first pre-cursor and at least one post-cursor channel cient values are determined by including a contribution of a
impulse response. main-cursor, a first precursor and at least one post-cursor
channel impulse response.
12. The method of claim 1, further comprising the step of 24. The apparatus of claim 13 further comprising a register
obtaining one or more programmable profile values from a for storing one or more programmable profile values, wherein
register, wherein said one or more programmable profile val said one or more programmable profile values indicate cursor
ues indicate cursor tap values that contribute to said filter tap values that contribute to said filter coefficient values.
coefficient values. 25. The apparatus of claim 13, wherein said apparatus is a
13. An apparatus for joint adaptation of filter coefficient physical medium dependent block in a link device.
values in two communicating devices, said apparatus com
prising: c c c c c