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Phím trả lời
1. b) a server / storage 2. c) 4MHz, 6MHz, 8MHz 3. c) Improve the system
performance and
reduce the
manufacturing costs
4. a) JUMP, CALL, RETURN, 5. a) 4 6. b) CD-RW drive
BRANCH-IF-
CONDITION
7. b) look aside and 8. a) status of the result 9. c) High performance,
look through High
reliability, Large volume
10. c) 1 11. a) Cache usually resides 12. b) stack
inside the CPU
13. b) Serial 14. a) FDD, HDD, SSD, DVD, 15. d) Disk drive
RAID, NAS, SAN
16. a) current executed 17. c) Indirect mapping 18. b) 1.5Gb/s
19. b) two 20. b) Peripheral 21. d) loop
Component
Interconnect
22. c) Disks, heads, tracks, 23. a) Mechanical mouse, 24. a) Non-volatile
memory,
sectors, cylinders Optical mouse, Laser semiconductor
memory,
mouse read only memory
25. b) R3 <- R2 + R1 26. c) 700MB and 4.7GB 27. c) Network Attached
Storage
28. b) CD-ROM, CD-R, CD- 29. b) Indirect 30. d) Synchronous DRAM
RW, DVD-ROM, DVD-
R,
DVD-RW
31. a) Hit is slow 32. d) the top 33. c) R1 <- R2 - R3
34. d) pits and lands 35. b) disk / RAM 36. a) a partition
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37. a) Input data and 38. d) ROM and RAM 39. b) ADD, SUBTRACT,
Control
MULTIPLY, DIVIDE
40. a) Volatile memory, 41. d) M[1000] <- M[R1] 42. b) Tag, Line, Word
semiconductor memory,
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random access
memory
43. a) Higher accessing 44. c) Beam sensor 45. b) memory address of
speed, Less power next instruction
consumption, More
compact in size
46. b) Increase cache 47. a) Immediate, 48. a) ISA, EISA, PCI,
block size, Direct, Indexed, AGP, PCIe
Increase cache Relative
associative level
49. a) temperature 50. c) Partition table, boot 51. c) Backlit and
sector, file system, Reflective
and electricity
root directory
52. c) an electron beam 53. d) 16 and 32 54. c) spatial locality and
temporal locality.
55. c) instruction operands 56. c) Instruction fetch 57. b) Data conflict
cycle,
Memory read cycle,
Peripheral read cycle,
Bus read cycle
58. b) SAS, SATA, M.2, U.2, 59. d) parallel processing 60. c) IF, ID, EX, MEM, WB
PCle and multi-core CPU
systems.
61. b) one / simultaneous 62. a) SRAM, DRAM. 63. a) very fast, small in
size, high cost per
bit
64. c) Delayed branching, 65. b) symmetric structure 66. c) execution signal
Branch prediction
67. d) PC 68. a) internal memory 69. c) Instructions are
and peripheral saved from CPU to
devices. memory after
execution.
70. a) registers, cache. 71. a) Disk drive 72. d) CD-R drive
73. a) resource conflicts, 74. c) functionality, 75. a) scan
data conflicts and performance and
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branching cost
instructions.
76. c) Complicated, fast and 77. b) MAR and MBR are 78. b) 2, 2 and 4.
flexible mapping interfaces between
the
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CPU and system bus.
79. d) ABH master, ABH 80. d) 8, 16, 32, 64 81. a) Complicated, slow
slave, PCI arbiter, PCI and flexible
interface mapping
82.c) addresses of operands. 83. c) a flip-flop / a 84. c) Accelerated Graphics
capacitor.
Port
85.c) a network of servers 86. a) 6, 8, 10 87. b) Non-volatile, mass
storage, based on
magnetic principles
88.b) Bootstrap loader 89. a) A bus, C bus and D 90. b) Memory addressing
bus
91.a) PC, IR, MBR, A, Y, Z 92. b) Data conflict 93. c) Arbitration,
Address, Data
94.a) data movement group, 95. b) HDD, SSD, RAM, 96. a) PATA, SATA, SCSI, SAS
computational group, Cache, Registers
conditional and
branching
97.d) intermediary 98. b) Compulsory misses, 99. d) Because DRAM uses
Capacity misses, Conflict less transistors per
misses memory cell than
SRAM
100.b) data word length. 101. b) period of time 102. d) 4GB/s, 8GB/s, 16GB/s
103.a) Very fast, small in 104. b) Thin Film Transistors 105. d) short pipelines.
number and size
106. d) Typewriter-derived, 107. a) 6 Gb/s 108. c) LIFO
Dot- matrix, Laser,
Inkjet
109.a) solid-state flash 110. c) closed neighbours / 111. d) Tag, Set, Word
memory chips near future
112.c) Flash memory, 113. a) IR 114. b) Electrode charger for
Controller, Cache, drum, Electrode
charger
Connection interface for paper, Drying
drum,
Paper tray
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115.c) Because it can balance116. b) system performance / 117. b) Magnetic memory
the speed of CPU and manufacturing costs
main memory better.
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118. a) Passive matrix and 119. b) Relative 120. d) access types,
Active matrix information
sustainability,
manufacturing
technologies.
121. b) system bus / at the 122. c) Because cache can 123. a) CU, ALU,
Registers
same time. predict the need of
instruction and data
of CPU.
124. a) Disk striping, Disk 125. c) 4 126. c) a
mirroring subsystem /
component
s
127. b) Disk mirroring 128. b) CPU 129. a) electronic
imaging
130. b) input and output 131. c) Direct 132. b) Cache balances
the
fast speed of CPU
and the slow speed
of main memory.
133. c) Random 134. a) server 135. b) 3
136. a) RAID 0, RAID 2, RAID 137. c) AX, BX, CX, DX 138. b) Redundant Array
4, RAID 6 of Independent
Disks
139. c) standard 140. a) split L1 cache 141. d) data items
input / into I- Cache and and
standard D-Cache instructions
output
142. c) Laser diode, beam 143. b) Immediate 144. a) Branching
conflict
splitter, laser sensor,
rotation mirror
145. c) macroarchitecture. 146. d) F1, F3, F5, F9, F11 147. d) 1.5
148. c) CPU and external 149. d) An execution stage 150. a)
may Indexed
consist of some
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execution
phases.
151. b) System 152. d) electron 153. a) Simple, fast and
interconnects and beam /
fixed mapping
CPU off-load phosphor
mechanisms.
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154. c) ROM is only used 155. không có 156. không có
to store
instructions while
RAM is only used to
store instructions
and
data.
không
1 có 158.c) binary word 159.
a) 2, 1, 1.5 and 0.
b)1Cache size, cache split, 161.a) peripheral 162.
a) 8
multi-level cache
163. b) RAID 0 164. b) computer 165. c) 3
components and
their working
methodologies.
166. b) NOT, AND, OR, XOR 167. a) Because electric 168. a) Indirect
charge
in the capacitor of
DRAM bits is leaking
by nature.
169. c) RAID 1 170. a) Disk striping 171. b) Registers, ROM, RAM,
Cache,
External
storages.
172. b) Address format 173. a) Ri <- M[X+PC] 174. c) CF, OF, AF, ZF
175. b) insert NO-OP 176. c) Direct 177. b) communication
instructions into channel of all bus
the position components
between 2
instructions that
have RAW.
178. b) If two system have 179. a) status flags, control 180. a) CU, ALU, Registers
the same flags
performance, the
system with cache is
cheaper
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181. c) MBR, CU 182. a) PC, address bus 183. d) MAR gets
memory
address of next
instruction from IR
and forwards it to
address bus
184. d) Solid-State Drive 185. c) Binary 186. b) Control
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187. b) the computer / 188. d) PS/2, COM, LPT, 189. c) ADD, SUB, DIV,
peripheral USB, HDMI MUL, SHR, ROL
devices.
190. d) CLK, IR, ALU flags 191. c) M[A] ← M[B] + M[C] 192. b) individual data items /
data blocks
193. a) each stage / a 194. c) SRAM, Cache 195. a) ROM, RAM, SSD
CPU component. controller, Tag
Ram
196. b) FAT, NTFS, Ext2, Ext4 197. c) accessed again in 198. d) CRT, LCD, Plasma
near
future
199. d) found / not found 200. d) Volatile memory 201. d) Photosensitive drum,
Laser light source,
Rotating mirror and
laser modulator,
Toner cartridge
202.d) PROM, EPROM, 203. d) Registers, 20 c) Thinner and
4
EEPROM, Flash Cache, ROM, lighter, consume
.
memory RAM, HDD less power, larger
viewable size
205. b) MOVE, LOAD, STORE,206. a) Instruction set 20
b) Level 1
7
PUSH. architecture,
.
Microarchitecture,
System Design.
208.a) 3 Gb/s 209.a) 1.5 Gb/s 21
c) 16
0
.
c)2ZF 212.d) ZF 21
c) 250MB/s, 500MB/s,
3
1GB/s
.
214.b) LRU 215. a) each block is / a
separate disk
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