OBJECTIVE

 Study the Architecture of 8086 Microprocessor

 Write 8086 Assembly Language Programs

2-Feb-23 1
used to write a program for a microcomputer
1. Machine Language
 Binary form of program (Instructions / data in1’ and 0’s form)
 Difficult for programmer to memorize
 Error occurs easily
2. Assembly Language
 More readable form of machine language
 Uses mnemonic codes
 Assembler needed to translate to machine code
3. High Level Language
 Uses English-like program statements
 Programs can usually be written faster & easily
 Compiler needed to translate high-level language statement to
machine code
 Executed slowly ; Require more memory
Introduction to 8086 (continued.....) 2-Feb-23 2
1. Fetch 2. Decode

3. Execute

Introduction to 8086 (continued.....) 2-Feb-23 3

 Features
 16-bit microprocessor , most of instructions are designed to
work with 16 bit binary words
 Data bus : 16 bit (read data from or write data to memory
and ports either 16 bits or 8 bits at a time
 Address bus : 20 bit (can address upto 220=1048576 = 1MB
memory locations). [Address range : 00000H to FFFFFH]
 It provides 14, 16-bit registers.
 It has multiplexed Address and Data bus AD0- AD15 and
A16 – A19.

8086 Architecture (continued…) 2-Feb-23 4

 Has ‘Look ahead’ feature to increase the
throughput. (i.e) It can prefetch upto 6 bytes from
memory and queues them in order to speed up
instruction execution.
 40 pin dual in line package
 Supply Voltage: +5V ; Clock Speed: 5MHz, 8MHz,
10MHz
 8086 is designed to operate in two modes,
Minimum and Maximum.

8086 Architecture (continued…) 2-Feb-23 5

8086 Architecture (continued…) 2-Feb-23 6
 The 8086 has two parts:
 the Bus Interface Unit (BIU)
Fetches instructions,
Reads and Writes data, and
computes the 20-bit address for memory operands
Transfers instruction bytes into the 6 byte FIFO queue

the Execution Unit (EU)

Decodes and
Executes the instructions using the 16-bit ALU.

Both units operate asynchronously to give the 8086 an

overlapping instruction fetch and execution mechanism
which is called as Pipelining.
8086 Architecture (continued…) 2-Feb-23 7
 BIU Registers CS Code Segment
DS Data Segment
ES Extra Segment
SS Stack Segment
IP Instruction Pointer

EU AX AH AL Accumulator
Registers BX BH BL Base Register
CX CH CL Count Register
DX DH DL Data Register
SP Stack Pointer
BP Base Pointer
SI Source Index Register
DI Destination Index Register
Flags Flag Register
8086 Architecture (continued…) 2-Feb-23 8
In total there are Fourteen 16-bit registers in an 8086

8086 Architecture (continued…) 2-Feb-23 9

Registers
– Registers are in the CPU and are referred to by specific names
– Data registers
• Hold data for an operation to be performed
• There are 4 data registers (AX, BX, CX, DX)
– Address registers
• Hold the address of an instruction or data element
• Segment registers (CS, DS, ES, SS)
• Pointer registers (SP, BP, IP)
• Index registers (SI, DI)
– Status register
• Keeps the current status of the processor
• The status register is called the FLAG register

8086 Architecture (continued…) 2-Feb-23 10

• Instructions execute faster if the data is in a
register
• Data Registers are general purpose registers but
they also perform special functions
• AX, BX, CX, DX are the data registers
• Low and High bytes of the data registers can be
accessed separately
– AH, BH, CH, DH are the high bytes
– AL, BL, CL, DL are the low bytes
8086 Architecture (continued…) 2-Feb-23 11
 AX
– Accumulator Register
– Used in Arithmetic, Logic and Data Transfer instructions
– Used in Multiplication and Division operations
– Used in I/O operations
 BX
– Base Register
– Also serves as an address register
– Used in array operations
– Used in Table Lookup operations (XLAT)
 CX
– Count register
– Used as a Loop Counter
– Used in shift and rotate operations
 DX
– Data register
– Used in Multiplication and Division
– Also used in I/O operations
8086 Architecture (continued…) 2-Feb-23 12
• Contains the offset addresses of memory locations
• Can also be used in Arithmetic and other operations
• SP: Stack pointer
– Used with SS to access the stack segment
• BP: Base Pointer
– Primarily used to access data on the stack
– Can be used to access data in other segments

8086 Architecture (continued…) 2-Feb-23 13

• SI: Source Index register
– is required for some string operations
– SI is associated with the DS in string operations.
 DI: Destination Index register

– is also required for some string operations.

– DI is associated with the ES in string operations.

The SI and the DI registers may also be used to access data

stored in arrays

8086 Architecture (continued…) 2-Feb-23 14

• Are Address registers
• Stores the memory addresses of instructions and data
• Memory Organization
– 20 bit address line addresses 1 MB of memory
– Each byte in memory has a 20 bit address
– Addresses are expressed as 5 hex digits from 00000 - FFFFF
– Problem: 20 bit addresses are TOO BIG to fit in 16 bit registers!
– Solution: Memory Segment
• A segment number is a 16 bit number
• Segment numbers range from 0000 to FFFF
• Block of 64K (65,536) (i.e 216)consecutive memory bytes
• Within a segment, a particular memory location is specified with
an offset
• An offset also ranges from 0000 to FFFF
8086 Architecture (continued…) 2-Feb-23 15
 Memory space is divided into overlapping segments
 Each segment is of 64 Kbytes
 Segment address begins at an address that is divisible by
1610 or 1016
 Segment register contains the starting address of a segment.
 16 bit words will be stored in two consecutive memory
locations.
If first byte of the data is stored at an even address, 8086
reads the entire word in one operation.
Example if the 16 bit data 2607H is stored at even
address 00520H, then for instruction MOV BX, [00520],
8086 reads the first byte and stores the data in BL and
reads the second byte and stores the data in BH.
BL  (00520) BH (00521)
8086 Architecture (continued…) 2-Feb-23 16
If the first byte of data is stored at an odd address,
8086 needs two operation to read the 16 bit data.
Example if the 16 bit data F520H is stored at odd
address 00521H, then for instruction MOV BX,
[00521],
In first operation, 8086 reads the 16 bit data from the
00520 location and stores the data of 00521 location in
register BL and discards the data of 00520 location.
In second operation, 8086 reads the 16 bit data from
the 00522 location and stores the data of 00522 location
in register BH and discards the data of 00523 location.

8086 Architecture (continued…) 2-Feb-23 17

 1MB Memory Space divided into
non-overlapping segments
64 KB

00000 20000

Seg-1 Seg-3 Seg-5 Seg-7 Seg-15

0FFFF 2FFFF
          
10000 EFFFF

Seg-2 Seg-4 Seg-6 Seg-8 Seg-16

1FFFF FFFFF

8086 Architecture (continued…) 2-Feb-23 18

 1 MB Memory Space

F0000
Starting Address of each segment

E0000
5000:FFFF
D0000
C0000
B0000
A0000
90000
80000 5000:0250
70000
60000
50000 5000:0000
40000
SegAddr:Offset
30000
20000
10000
00000
8086 Architecture (continued…) 2-Feb-23 19
 The BIU has a dedicated adder for determining
Physical memory addresses

Offset Value or Effective address (16 bits)

Segment Register (16 bits) 0 0 0 0

Adder

Physical Address (20 Bits)

8086 Architecture (continued…) 2-Feb-23 20

• Logical Address is specified as Segment:Offset
• Physical address is obtained by shifting the segment
address 4 bits to the left and adding the offset address
• Thus the physical address of the logical address A4FB:4872
is
A4FB0  1010 0100 1111 1011 0000
+ 4872  0100 1000 0111 0010
A9822 1001 1001 1000 0010 0010

8086 Architecture (continued…) 2-Feb-23 21

Overlapping segments

8086 Architecture (continued…) 2-Feb-23 22

8086 Architecture (continued…) 2-Feb-23 23
 Carry flag
Overflow flag
Parity flag
Direction flag
Interrupt enable Auxiliary flag
Trap flag Zero flag
6 - status flags
3 - control flags Sign flag

8086 Architecture (continued…) 2-Feb-23 24

• Status or Conditional flags:
– These are set according to the results of the
arithmetic or logic operations.
– Need not be altered by the user.

• Control flags:
– Used to control some operations of the MPU.
– These flags are to be set by the user, in order to
achieve some specific purposes.

8086 Architecture (continued…) 2-Feb-23 25

 CF (carry) Contains carry from leftmost bit following
arithmetic, also contains last bit from a shift or rotate
operation.
 PF (parity) Indicates the number of 1 bits that result from an
operation.(1=even)
 AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for
specialized arithmetic (BCD).
 ZF (zero) Indicates when the result of arithmetic or a
comparison is zero. (1=yes)
 SF (sign) Contains the resulting sign of an arithmetic
operation (1=negative)
 OF (overflow) Indicates overflow of the leftmost bit during
arithmetic.

8086 Architecture (continued…) 2-Feb-23 26

 DF (direction) Indicates left or right for moving or
comparing string data.

 IF (interrupt) Indicates whether external interrupts are

being processed or ignored.

 TF (trap) Permits operation of the processor in single step

mode.

8086 Architecture (continued…) 2-Feb-23 27

 Assume that the previous instruction performed the
following addition,

0010 0011 0100 0101 SF= 0 ZF= 0 AF= 0

0011 0010 0001 1001
0101 0101 0101 1110 PF= 0 CF= 0 OF= 0

0101 0100 0011 1001 SF= 1 ZF= 0 AF= 1

0100 0101 0110 1010
1001 1001 0101 0011 OF= 0
PF= 1 CF= 0

8086 Architecture (continued…) 2-Feb-23 28

 Various methods used to access instruction operands
is called as Addressing Mode

 General Instruction Format

OPCODE Operand  Operand

 Operands may be contained in

 Registers,
 Memory
 I/O ports.
 Three basic modes of addressing are
 Immediate
 Register
 Memory

Addressing Modes 2-Feb-23 29

 8086 Addressing modes - classified according to
flow of instruction execution
A. Sequential flow instructions
 Arithmetic
 Logical
 Data transfer
 Processor control
B. Control transfer instructions
 INT
 CALL
 RET
 JUMP

Addressing Modes (continued...) 2-Feb-23 30

A. Sequential flow instructions
1. Implied Addressing mode
2. Immediate addressing mode
3. Direct addressing mode
4. Register addressing mode
5. Register Indirect addressing mode
6. Indexed addressing mode
7. Register Relative addressing mode
8. Based Indexed addressing mode
9. Relative Based Indexed addressing mode
B. Control transfer instructions
1. Intersegment Direct addressing mode
2. Intersegment Indirect addressing mode
3. Intra segment Direct addressing mode
4. Intra segment Indirect addressing mode

Addressing Modes (continued...) 2-Feb-23 31

1. Implied Addressing - The data value/data
address is implicitly associated with the
instruction.
◦ AAA
◦ AAS
◦ AAM
◦ AAD
◦ DAA
◦ DAS
◦ XLAT

Addressing Modes (continued...) 2-Feb-23 32

2. Immediate Addressing – Data / operand is part
of the instruction Destination
Source

MOV AX, 25BF ; [ AX25BF H ] 16 Bit Data

MOV AL, 8EH ; [ AL8E ] 8 Bit Data

3. Direct Addressing – Data is pointed by 16 bit

offset value specified in the instruction
MOV AX, [5000H] ;
Effective Addr = 5000
PhyAddr = 10H*DS + 5000H

Addressing Modes (continued...) 2-Feb-23 33

4. Register Addressing – Data is in the register
specified in the instruction

MOV BX, AX No PhyAddr, since data is in regr

16 BIT Operand Registers - AX, BX, CX,DX, SI, DI, SP, BP

8 BIT Operand Registers - AL, AH, BL, BH, CL, CH, DL, DH

Addressing Modes (continued...) 2-Feb-23 34

5. Register Indirect Addressing – Data is pointed by
the offset value in the register, specified in the
instruction

MOV AX, [BX] Default Segment - DS or ES

Offset – BX or SI or DI

DS BX
PhyAddr = 10H *
ES
+ SI
DI
If DS=5000H; BX=10FF;
Then EffectiveAddr = 10FF
and PhyAddr = 10H*5000H + 10FFH = 510FFH

Addressing Modes (continued...) 2-Feb-23 35

6. Indexed Addressing
 Data is pointed by the offset in the index register
specified in the instruction
 DS is the default segment register for SI and DI

MOV AX, [SI] Data is available in the logical

address [DS:SI]
Effective Addr = [SI]
SI
PhyAddr = 10H * DS + DI

Addressing Modes (continued...) 2-Feb-23 36

7. Register Relative Addressing
 Data is pointed by the sum of 8 bit or 16 bit
displacement specified in the instruction plus
 Offset specified in the registers –BX, BP, SI, DI
 Default segment registers – DS, ES

MOV AX, 50H [BX]

EffectiveAddr = 50H+[BX]
BX
DS BP
PhyAddr = 10H * ES +
SI
DI

Addressing Modes (continued...) 2-Feb-23 37

8. Based Indexed Addressing
 Data is pointed by content of base register specified
in the instruction plus
 Content of index register specified in the
instruction
 Default segment registers – DS, ES

MOV AX, [BX] [SI]

BX SI
EffectiveAddr = BP + DI

DS BX SI
PhyAddr = 10H * ES
+ BP
+ DI

Addressing Modes (continued...) 2-Feb-23 38

9. Register Relative Addressing
 Data is pointed by the sum of 8 bit or 16 bit
displacement specified in the instruction plus
 Offset specified in the base registers –BX, BP plus
 Offset specified in the index registers – SI, DI
 Default segment registers – DS, ES

8 bit BX SI
EffectiveAddr = 16 bit + BP + DI

DS 8 bit BX SI
PhyAddr = 10H * ES +
16 bit
+ BP + DI

Addressing Modes (continued...) 2-Feb-23 39

 Intrasegment Direct Addressing –
 Control transfer instruction and
 Address where control is transferred lies in the same
segment
 Immediate displacement value specified in instruction
 Displacement is w.r.t IP register content
 Short jump – 8 bit signed displacement ‘d’
i.e (-27 < d < +27-1) = (-128 < d < +127 )
= (-80H < d < +7FH )
 Long jump – 16 bit signed displacement ‘d’
 i.e (-215 < d < +215 ) = (-32768 < d < + 32768 )
 Example: JMP SHORT LABEL
LABEL lies within (-128 to +127 ) from the current IP
content

Addressing Modes (continued...) 2-Feb-23 40

Intrasegment Direct Addressing –

 Short Jump or Code Segment

CS: 3000H
 Near Jump IP: 0000H
 The jump destination is
in the same code CS: 3000H JMP NEXT
IP: 0010H
segment
 To execute the jump, CS: 3000H
only the contents of NEXT: INC BX
IP: 0020H
Instruction Pointer (IP)
register needs to be
changed

Addressing Modes (continued...) 2-Feb-23 41

 Intrasegment Indirect Addressing –
 Control transfer instruction and
 Address where control is transferred lies in the same
segment
 Displacement value specified indirectly – as content of
a register or a memory location in the instruction
 Used in unconditional instructions

 Example: JMP [BX]

EffectiveAddr = [BX]
PhyAddr = 10H*[CS]+[BX]

Addressing Modes (continued...) 2-Feb-23 42

Intrasegment Indirect Addressing
Code Segment
6FFFF BX = 75ABH
CS = 6000H

675AB
Effective Addr = [BX]
MOV AX, BX
PhyAddr = 10H*[CS]+[BX]

61000 JMP [BX] Displacement from current location:

675AB - 61000 = +65AB H= +2602710
60000

Addressing Modes (continued...) 2-Feb-23 43

 Intersegment Direct Addressing –
 Control transfer instruction and
 Address where control is transferred lies in the
different segments
 Branching from one code segment to another code segt
 CS and IP of destination address are specified in
instruction
 Example: JMP 5000H: 2000H
EffectiveAddr = 2000H
PhysicalAddr = 10H * 5000H + 2000H = 52000H

Addressing Modes (continued...) 2-Feb-23 44

 Intersegment Direct Addressing
Code Segment A
 Long Jump or Far Jump CS: 3000H
IP: 0000H

 The jump destination is in CS: 3000H

IP: 0010H JMP NEXT
a different code segment

 To execute the jump, 8086 Code Segment B

has to change the contents CS: 6000H
of Code Segment (CS) IP: 0000H
register and IP register
CS: 6000H
NEXT: INC BX
IP: 0050H

Addressing Modes (continued...) 2-Feb-23 45

 Intersegment Indirect Addressing –
 Control transfer instruction and
 Address where control is transferred lies in the
different segments
 Branching from one code segment to another code segt
 CS and IP of destination address are specified
indirectly in the instruction
 Starting address of a memory block specified in instn
(i.e) content of a memory block containing 4 bytes
IP(LSB), IP(MSB), CS(LSB), CS(MSB)
 Example: JMP [2000H]
EffectiveAddr = 2000H
PhysicalAddr = 10H * DS + 2000H

Addressing Modes (continued...) 2-Feb-23 46

Intersegment Indirect Addressing
DS = 6000H
6FFFF 7FFFF

MSB LSB

74466 IP 44 66

CS 70 00
62003 70H
62002 00H
62001 44H
62000 66H

60100 JMP [2000H]

60000 70000

Addressing Modes (continued...) 2-Feb-23 47

1. Data Copy / Transfer Instructions
2. Arithmetic Instructions
3. Logical Instructions
4. Shift and Rotate Instructions
5. String Manipulation Instructions
6. Branch and Loop Instructions
5. Flag Manipulation Instructions
6. Machine Control Instructions

Instruction Set (continued...) 2-Feb-23 48

1. DATA TRANSFER INSTRUCTIONS

 Transfers data from one register or memory

location to another register or memory location

 Source: Seg.Register /
Gen.Register /Mem.location
 Destination: Seg.Register /
Gen.Register /Mem.location
 Note: Both Source and
Destination cannot be
Mem.Locn

Instruction Set (continued...) 2-Feb-23 49

 General purpose byte or word transfer instructions
MOV Copy byte or word from specified source to specified
destination
PUSH Copy specified word to top of stack
POP Copy word from top of stack to specified
location
XCHG Exchange bytes or exchange words
XLAT Translate a byte in AL using a table in
memory
Simple input and output port transfer instructions
IN Copy a byte or word from specified port to
accumulator
OUT Copy a byte or word from accumulator to
specified port
Instruction Set (continued...) 2-Feb-23 50
 Special address transfer instructions:
LEA Load effective address of operand into specified
register
LDS Load DS register and other specified register from
memory
LES Load ES register and other specified register from
memory
Flag transfer instructions
LAHF Load (copy to ) AH with the low byte of the flag
register
SAHF Store (copy) AH register to low byte of flag
register
PUSHF Copy flag register to top of stack
POPF Copy word at top of stack to flag register
Instruction Set (continued...) 2-Feb-23 51
Instruction Comments
MOV DS, 5000H Not Valid; immediate addressing with
segment registers not permitted

MOV AX, 5000H; Immediate addressing

MOV DS, AX Register addressing
MOV AX, [2000H] Direct addressing
MOV AX, [SI] Indirect addressing
MOV AX , 50H[BX] Register relative / Indexed addr
• Push Higher Byte AH into the location
PUSH AX pointed by SP and Push Lower Byte AL
PUSH DS into the location pointed by SP-1;
PUSH [5000H] SPSP-2
• Content of loc. 5000H followed by
5001H in DS are pushed into the stack
Instruction Set (continued...) 2-Feb-23 52
 Do not click the mouse to see the full animation

*Knowing that,
DS=2042H.
SI=500H, AH AL
AX=214E, 21 4E
MOV [SI], AX 21 20921H
4E 20920H

SI=500

DS=2042H DS=20420H

Instruction Set (continued...) 2-Feb-23 53

 Physical Address
PUSH AX
Stack Segment

AH AL 20000 SS = 2000
88 44 SP =

44 2FFFB FFFB
88 2FFFC FFFC
XX 2FFFD FFFD
XX 2FFFE FFFE
XX 2FFFF FFFF

Instruction Set (continued...) 2-Feb-23 54

Instruction Comments
• Pops stack top content pointed by SP into
Lower Byte of the register / mem. location
1. POP AX and next byte in the stack into Higher Byte
2. POP DS of the register / mem. location ; SPSP+2
3. POP [5000H] • Content of stack top and next byte in the
stack are popped into 5000H & 5001H in
DS
• Exchanges data b/w AX &
1. XCHG [5000H], AX
2. XCHG BX, AX mem.loc [5000H] in data seg.
•Exchange data b/w AX & BX
1. IN AL, 03H
2. IN AX, DX 03H is 8-bit port address
3. MOV DX, 0800H [DX] is 6-bit port address
IN AX, DX
Instruction Set (continued...) 2-Feb-23 55
 Physical Address
POP AX
Stack Segment

AH AL 20000 SS = 2000
xx
88 xx
44 SP =

44 2FFFB FFFB
88 2FFFC FFFC
XX 2FFFD FFFD
2FFFE FFFE
2FFFF FFFF

Instruction Set (continued...) 2-Feb-23 56

Instruction Comments

1. OUT 03H, AL 1. Send data in AL to a port whose

address is 03H
2. OUT DX, AX 2. Send data in AX to a port whose
3. MOV DX, 0300H address is in DX
OUT DX, AX 3. Send data in AX to a port whose
address is in DX, set as 0300H

Instruction Set (continued...) 2-Feb-23 57

 XLAT called translate instruction.
 The operation of XLAT is to change the value of AL with
the memory pointed to by (AL+BX)

AL Mem[AL+BX]

dddd+mmmm data

AL=dddd

BX=mmmm AL=data

for the example slides do not click the mouse to see the full animation

Instruction Set (continued...) 2-Feb-23 58

 More clearly the XLAT instruction converts the
content of register AL, using a table. Its beginning
address is contained in register BX. The content of
register AL is interpreted as a relative address in the
table.

 XLAT is the only instruction that adds 8 bit number

to 16 bit number!

 XLAT does not Affect the flags..

Instruction Set (continued...) 2-Feb-23 59

Instruction Comments
1. LEA BX, ADR 1. BX  Offset (ADR)
2. LEA SI, ADR[BX] 2. SI  Offset (ADR) + [BX]
3. LDS BX, 5000H 3. BX(LB)  [5000H]
BX(HB)  [5001H]
4. LES BX, 5000H
DS/ES(LB)  [5002H]
DS/ES(HB)  [5003H]

Note: Effective Address is also called as Offset

8086 Instruction Set (continued...) 2-Feb-23 60

Instruction Comments
1. LAHF 1. AH  [Flag (LB)]
2. SAHF 2. Set/Reset all condition code flags except
Overflow flag
3. PUSHF 3. SP  SP-2; for each PUSH operation;
Push FlagRegr(HB) followed by
FlagRegr(LB) into the stack SS:SP
4. POPF 4. SP  SP+2; for each POP operation;
Pop into FlagRegr(LB) followed into
FlagRegr(HB) from stack SS:SP

8086 Instruction Set (continued...) 2-Feb-23 61

1. Data Copy / Transfer Instructions
2. Arithmetic Instructions
3. Logical Instructions
4. Shift and Rotate Instructions
5. String Manipulation Instructions
6. Branch and Loop Instructions
5. Flag Manipulation Instructions
6. Machine Control Instructions

8086 Instruction Set (continued...) 2-Feb-23 62

2. ARITHMETIC INSTRUCTIONS

Performs
 Addition,
 Subtraction,
 Multiplication,
 Division,
 Increment,
 Decrement
along with ASCII and Decimal adjustment

 Operands in : Immediate / Register / Memory locn.

 Note: Flag bits in flag register are affected

8086 Instruction Set (continued...) 2-Feb-23 63

 Addition instructions:
ADD Add specified byte to byte or specified word to
word
ADC Add byte + byte + carry flag (or)
word + word + carry flag
INC Increment specified byte or specified word by 1
AAA ASCII adjust after addition
DAA Decimal (BCD) adjust after addition
Multiplication instructions
MUL Multiply unsigned byte by byte or unsigned word
by word
IMUL Multiply signed byte by byte or signed word by
word
AAM ASCII adjust after multiplication
8086 Instruction Set (continued...) 2-Feb-23 64
 Subtraction Instructions:
SUB Subtract byte from byte or word for word
flag from word.
SBB Subtract byte and carry flag from byte or word ad
carry
DEC Decrement specified byte or specified word by 1
NEG Negate – invert each bit of a specified byte or word
and add 1. (form 2’s complement)
CMP Compare two specified bytes or two specified
words
AAS ASCII adjust after subtraction
DAS Decimal (BCD) adjust after subtraction
8086 Instruction Set (continued...) 2-Feb-23 65
 Division Instructions:
DIV Divide unsigned word by byte or unsigned DW by
word
IDIV Divide signed word by byte or signed DW by word
AAD ASCII adjust before division
CBW Fill upper byte of word with copies of sign bit of
lower byte
CWD Fill upper word of DW with sign bit of lower word

8086 Instruction Set (continued...) 2-Feb-23 66

 • Result is in destination operand
• All the condition code flags are affected
• Content of segment registers cannot be added
• Memory to memory addition not possible
ADD Add
1. ADD AX, 0100H 1. Immediate addressing
2. ADD AX, BX 2. Register addressing
3. ADD AX, [SI] 3. Indexed / indirect addressing
4. ADD AX, [5000H] 4. Direct addressing

5. ADD [5000H], 0100H 5. Immediate addressing

6. ADD 0100H 6. Implicit addressing

(destination AX) &
• Source : Regr / Mem.Locn / immediate
• Destination : Regr / Mem.Locn immediate addressing
8086 Instruction Set (continued...) 2-Feb-23 67
 • Same as ADD instruction
• Adds the carry flag bit with the result.
• All the condition code flags are affected
ADDC Add with carry
1. ADC 0100H 1. Immediate addressing
2. ADC AX, BX 2. Register addressing
3. ADC AX, [SI] 3. Indexed / indirect addressing
4. ADC AX, [5000H] 4. Direct addressing

5. ADC [5000H], 0100H 5. Immediate addressing

6. ADD 0100H 6. Implicit addressing

(destination AX) &
• Source : Regr / Mem.Locn / immediate
• Destination : Regr / Mem.Locn
immediate addressing

8086 Instruction Set (continued...) 2-Feb-23 68

• Register/Mem.content incremented / decremented by 1
• All the condition code flags are affected except CF
• Immediate operand cannot be incremented

INC Increment
1. INC AX 1. Register addressing
2. INC [BX] 2. Register indirect addressing
3. INC [5000H] 3. Direct addressing

DEC Decrement
1. DEC AX 1. Register addressing
2. DEC [BX] 2. Register indirect addressing
3. DEC [5000H] 3. Direct addressing

8086 Instruction Set (continued...) 2-Feb-23 69

• Destn.operand  Destn.operand – Source operand
• All the condition code flags are affected

SUB Subtract
1. SUB AX, 0100H 1. Immediate addressing
2. SUB AX, BX 2. Register addressing
3. SUB AX, [SI] 3. Indexed / indirect addressing
4. SUB AX, [5000H] 4. Direct addressing
5. SUB [5000H], 0100H 5. Immediate addressing

• Source : Regr / Mem.Locn / immediate

• Destination : Regr / Mem.Locn

8086 Instruction Set (continued...) 2-Feb-23 70

• Destn.operand  Destn.operand – (Source operand + CF)
• All the condition code flags are affected

SBB Subtract with borrow

1. SBB AX, 0100H 1. Immediate addressing
2. SBB AX, BX 2. Register addressing
3. SBB AX, [SI] 3. Indexed / indirect addressing
4. SBB AX, [5000H] 4. Direct addressing
5. SBB [5000H], 0100H 5. Immediate addressing

• Source : Regr / Mem.Locn / immediate

• Destination : Regr / Mem.Locn

8086 Instruction Set (continued...) 2-Feb-23 71

• Destn.operand – Source operand
• Result not stored anywhere
• All the condition code flags are affected
• ZF=1(equal); CY=1 (src > destn); CY =0, ZF=0 (src < destn)

CMP Compare
1. CMP AX, 0100H 1. Immediate addressing
2. CMP BX, 0100H 2. Immediate addressing
3. CMP BX, [SI] 3. Indexed / indirect addressing
4. CMP BX, CX 4. Register addressing
5. CMP [5000H], 0100H 5. Direct/Immediate addressing

• Source : Regr / Mem.Locn / immediate

• Destination : Regr / Mem.Locn

8086 Instruction Set (continued...) 2-Feb-23 72

 AAA ASCII Adjust after addition

• Executed after ADD

• ADD must have added two ASCII no’s & result is in AL
• AAA converts AL to unpacked decimal digits(Implicit addressing)
AX AH (8 bits) AL (8 bits)

ALHIGH ALLOW

(1) If 0 < ALLOW < 9 and AF=0, then ALHIGH = 0

(2) If 0 < ALLOW < 9 and AF=1,
then ALLOW = ALLOW +06 and ALHIGH = 0 and AH=AH+1

(3) If ALLOW > 9, then AL=AL+06H and ALHIGH = 0 and

AH=AH+1, ACF=CF= 1

8086 Instruction Set (continued...) 2-Feb-23 73

 DAA Decimal Adjust Accumulator

• Executed after adding two packed BCD numbers

• Converts packed BCD numbers to unpacked BCD no’s
• Result has to be in AL
AX AH (8 bits) AL (8 bits)

(1) If ALLOW > 9 ALHIGH ALLOW

OR
if AF=1, then DAA adds 06H to AL
(2) After adding 06H to AL, if ALHIGH > 9
OR
if CF=1, then DAA adds 60H to AL.

8086 Instruction Set (continued...) 2-Feb-23 74

1. Data Copy / Transfer Instructions
2. Arithmetic Instructions
3. Logical Instructions
4. Shift and Rotate Instructions
5. String Manipulation Instructions
6. Branch and Loop Instructions
5. Flag Manipulation Instructions
6. Machine Control Instructions

8086 Instruction Set (continued...) 2-Feb-23 75

3. LOGICAL INSTRUCTIONS

Logical Instructions:
NOT Logical Invert: Invert each bit of a byte or word
in another byte or word
AND Logical AND: AND each bit in a byte or word with
the corresponding bit
OR Logical OR: OR each bit in a byte or word with the
corresponding bit in another byte or word
XOR Logical XOR: Exclusive OR each bit in a byte or
word with the corresponding bit in another byte or
word
TEST Logical Compare: AND operation to update flags,
[OF, CF, SF, ZF, PF] but don’t change operands

8086 Instruction Set (continued...) 2-Feb-23 76

3. LOGICAL INSTRUCTIONS

Logical Instructions:
NOT NOT AX;
NOT [5000H];
AND AND AX, 0008H;
AND AX, BX;
AND [5000H], DX;
OR OR AX, 0008H;
OR AX, BX;
OR DX, [5000H];
XOR XOR AX, 0098H; XOR AX, BX; XOR AX, [5000H];
TEST TEST AX, BX; TEST [5000H] 06H;
TEST [BX][DI], CX

8086 Instruction Set (continued...) 2-Feb-23 77

1. Data Copy / Transfer Instructions
2. Arithmetic Instructions
3. Logical Instructions
4. Shift and Rotate Instructions
5. String Manipulation Instructions
6. Branch and Loop Instructions
5. Flag Manipulation Instructions
6. Machine Control Instructions

8086 Instruction Set (continued...) 2-Feb-23 78

 4. SHIFT AND ROTATE INSTRUCTIONS
SHIFT INSTRUCTIONS

Shift Instructions (count is either 1 or specified by CL)

SHL/ Shift Left / Shift Arithmetic Left:
SAL Shift bits of byte or word left, put zero(s) in LSB(s).
SHR Shift Right:
Shift bits of byte or word right, put zero(s) in MSB(s).
SAR Shift Arithmetic Right:
Shift bits of word or byte right, copy old MSB into new MSB

8086 Instruction Set (continued...) 2-Feb-23 79

SHL/ SAL Shift bits of byte or word left, put zero(s) in LSB(s)

x0 Carry Flag
MSB LSB
SHL / SAL
1st execution 10 1 01 10 01 0 10 01

1 Carry Flag
MSB LSB
SHL / SAL
2nd execution 1 0 1 0 0 1 0 0

8086 Instruction Set (continued...) 2-Feb-23 80

SHR Shift bits of byte or word right, put zero(s) in MSB(s).

Carry Flag
MSB LSB
0 1 1 0 1 0 0 1 x

SHR 1st execution 0 0 1 1 0 1 0 0 1

SHR 2nd execution 0 0 0 1 1 0 1 0 0

8086 Instruction Set (continued...) 2-Feb-23 81

SAR Shift bits of word or byte right, copy old MSB into
new MSB

Carry Flag
MSB LSB
1 0 1 0 1 0 0 1 x

SHR 1st execution 1 1 0 1 0 1 0 0 1

SHR 2nd execution 1 1 1 0 1 0 1 0 0

8086 Instruction Set (continued...) 2-Feb-23 82

 4. SHIFT AND ROTATE INSTRUCTIONS
ROTATE INSTRUCTIONS

Rotate Instructions (count is either 1 or specified by CL)

ROL Rotate Left without Carry: Rotate bits of byte or word
left, MSB to LSB and to CF
ROR Rotate Right without Carry: Rotate bits of byte or word
right, LSB to MSB and to CF
RCL Rotate Left through Carry: Rotate bits of byte or word
left, MSB to CF and CF to LSB
RCR Rotate Left through Carry: Rotate bits of byte or word
right, LSB to CF and CF to MSB

8086 Instruction Set (continued...) 2-Feb-23 83

ROL Rotate bits of byte or word left, MSB to LSB and to CF
RCL Rotate bits of byte or word left, MSB to CF and CF to LSB

x1
0 Carry Flag

MSB LSB
ROL 10 01 10 01 01 10 01 10
st execution
12nd execution
Carry Flag
1
0
x
MSB LSB
RCL
01 10 01 01 10 x10 0x1 10x
321rd
nd
st execution
execution

8086 Instruction Set (continued...) 2-Feb-23 84

1. Data Copy / Transfer Instructions
2. Arithmetic Instructions
3. Logical Instructions
4. Shift and Rotate Instructions
5. String Manipulation Instructions
6. Branch and Loop Instructions
5. Flag Manipulation Instructions
6. Machine Control Instructions

8086 Instruction Set (continued...) 2-Feb-23 85

 5. STRING MANIPULATION INSTRUCTIONS
String Instructions
REP An instruction prefix. Repeat following
instruction until CX=0
REPE/REPZ Repeat while equal/zero
REPNE/REPNZ Repeat while not equal/zero
MOVX/MOVSB/ Move byte or word from one string to another
MOVSW
COMPS/COMPSB/ Compare two string bytes or two string words
COMPSW
SCAS/SCASB/ Scan a string. Compare a string byte with a byte
SCASW in AL or a string word with a word in AX
LODS/LODSB/ Load string byte into AL or string word into AX
LODSW
STOS/STOSB/STOSW Store byte from AL or word from AX into string
8086 Instruction Set (continued...) 2-Feb-23 86
1. Data Copy / Transfer Instructions
2. Arithmetic Instructions
3. Logical Instructions
4. Shift and Rotate Instructions
5. String Manipulation Instructions
6. Branch and Loop Instructions
5. Flag Manipulation Instructions
6. Machine Control Instructions

8086 Instruction Set (continued...) 2-Feb-23 87

6. BRANCH AND LOOP INSTRUCTIONS

1. Unconditional Branch Instructions

2. Conditional Branch Instructions
3. Loop Instructions

Unconditional Branch Instructions:

CALL Call a procedure (subprogram), save return
address on stack
RET Return from procedure to calling program
JMP Go to specified address to get next instruction

8086 Instruction Set (continued...) 2-Feb-23 88

 Conditional Branch Instructions
JA/JNBE Jump if above/ jump if not below or equal
JAE/JNB Jump if above or equal/ jump if not below
JB/JNAE Jump if below/ jump if not above or equal
JC Jump if carry =1
JBE/JNA Jump if below or equal/ jump if not above
JE/JZ Jump if equal/ jump if zero
JG/JNLE Jump if greater/ jump if not less than or equal
JGE/JNL Jump if greater than or equal/ jump if not less than
JL/JNGE Jump if less than/ jump if not greater than or equal
JLE/JNG Jump if less than or equal/ jump if not greater than
JNC Jump if no carry
JNE/JNZ Jump if not equal/ jump if not zero
8086 Instruction Set (continued...) 2-Feb-23 89
 Conditional Branch Instructions
JNO Jump if no overflow
JNP/JPO Jump if not parity/ jump if parity odd (PF = 0)
JNS Jump if not sign
JO Jump if overflow
JP/JPE Jump if parity/ jump if parity even
JS Jump if sign
Interrupt Instructions:
INT Interrupt program execution, call service
procedure
INTO Interrupt program execution if OF=1
IRET Return from interrupt service procedure to
main program
8086 Instruction Set (continued...) 2-Feb-23 90
 Loop Instructions
LOOP Loop through a sequence of
instructions until CX=0
LOOPE/LOOPZ Loop through a sequence of
instruction while ZF=1 and CX !=0
LOOPNE/LOOPNZ Loop through a sequence of
instruction while ZF=0 and CX!=0.
JCXZ Jump to specified address if CX=0.

8086 Instruction Set (continued...) 2-Feb-23 91

1. Data Copy / Transfer Instructions
2. Arithmetic Instructions
3. Logical Instructions
4. Shift and Rotate Instructions
5. String Manipulation Instructions
6. Branch and Loop Instructions
7. Flag Manipulation Instructions
8. Machine Control Instructions

8086 Instruction Set (continued...) 2-Feb-23 92

7. FLAG MANIPULATION INSTRUCTIONS

Flag Manipulation Instructions:

STC Set carry flag
CLC Clear carry flag
CMC Complement the status of carry flag
STD Set direction flag
CLD Clear direction flag
STI Set interrupt enable flag (enable INTR)
CLI Clear interrupt enable flag (disable INTR)

8086 Instruction Set (continued...) 2-Feb-23 93

1. Data Copy / Transfer Instructions
2. Arithmetic Instructions
3. Logical Instructions
4. Shift and Rotate Instructions
5. String Manipulation Instructions
6. Branch and Loop Instructions
7. Flag Manipulation Instructions
8. Machine Control Instructions

8086 Instruction Set (continued...) 2-Feb-23 94

8. MACHINE CONTROL INSTRUCTIONS

Machine Control Instructions:

HLT Halt until interrupt or reset
WAIT Wait until signal on the TEST pin is low
LOCK An instruction prefix.
Prevents another processor from taking the bus
while the adjacent instruction executes
NOP No action except fetch and decode

8086 Instruction Set (continued...) 2-Feb-23 95

Hints given to the assembler using predefined alphabetical
strings to correctly understand the assembly language
programs and prepare machine codes – called as
ASSEBLER DIRECTIVES

Hints given to the assembler

1. to assign a particular constant with a label or
2. Initialize particular memory locations or labels with
constants - Called as OPERATORS
- OPERATORS perform arithmetic and logical tasks.

Assembler Directives (continued...) 2-Feb-23 96

 ASSEMBLER DIRECTIVES USED IN
MICROSOFT MACRO ASSEMBLER OR TURBO ASSEMBLER

DIRECTIVES
1.DB Define Byte
2. DW Define Word
3. DQ Define Quadword
4. DT Define Ten Bytes
5. END End of Program
6. ENDP End of Procedure
7. ENDS End of Segment
8. ASSUME Assume Logical Segment Name
9. SEGMENT Logical segment

Assembler Directives (continued...) 2-Feb-23 97

 DIRECTIVES (continued….)
10. EQU Equate
11. EVEN Align on even memory address
12. EXTRN and External and Public
PUBLIC
13. LOCAL Local
14. GLOBAL Global
15. GROUP Group the related segments
16. LABEL Label
17. LENGTH Byte length of a label
18. NAME Logical name of a module
19. ORG Origin
20. PROC Procedure
Assembler Directives (continued...) 2-Feb-23 98
 OPERATORS USED IN
MICROSOFT MACRO ASSEMBLER OR TURBO ASSEMBLER
DIRECTIVES (continued….)
21. FAR PTR Near pointer
22. NEAR PTR Far pointer
OPERATORS
1.OFFSET Offset of a label
2. PTR Pointer
3. SEG Segment of a label
4. SHORT Short
5. ‘+ and -’ Addition and subtraction operators
6. TYPE Type

Assembler Directives (continued...) 2-Feb-23 99

 DIRECTIVES
1.DB DB directive is used to reserve bytes or bytes
of memory location , with data type that
may be a
-Constant
-Variable
-String etc

Example - 1
PRICE DB 49h, 98h, 29h ; Directs assembler to -
reserve an array of 3 bytes named as PRICE and initialize.

Assembler Directives (continued...) 2-Feb-23 100

Example - 2
MESSAGE DB ‘GOOD MORNING’;
Reserve an array of bytes equal to the number of
characters in the string named as MESSAGE and
initialize by the ASCII equivalent of these characters

Example – 3
TEMP DB 100 DUP(?) ;
Set 100 bytes of storage in memory and give it the name
as TEMP, but leave the 100 bytes uninitialized.
Program instructions will load values into
these locations.
DUP - Duplicates

Assembler Directives (continued...) 2-Feb-23 101

 DIRECTIVES
2. DW DW directive is used to reserve words (16
bits) or words of memory location , with
data type that may be a
-Constant
-Variable
-String etc

Example - 1
WORDS DW 4987h, 1F98h, AB29h ;
Directs assembler to reserve an array of 3 Words named as
WORDS and initialize.
Lower bytes stored in lower and upper bytes stored in higher
addresses
Assembler Directives (continued...) 2-Feb-23 102
Example - 2
STAR DW 5 DUP (1234H);
Directs assembler to reserve an array of 5 Words
named as STAR and initializes all the locations with
Lower bytes stored in lower and upper bytes stored in
higher addresses

Assembler Directives (continued...) 2-Feb-23 103

 DIRECTIVES
3. DQ DW directive is used to reserve 4 word bytes
(i.e 4 x 8 bits) of memory location , with data
type that may be a
-Constant
-Variable
-String etc; and may be initialized

DIRECTIVES
4. DT DW directive is used to reserve 10 bytes (i.e
10 x 8 bits) of memory location , with data
type that may be a
-Constant ; Variable; String etc
and may be initialized
- Generally processed by numerical
processors
Assembler Directives (continued...) 2-Feb-23 104
 DIRECTIVES
5. END END of program directive marks the end of an
assembly language program (ALP).
-Ignores all source lines available after this line
-Must be used as the last statement in the file
6. ENDP END of procedure directive marks the end of
procedure.
1. In an ALP - subroutines are called procedure.
2. A procedure is an independent program
module
3. - PROCEDURE STAR
-
-
STAR ENDP

Assembler Directives (continued...) 2-Feb-23 105

 DIRECTIVES
7. ENDS END of Segment directive - marks the end
of logical segment.
-Logical segments are assigned with names
using ASSUME directive
-Must be used the last statement in the
segment along with segment name as prefix
8. ASSUME -This directive is used to assign name for
logical segments
-ASSUME directive is a MUST at the
beginning of each ALP.
9. SEGMENT -Marks the starting of logical segment
-Also assigns a name to the logical segment

Assembler Directives (continued...) 2-Feb-23 106

ASSUME CS : CODE, DS : DATA
DATA SEGMENT
STAR DB 20 DUP (?)
:
:
DATA ENDS
CODE SEGMENT
:
:
:
CODE ENDS
END

Assembler Directives (continued...) 2-Feb-23 107

 DIRECTIVES
10. EQU EQU directive is used to assign a label with
a value or symbol
-Used to reduce recurrence of numerical
values or constants in ALP code
-One change in the EQU statement will give
correct and modified code.
-When assembler comes across the label, it
substitutes the numerical values

EXAMPLE
CONST1 EQU 0510H assigns constant 0510h with
label CONST1
ADDITION EQU ADD assigns another label
ADDITION with mnemonic ADD

Assembler Directives (continued...) 2-Feb-23 108

 DIRECTIVES
11. EVEN Align on even memory address directive updates
the location counter to next even address.
- While starting the assembling process, the
assembler initializes a location counter and
updates it sequentially to the program variables;
constants ; modules etc. as required.

EXAMPLE
EVEN
PROCEDURE ROOT
:
:
ROOT ENDP

Assembler Directives (continued...) 2-Feb-23 109

 DIRECTIVES
12. EXTERN • EXTERN directive informs the assembler
and that the names / procedures / labels declared
PUBLIC after this directive have already been defined
in some other ALP module
• In the module where the names,
procedures, labels actually appear must be
declared PUBLIC

MODULE1 SEGMENT
PUBLIC FACTORIAL FAR
MODULE1 ENDS
MODULE2 SEGMENT
EXTRN FACTORIAL FAR
MODULE1 ENDS
Assembler Directives (continued...) 2-Feb-23 110
 DIRECTIVES
13. LOCAL • LOCAL directive informs the assembler
that the labels / variables /constants /
procedures declared after this directive are
used ONLY by that particular module
• In some other module same labels /
variables /constants / procedures can be used
for different purposes.
• Single statement can be used to declare all
labels / variables /constants / procedures

LOCAL a, b, DATA, ARRAY, ROUTINE

Assembler Directives (continued...) 2-Feb-23 111

 DIRECTIVES
14. GLOBAL • LOCAL directive informs the assembler
that the labels / variables /constants /
procedures declared after this directive can
be used by OTHER modules in the program

ROUTINE PROC GLOBAL

Procedure ROUTINE is declared as a global label

Assembler Directives (continued...) 2-Feb-23 112

 DIRECTIVES
15. GROUP • Forms logical groups of segments with
similar purpose or types
• Assembler informs loader/linker to place
group declared segments or operands must
lie within 64KB memory segment

PROGRAM GROUP CODE, DATA, STACK

CODE, DATA, STACK segments lie within 64 KB which
is named as PROGRAM

Assembler Directives (continued...) 2-Feb-23 113

 DIRECTIVES
16. LABEL • Used to assign a name to the current
content of the location counter
•The type of the label must be specified (i.e)
NEAR or FAR label, BYTE or WORD label

After reserving 50
locations for DATAS,
DATA SEGMENT the next location will
DATAS DB 50H DUP (?) be assigned a label
DATA-LAST LABEL BYTE FAR DATA-LAST and its
DATA ENDS type will be Byte and
Far

Assembler Directives (continued...) 2-Feb-23 114

 DIRECTIVES
17. LENGTH Used to refer to the length of a data array or
string
MOV CX, LENGTH ARRAY
Substitutes the length of the array ARRAY in bytes

DIRECTIVES
18. NAME Used to assign a name to an ALP module

MULTI_PGM NAME
:
:
:
END

Assembler Directives (continued...) 2-Feb-23 115

 DIRECTIVES
19. ORG Directs the assembler to start the memory
allotment for the particular block or code from
the declared address in the ORG statement
Without ORG location counter is initialized to
0000
ORG 200H
Initializes the location counter to the address 0200h instead
of 0000h

Assembler Directives (continued...) 2-Feb-23 116

 DIRECTIVES
20. PROC Marks the start of a named procedure

NEAR / FAR specify the type of the procedure

NEAR- called by the main program located

within 64K of physical memory
FAR – Called by the main program located at a
more than 64K of physical memory

RESULT PROC NEAR

ROUTINE PROC FAR
Procedure RESULT is placed in the same segment
Procedure ROUTINE is placed in some other segment

Assembler Directives (continued...) 2-Feb-23 117

 DIRECTIVES
21. FAR PTR • Indicates the assembler that the label
following FAR PTR is not within the
same segment
• Address of label is of 32 bits (4 bytes)
[2 bytes offset followed by 2 bytes
segment address]

JMP FAR PTR LABEL1

CALL FAR PTR ROUTINE

Assembler Directives (continued...) 2-Feb-23 118

 DIRECTIVES
22. NEAR PTR • Indicates the assembler that the label
following FAR PTR is in the same
segment
• Address of label is of 16 bits (2 bytes)
[2 bytes offset only]

JMP NEAR PTR LABEL1

CALL NEAR PTR ROUTINE

Assembler Directives (continued...) 2-Feb-23 119

 OPERATORS
1. OFFSET OFFSET operator indicates the assembler
to compute the16 bit displacement (offset)
of the label and replace the string ‘OFFSET
LABEL’ by the computed displacement
Used with arrays, strings, labels and procedures to
decide their offset in their default segments

CODE SEGMENT
MOV SI, OFFSET LIST
CODE ENDS
DATA SEGMENT
LIST DB 10H
DATA ENDS
Assembler Directives (continued...) 2-Feb-23 120
 OPERATORS
2. PTR - PTR operator is used to declare the type of a
label, variable or memory operand.
- PTR operator is prefixed by BYTE or WORD

MOV AL, BYTE PTR [SI] - Moves content of memory

location addressed by SI to AL
INC BYTE PTR [BX] - Increments byte content of
memory location addressed by BX
MOV BX, WORD PTR [2000H] - Moves 16 bit content of
memory location 2000h to BX (i.e) [2000h] to BL, [2001h] to
BH
INC WORD PTR [2000H] - Increments word content of
memory location 3000h and 3001h as a 16 bit number
Assembler Directives (continued...) 2-Feb-23 121
 OPERATORS
3. SEG SEG operator is used to decide the segment
address of the label, variable or procedure and
substitutes the segment base address in place of
‘SEG’ label

MOV AX, SEG ARRAY

MOV DS, AX

Moves the segment address of ARRAY in which it is

appearing into the register AX and then into DS

Assembler Directives (continued...) 2-Feb-23 122

 OPERATORS
4. SHORT SHORT operator indicates to the assembler
that only one byte is required to code the
displacement for a jump
By specifying this way the assembler saves
memory.
JMP SHORT LABEL

OPERATORS
5. +, - Represents arithmetic addition and subtration

MOV AL, [SI +2]

MOV DX, [BX -5]
MOV BX, [OFFSET LABEL +10H]
Assembler Directives (continued...) 2-Feb-23 123
 OPERATORS
6. TYPE TYPE operator directs the assembler to decide
the data type of the specified label and replace
the ‘TYPE’ label by the decided data type.

For byte type variable, the data type is 1;

For word type variable, the data type is 2;
For double word type, the data type is 4;

MOV AX, TYPE STRING

If STRING is a word array, then the value 0002h is

moved in AX

Assembler Directives (continued...) 2-Feb-23 124

Reasons for breaking a program into small parts:

1. Modules are easy to comprehend

2. Different modules can be assigned to different
programmers
3. Debugging and testing done in orderly fashion
4. Documentation – easily understood
5. Modifications – localized
6. Frequently used tasks can be programmed into
modules that are stored in libraries and used by
several programs.

Modular Programming (continued...) 2-Feb-23 125

A Program that converts assembly language program into
equivalent machine codes, which may further be converted to
executable codes
Assembler does the following in steps:
• Decides the address of each label
• Substitutes the values for each of the constants and variables
• Forms the machine code for mnemonics and data in the
assembly language program
During the above process, assembler finds out syntax errors, but
logical errors are not found
For completing these tasks assembler needs hints from the
programmer ; like -
• Storage required for a particular constant or a variable,
• Logical names of the segment,
• Types of the different routines and modules,
• End of files, etc.
Assembler; Linker; Relocator (continued...) 2-Feb-23 126
 An assembler translates the assembly language
program into machine language program
 Assembly language program  source codes
 Machine language program object codes
 Assembler converts Source code into Object code
 Linker converts Object code into executable code

Assembler; Linker; Relocator (continued...) 2-Feb-23 127

Assembler works in passes:
1. In the first pass, it determines the displacement of
the named data items, the offset of labels etc. and
puts this information to in a symbol table.

2. In the second pass, it produces the binary codes for

each instructions and inserts the offsets etc. that it
calculated in the first pass.

3. It generates two files namely object file (.OBJ) and

assembler list file (.LST).

Assembler; Linker; Relocator (continued...) 2-Feb-23 128

 Linker is a program used to join several object files into one
large object file.

1. While writing large programs it is good to divide them

into modules so that each modules can be written, tested,
debugged independently and then use linker to combine
the modules to form the actual program.

2. It produces two files - link file which contains the binary

codes of all the combined modules and a link map file
which contains the address information about the linked
files.

Assembler; Linker; Relocator (continued...) 2-Feb-23 129

 A locator is the program used to assign the specific
addresses of where the segments of object code are
to be loaded in to main memory.

1. Examples include EXE2BIN which comes with

the IBM PC DOS.
2. Converts .exe to .bin files which has physical
addresses

Assembler; Linker; Relocator (continued...) 2-Feb-23 130

 A debugger is the program which allows to load the
object code program in to system memory.

1. It allows to look at the contents of the registers and

memory locations after a program is run.

2. It also allows to set breakpoints at any points in the

program.

3. It allows to find the source of the problem into the

program.

4. There are lots of debuggers available like Borland

Turbo Debugger, Microsoft’s Code view debugger etc.

Assembler; Linker; Relocator 2-Feb-23 131

 A STACK is a Last-Input-First-Output (LIFO)
read/write memory (i.e) data segment
 It is a top-down data structure, whose elements
are accessed using SS and SP registers
 Stack pointer is decremented by 2 while ‘pushing
into’ the stack
 Stack pointer is incremented by 2 while ‘poping
off’ the stack

Stacks (continued . . .) 2-Feb-23 132

Stack is used to:

 Store return addresses whenever a procedure is

called

 Save contents of registers / register status of the

processor while calling a procedure

 Hold data or addresses that will be acted upon by

the procedure

Stacks (continued . . .) 2-Feb-23 133

ASSUME CS:CODE, SS: STACK

STACK SEGMENT
STACKDATA DW 40 DUP(0)
STACKTOP LABEL WORD
STACK ENDS

CODE SEGMENT
MOV AX, STACK
MOV SS, AX ;initialize stack Seg. Regr.
LEA SP, STACKTOP ;initialize stack pointer
- - - - - -
- - - - - - ;program instructions
CODE ENDS
END
Stacks (continued . . .) 2-Feb-23 134
PUSH always transfers 2 bytes of data to the stack.
Syntax : PUSH <src>;
<src> could be any 2 byte Register or Memory location
or Immediate value

When PUSH is executed, the most significant byte is

stored in stack segment pointed to by SP-1, and the
least significant byte to location pointed by SP-2.

Stacks (continued . . .) 2-Feb-23 135

 Do not click the mouse to see the full animation

 PUSH AX

AX

F2 200FD
31 200FE
20100

SP=00FD
SP=00FE
SP=0100 SS=2000H

Stacks (continued . . .) 2-Feb-23 136

Assume Show the changes in the stack
SS=2000H, after executing the following
SP=100H, instructions:
AX=31F2H,
BX=413AH, PUSH AX
PUSH BX
CX=FFFFH.
POP CX
POP AX

Stacks (continued . . .) 2-Feb-23 137

SS=2000H,
SP=100H,
AX=31F2H, CH CL

BX=413AH, 41
FF 3A
FF
CX=FFFFH. BH BL
41 3A
PUSH AX
3A 200FC
PUSH BX AH AL
41 200FD
POP CX 31 F2 F2 200FE
POP AX 31 200FF
XX 20100

SP=0100h
SP=00FEh
SP=00FCh SS=2000H

Stacks (continued . . .) 2-Feb-23 138

◦ A procedure is a sequence of instructions written
to perform a particular task

◦ Replacing a set of frequently used instructions

by a procedure saves program memory space

◦ A CALL instruction in the main program causes

8086 to the execute the set of instructions
contained in a procedure

◦ A RET instruction at the end of procedure

returns execution to the next instruction in the
main program

Procedures (continued . . .) 2-Feb-23 139

 MAINLINE
OR
CALLING PROGRAM

PROCEDURE
INSTRUCTIONS

CALL

NEXT MAINLINE
INSTRUCTIONS
RET

Procedures (continued . . .) 2-Feb-23 140

Procedures (continued . . .) 2-Feb-23 141
◦ Saves program memory space

◦ Problem can be divided into small modules

◦ Allows reusability of code

Disadvantage

◦ Takes more time to execute

Procedures (continued . . .) 2-Feb-23 142

 8086 performs the following operations when a
CALL instruction is executed

1. Stores the address of the instruction after the

CALL instruction on to the stack

2. Changes the contents of Instruction Pointer

(IP) register and in some cases the Code
Segment (CS) register to contain and point to
the starting address of the procedure

Procedures (continued . . .) 2-Feb-23 143

◦ Direct Near (within segment) CALL
◦ Direct Far (inter segment) CALL
◦ Indirect Near (within segment) CALL
◦ Indirect Far (within segment) CALL

Procedures (continued . . .) 2-Feb-23 144

 When 8086 does a NEAR CALL, it pushes the
instruction pointer (IP) value (for the instruction
after CALL) on to the stack

 A RET instruction at the end of a procedure pops

this value back to instruction pointer (IP) to
return to the calling program (main program).

Procedures (continued . . .) 2-Feb-23 145

 A macro is the repeatedly appearing group of
instructions, that is given a name at the start of
the program.
 A macro can be defined anywhere in a program
using the directives MACRO and ENDM

Defining a Macro:
name MACRO [optional arguments]
statements..
statements..
ENDM

Macros (continued . . .) 2-Feb-23 146

• Macro name can be used in the actual program
• Every occurrence of the macro name (apart
from the definition) is replaced by the
statements in the macro definition.

Macros (continued . . .) 2-Feb-23 147

Advantages
1. Repeated small group of instructions replaced by one
macro
2. Errors in macros are fixed only once, in the definition
3. Duplication of effort is reduced
4. Programming is made easier and less error prone
5. Generally quicker in execution than subroutines
Disadvantages
In large programs, macros produce larger code size
than procedures

Macros (continued . . .) 2-Feb-23 148

1. Advantage of using 1. Advantage of using
procedures is that the macro is that it avoids
machine codes for the overhead time
the group of involved in calling and
instruction in the returning from a
procedures needs to procedures.
be loaded into main
memory only once. 2. Disadvantage is that
macros make the
2. Disadvantage using program occupy more
the procedures is the memory than using a
need for the stack. procedure.
Macros (continued . . .) 2-Feb-23 149
 Capability to suspend the execution of running
program and execution of another program to
fulfill specific requirement upon request

 After finishing the second program, automatically

return to the first program and start execution
from where it was left

Interrupts and ISR (continued . . .) 2-Feb-23 150

 Most microprocessors allow normal program
execution to be interrupted by some external signal or
by a special instruction in the program.

 In response to an interrupt, the microprocessor stops

executing its current program and calls a procedure
which “services” the interrupt.

 A special instruction --- IRET --- at the end of

interrupt-service procedure returns execution to the
interrupted main program.

Interrupts and ISR (continued . . .) 2-Feb-23 151

 SOURCES OF 8086 INTERRUPTS
8086 interrupts can be classified into two types:

 1) Predefined interrupt
Some error condition produced by execution of an
instruction, e.g., trying to divide some number by zero.
(Interrupt due to exceptions)

 2) User defined interrupt

i) Hardware interrupt
An external signal applied to NMI, INTR pins
ii) Software interrupt
Execution of interrupt instruction INT

Interrupts and ISR (continued . . .) 2-Feb-23 152

NMI (Non Maskable Interrupt):
Any interrupt request at NMI input pin cannot be masked
or disabled by any means; type is implicit

INTR:
This hardware interrupt can be masked using Interrupt
Flag (IF); 256 Types (00h to FFh); to handle more than
one interrupts that occur at a time, Programmable
Interrupt Controller is required.

INT:
This is a software interrupt; the type is specified in the
instruction

At the end of each instruction cycle, 8086 checks if any

interrupt service has been requested.

If yes, then 8086 responds to the interrupt by stepping

through the following series of actions:
Interrupts and ISR (continued . . .) 2-Feb-23 153
1. 8086 decrements SP by 2 and pushes flag register
content into the stack.
2. 8086 disables INTR input by clearing IF flag in
flag register
3. The TF (trap) flag in flag register is Reset
4. Decrements SP again by 2 and pushes current CS
content into the stack.
5. Decrements SP again by 2 and pushes current IP
content into the stack.
6. Does an indirect far jump to the start of the
procedure written to respond to the interrupt.

Interrupts and ISR (continued . . .) 2-Feb-23 154

 main 1. Push FLAGS Interrupt
Program 2. Clear IF Service Routine
3. Clear TF (ISR)
4. Push CS PUSH registers
5. Push IP ...
6. Fetch ISR ...
address ...
....
POP IP ...
....
POP CS
...
POP FLAGS POP registers
IRET

Interrupts and ISR (continued . . .) 2-Feb-23 155

 HOW DOES 8086 GET TO
INTERRUPT SERVICE ROUTINE?

1. 8086 loads its CS and IP registers with the

address of ISR.

2. So, the next instruction to be executed is the

first instruction of ISR

Interrupts and ISR (continued . . .) 2-Feb-23 156

 HOW DOES 8086 GET THE ADDRESS OF
INTERRUPT SERVICE ROUTINE (ISR)?
1. In an 8086 system, each “interrupter” (external and
internal ) has an id#; 8086 treats this id# as interrupt-type#
2. After receiving INTR signal, 8086 sends an INTA signal
3. After receiving INTA signal, interrupter releases it’s id#,
(i.e.) type# of the interrupt.
5. 8086 multiplies this id# or type# by 4 to produce the
desired address of the location in the Interrupt Vector
Table (IVT), where ISR address is stored.
6. 8086 reads 4 consecutive bytes starting from this location
to get the starting address of ISR
7. First 2 bytes are loaded in to IP
8. Second 2 bytes to CS
Interrupts and ISR (continued . . .) 2-Feb-23 157
 INTERRUPT VECTOR TABLE (IVT)
 In an 8086 system, the first 1Kbytes (1024 bytes) of
memory, from 00000 to 003FF, is set aside as a Table
for storing the starting addresses of interrupt service
routines.

 Since 4 bytes are required to store CS and IP values

for each ISR, the Table can hold the starting addresses
for up to 256 ISRs.

 The starting address of an ISR is often called the

interrupt vector or the interrupt pointer.

 So the Table is referred to as interrupt-vector table or

interrupt-pointer table.

Interrupts and ISR (continued . . .) 2-Feb-23 158

 The 256 interrupt vectors are arranged in the table in
memory as follows in the next slide.

Note :
 The IP value is put in as the lower word of the vector
and CS as higher word of the vector

 Each double word interrupt vector is identified by a

number from 0 to 255 (00h to FFh)

 INTEL calls this number as the TYPE of the interrupt

Interrupts and ISR (continued . . .) 2-Feb-23 159

 AVAILABLE 3FFH TYPE 255
FOR USER
...
(224) 080H TYPE 32
TYPE 31
RESERVED (27)
...
014H TYPE 5
TYPE 4
010H Overflow INTO

TYPE 3
Predefined/ 00CH One Byte INT
Dedicated/Internal TYPE 2
Interrupts Pointers 008H NON-MASKABLE
(5) TYPE 1
004H SINGLE STEP
CS Base Address TYPE 0
IP Offset 000H DIVIDE ERROR
Higher priority interrupts will be
served first

Interrupts and ISR (continued . . .) 2-Feb-23 161

Interrupt Type Priority
DIVIDE ERROR, INT N, INT0 HIGHEST
NMI
INTR
LOWEST
SINGLE STEP

Interrupts and ISR (continued . . .) 2-Feb-23 162

S.No CALL Instruction INTn instruction
1 Upon the execution ,the control Upon execution the control will
will jump to any one of the 1 MB jump to a fixed location in the
of memory locations . vector table.
2 The user can insert in the Can occur at any time activated
sequence of instructions of a by hardware
program
3 Once initiated it cannot be Can be masked
masked
4 When initiated ,it stores the CS:IP When initiated ,it stores the
of the next instruction on the CS:IP of the next instruction and
stack also the flag register on the
stack.
5 The last instruction of the The last instruction of the ISS
subroutine will be RET will be IRET
Interrupts and ISR (continued . . .) 2-Feb-23 163
1. External interface sends an interrupt signal, to the Interrupt
Request (INTR) pin, or an internal interrupt occurs.
2. The CPU finishes the present instruction (for a hardware
interrupt) and sends Interrupt Acknowledge (INTA) to
hardware interface.
3. The interrupt type N is sent to the Central Processor Unit
(CPU) via the Data bus from the hardware interface.
4. The contents of the flag registers are pushed onto the stack.
5. Both the interrupt (IF) and (TF) flags are cleared. This
disables the INTR pin and the trap or single-step feature.

Interrupts and ISR (continued . . .) 2-Feb-23 164

6. The contents of the code segment register (CS) are pushed
onto the Stack.
7. The contents of the instruction pointer (IP) are pushed
onto the Stack.
8. The ISR address from the interrupt vector table (IVT) is
fetched, by finding (4 x N). Where N is the ‘type’ of
interrupt.
9. In the IVT, the first 2 bytes starting from 4 x N is placed
into the IP and the next 2 bytes from (4xN +2) is placed
into the CS, so that the next instruction is executed from
the ISR addressed by the interrupt vector.
10. While returning from the ISR by the Interrupt Return
(IRET) instruction, the IP, CS and Flag (PSW) registers
are popped from the stack and returns to the state prior to
the interrupt.
Interrupts and ISR (continued . . .) 2-Feb-23 165
 OVERVIEW
 INTRODUCTION TO 8086
 8086 ARCHITECTURE
 ADDRESSING MODES
 8086 INSTRUCTION SET
 ASSEMBLER DIRECTIVES
 ASSEMBLY LANGUAGE PROGRAMMING
 MODULAR PROGRAMMING
 STACKS
 PROCEDURES
 MACROS
 INTERRUPTS AND INTERRUPT SERVICE ROUTINES
 BYTE AND STRING PROGRAMMING 2-Feb-23 166
• A string is a series of bytes or words stored in
successive memory locations

• 8086 can perform the following operations on

strings
– Moving a string from one place in memory to
another
– Compare two strings
– Search a string for a specified character

Strings (continued . . .) 2-Feb-23 167

 String
instructions

MOVS LODS STOS

MOVSB MOVSW LODSB LODSW STOSB STOSW

B stands for byte, and W stands for word

Strings (continued . . .) 2-Feb-23 168

MOVSB/ MOVSW Instruction
• Copies a byte or word from a location in the data
segment (DS) to the location in the extra segment
(ES)
• Offset of source in data segment must be in SI
register
• Offset of destination in extra segment must be in
DI register
• For multiple byte/word moves the count is stored
in CX register

Strings (continued . . .) 2-Feb-23 169

• DF = 0
– SI & DI will be incremented by 1 or 2 after
every byte or word is moved
• DF = 1
– SI & DI will be decremented by 1or 2 after
every byte or word is moved

Strings (continued . . .) 2-Feb-23 170

Strings (continued . . .) 2-Feb-23 171
 LEA (Load Effective Address)
◦ this instruction determines the offset of the
variable or memory location named as the
source and puts it in the specified 16-bit register
 CLD (Clear Direction Flag)
 REP (Repeat)
◦ A prefix written before one of the string
instruction
◦ Causes string instruction to be repeated until
CX=0
Strings (continued . . .) 2-Feb-23 172
For LODSB this is how it is done
◦ AL = DS:[SI]

◦ if D = 0 then SI = SI + 1

◦ else SI = SI – 1

◦ And LODSW is the same except that SI by 2

Strings (continued . . .) 2-Feb-23 173

For STOSB Store byte in AL into ES:[DI]. Update DI.

For STOSW Store word in AX into ES:[DI]. Update DI.

How STOSB executes?

 ES:[DI] = AL
if DF = 0 then DI = DI + 1
 Else DI = DI - 1

 And STOSW executes the same as STOSB but DI is

incremented or decremented by 2

Strings (continued . . .) 2-Feb-23 174