Virtuoso SystemVerilog Netlister User Guide

Product Version IC23.1

March 2025
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 Virtuoso SystemVerilog Netlister User Guide
Table of Contents

Contents
1 6
Introduction to Virtuoso SystemVerilog Netlister 6
Licensing Requirements 6
Benefits of SystemVerilog Netlister 7
Benefits of SystemVerilog Netlister over NC Verilog Netlister 10
Prerequisites for Using SystemVerilog Netlister 11
Launching SystemVerilog Netlister 12
SystemVerilog Netlister Batch Mode 14
SystemVerilog Config Views 15
Migrating SystemVerilog Integration Designs to SystemVerilog Designs 16
Exporting SystemVerilog Netlister Settings as Environment Variables 17
2 18
Netlist Generation 18
Netlist Generation Flow in SystemVerilog Netlister 18
Specifying a Design for Netlist Generation 20
Configuring Netlist Generation Options 21
Configuring Design Variables 23
Generating and Regenerating a Netlist 24
Viewing a Netlist 25
State Management 26
ATPG Compatible Verilog Netlists 27
Generating ATPG Compatible Verilog Netlists 28
Importing a SystemVerilog Package File 29
Specifying Additional xrun Arguments in SystemVerilog Netlister 31
DataType Propagation 32
Netlist Customization Using the .simrc File 37
3 41
SystemVerilog Netlister Forms 41
Additional Arguments Form 41
Editing Design Variables Form 42
Export Environment Variables Form 42
Load State Form 43

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Table of Contents

Save State Form 43

Select Design/Directory Form 44
SystemVerilog Netlister Graphical User Interface 45
SystemVerilog Netlister Options Form 46
Netlister Tab 46
Miscellaneous Tab 51
Verilog Tab 53
4 56
Environment Variables 56
addArgTableList 57
addPrefixToCells 57
cellPrefixName 58
createXrunArgs 59
createXrunBinding 60
defaultNettype 61
enableDataPropagate 62
enableVerilogATPG 62
expandIterateInst 63
enableTimeScale 64
hdlVarFile 65
isPortInANSIFormat 65
mergedNetlist 66
nettypesToIgnore 67
refLib 68
reUseHdlCompilationSetup 68
simPrecision 69
simPrecisionUnit 70
simTime 71
simTimeUnit 71
termMismatch 72
termDirectionMismatch 73
useTranForCdsAliasThru 74
vlogCompatVersion 75
vlogSupply0Sigs 76
vlogSupply1Sigs 77
outputXmlFile 77

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Table of Contents

printDirectivesForVerilog2001 78
printParamForTextInst 79
netlistNoWarn 80
genUniqCellNameIfConflict 81
5 82
SKILL Functions and Flags 82
asiDigitalSimAutoloadProc 82
SKILL Flags 83
6 85
Batch Mode Options in SystemVerilog Netlister 85
runsv 85
cdsCreateConfig 89
si2runsv 90

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 Virtuoso SystemVerilog Netlister User Guide
Introduction to Virtuoso SystemVerilog Netlister

1
Introduction to Virtuoso SystemVerilog
Netlister

Digital system verification uses the SystemVerilog language extensively, and this has introduced
the Digital-Mixed-Signal (DMS) use model. The DMS use model allows discrete models to
represent analog circuits. SystemVerilog allows you to use user-defined type and resolution
functions, which make the net obsolete as a scalar object.
These use-model changes require a netlister that supports modern constructs, imports data from a
design database, and produces a simulator-compatible netlist. A netlister that has these capabilities
can traverse the design hierarchy to build the complete structure of a netlist. In such cases, the
hierarchy can be a schematic view and a text view, or only a text view.

Virtuoso® SystemVerilog Netlister is a utility that helps you generate netlists of digital
SystemVerilog designs. This utility imports configuration views of digital designs for netlist
generation, directly parses and accesses SystemVerilog and Verilog text models and creates LRM-
compliant SystemVerilog configurations to generate compatible netlists.
This topic describes how to use the SystemVerilog Netlister to configure the environment for
generating netlists of SystemVerilog designs. This topic is aimed at developers and designers of
integrated circuits and assumes that you are familiar with:
The Virtuoso Studio design environment and application infrastructure mechanisms designed
to support consistent operations between all Cadence® tools.
The applications used to design and develop integrated circuits in the Virtuoso Studio design
environment, notably, Virtuoso Schematic Editor.
The Virtuoso Studio design environment technology file.

Licensing Requirements
Virtuoso SystemVerilog Netlister requires the following licenses:
Cadence Design Framework II license (License Number 111)
Virtuoso Schematic Editor Verilog(R) Interface license (License Number 21400)

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Introduction to Virtuoso SystemVerilog Netlister--Benefits of SystemVerilog Netlister

Virtuoso AMS Designer Environment license (License Number 70000) or Virtuoso Schematic
Editor XL license (License Number 95115)
For information about licensing in the Virtuoso Studio design environment, see Virtuoso Studio
Design Environment Licensing Setup .

Related Topics
Virtuoso Studio Design Environment Licensing Setup
Benefits of SystemVerilog Netlister
Benefits of SystemVerilog Netlister over NC Verilog Netlister
Launching SystemVerilog Netlister
SystemVerilog Netlister Batch Mode
Migrating SystemVerilog Integration Designs to SystemVerilog Designs

Benefits of SystemVerilog Netlister

SystemVerilog Netlister provides a quick and efficient approach to netlist SystemVerilog designs
and provides the following features and capabilities:

Feature Description

Dual Provides a graphical user interface and a command-line interface. Supports the
Interface batch or command-line mode using the runsv command.

LRM- Uses only SystemVerilog LRM constructs. This makes the netlist simulator-
compliant independent and available to a SystemVerilog-compliant tool. Vendor
Netlist extensions are not supported.

HED Config Fully supports HED configurations that match UNL. Netlist generation is based
on HED configurations.

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Introduction to Virtuoso SystemVerilog Netlister--Benefits of SystemVerilog Netlister

Direct
Restricts the use of the direct access OA file.
Access to
HDL File Updating the OA for text or symbol for text-in-text instance is redundant.
Supports read-only libraries.
Supports handling ports of packed or unpacked arrays in the design.
Ensures accurate datatype propagation from leaf-level SystemVerilog and
Verilog cellviews to top-level schematic views. The datatype propagation is
based on the native datatype definitions from text files. By default, datatype
propagation is disabled.
Ensures that instances are saved with explicit port connections. Supports
smart connections with module ports of Verilog and SystemVerilog views.
Requires the following:
Instance parameters are netlisted correctly and parameters are
propagated in a UNL-supported method.
Instance parameters that differ from the default parameters use the
explicit declaration format.

Schematic Supports the following formats:

Text
Text-in-schematic
Sandwich
Configuration Schematic-in-text
Text-in-text

Text on Top Supports digital text-on-top views (Verilog, SystemVerilog). Allows descending
into the leaf-level schematic or text views.

Creation of Supports:
SV 2001
Same cell from different libraries
Config for
Bindings Multiple views of the same cell

Config in Supports config-in-config views where config view has the top-level schematic
Config of different cells.

Symbol Avoids the requirement for a symbol unless the cell is instantiated in a
Avoidance schematic view.

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Introduction to Virtuoso SystemVerilog Netlister--Benefits of SystemVerilog Netlister

Data type Supports SystemVerilog data types. Requires that any net, port, or bus from a
Handling schematic or symbol uses the interconnect net type, by default. Support for the
wire net type is also available. Allows declaring internal signals with these
nettypes.

Instance Requires the following:

Parameters
Instance parameters are netlisted correctly and parameters are propagated
Handling
in a UNL-supported method.
Instance parameters that differ from the default parameters use the explicit
declaration format.

Port Ensures that instances are saved with explicit port connections. Supports smart
Connection connections with module ports of Verilog and SystemVerilog views.
Handling

Optional Creates an xrunArgs file, which includes the full set of generated files.
xrunArgs File
Creation

Keywords Prefixes each 1800-2012 keyword with an escape character.

Handling

Inherited Mandates the use of port-drilling only for schematic views.

Connection
Handling

Self- Creates a self-contained set of files without links to the text views in dfII*.
contained
Netlist
Creation

ANSI Port Supports module port declaration in ANSI format.

Declaration

Iterated Supports instance arrays instead of flattened instances in the design.

Instance
Support

Design Supports the use of design variables. All design variables are saved in the
Variable cds_globals.sv file.
Support

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Introduction to Virtuoso SystemVerilog Netlister--Benefits of SystemVerilog Netlister over NC Verilog
Netlister

Shorting Supports shorting devices with two terminals.

Support

Bind to Open Supports binding instances to open ports.

Support

Save/Load Supports saving states with specified settings and subsequently loading these
State saved states for reuse.

cdsenv Provides various .cdsenv options for configuring netlist generation. Saves the
Support values of these options into states.

CDF Fully supports CDF parameters, including pPar.

Parameter
Support For all stopping views, the defined CDF parameters are printed on the
instance line, instead of the defparam statement.

For more information on CDF Parameters, see Defining Parameters .

Related Topics

Defining Parameters
Introduction to Virtuoso SystemVerilog Netlister
Benefits of SystemVerilog Netlister over NC Verilog Netlister
Prerequisites for Using SystemVerilog Netlister
Launching SystemVerilog Netlister
SystemVerilog Netlister Batch Mode
Migrating SystemVerilog Integration Designs to SystemVerilog Designs

Benefits of SystemVerilog Netlister over NC Verilog

Netlister
Some of the advantages that SystemVerilog Netlister offers, which the NC Verilog Netlister does
not, are as follows:
Symbol is redundant for text-in-text instances

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Introduction to Virtuoso SystemVerilog Netlister--Prerequisites for Using SystemVerilog Netlister

OA update for text is redundant

Schematic text sandwich structure
Support for read-only libraries
Full support for HED config
Flexible flowchart control
Advanced parameter and bus handling
Simulator-independent netlist and binding

Related Topics

Introduction to Virtuoso SystemVerilog Netlister

Benefits of SystemVerilog Netlister
Prerequisites for Using SystemVerilog Netlister
Launching SystemVerilog Netlister
SystemVerilog Netlister Batch Mode
Migrating SystemVerilog Integration Designs to SystemVerilog Designs

Prerequisites for Using SystemVerilog Netlister

You must have access to the following to use Virtuoso SystemVerilog Netlister:
Cadence Virtuoso 64-bit version (IC6.1.8 ISR8 or higher)
SystemVerilog Netlister is launched from Virtuoso.
Cadence Xcelium™ xrun utility 64-bit version (18.09 or higher)
The xrun utility helps you specify all input files and options in a single command.
It can take SystemVerilog designs as input. The utility uses the Cadence Native Code tools to
compile and netlist designs.
Additionally, ensure that you update your .cshrc file as follows:
Specify the path to the Virtuoso installation.
Specify the path to the Xcelium installation.

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Introduction to Virtuoso SystemVerilog Netlister--Launching SystemVerilog Netlister

To ensure that you use the 64-bit version of Virtuoso and Xcelium, add the environment
variable setenv CDS_AUTO_64BIT ALL to your .cshrc file.

Related Topics
Introduction to Virtuoso SystemVerilog Netlister
Benefits of SystemVerilog Netlister
Launching SystemVerilog Netlister
SystemVerilog Netlister Batch Mode
Migrating SystemVerilog Integration Designs to SystemVerilog Designs

Launching SystemVerilog Netlister

SystemVerilog Netlister provides a simple and efficient interface to let you configure settings and
options for netlist generation.
To launch the SystemVerilog Netlister application and specify the design:
1. Launch Virtuoso.
2. In the CIW, choose Tools – SystemVerilog – Netlister.
The SystemVerilog Netlister window appears.
3. Click Browse to specify the design.

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Introduction to Virtuoso SystemVerilog Netlister--Launching SystemVerilog Netlister

Alternatively, to first select the design and then launch SystemVerilog Netlister:
1. Launch Virtuoso.
2. In the CIW, choose Tools – Library Manager.
The Library Manager window appears.
3. In the Library Manager window, select a library from the Library list.
The cells present in the specified library appear in the Cell list.
4. Select a cell from the Cell list.
The views present in the specified cell appear in the View list.
5. Select a dnl_state* view from the View list.
The SystemVerilog Netlister window appears and shows the design.

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Introduction to Virtuoso SystemVerilog Netlister--SystemVerilog Netlister Batch Mode

Related Topics
Introduction to Virtuoso SystemVerilog Netlister
Benefits of SystemVerilog Netlister over NC Verilog Netlister
Prerequisites for Using SystemVerilog Netlister
SystemVerilog Netlister Batch Mode
Migrating SystemVerilog Integration Designs to SystemVerilog Designs

SystemVerilog Netlister Batch Mode

Before you launch SystemVerilog Netlister ensure that you meet all the prerequisites.
SystemVerilog Netlister can be launched in batch mode by running the runsv command. This
command supports the following options:
-lib <libName>
-cell <cellName>
-view <config_viewname>
-rundir <projectdir>
-netlist
-cdsenv <path of .cdsenvfile>
-state <saved SystemVerilog Netlister state (stateLib/stateCell/stateView)>

For example, if you have a design topLib/topCell/config_sv and you specify the project directory
as runsv_run, use the following command to generate the netlist in batch mode:
runsv -lib topLib -cell topCell -view config_sv -netlist -rundir runsv_run

To increase performance, load the initialization details in a .runsvinit file instead of the .cdsinit
file.

You can optionally use the -cdsenv option to read the file. However, if you want to enable
data type propagation or create an additional argument file, set the enableDataPropagate,
defaultNettype, mergedNetlist, and createXrunArgs environment variables in the .cdsenv
or the .cdsinit file.

Related Topics

Introduction to Virtuoso SystemVerilog Netlister

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Introduction to Virtuoso SystemVerilog Netlister--SystemVerilog Config Views

Prerequisites for Using SystemVerilog Netlister

createXrunArgs
defaultNettype
enableDataPropagate
mergedNetlist
runsv

SystemVerilog Config Views

When using SystemVerilog Netlister, ensure that your specified design has a config view that
contains only digital content. This digital content can be a SystemVerilog or Verilog text view, a
schematic view, or a symbol view. If your design does not have a config view, use the
cdsCreateConfig utility available with SystemVerilog Netlister. This utility helps you create a config
view.
You can use the following options with the cdsCreateConfig utility:
cdsCreateConfig
-lib topLibName
-cell topCellName
-view topViewName
[-config newConfigName]
[-liblist 'lib1 lib2']
[-viewlist 'view1 view2']
[-stoplist 'stopview1 stopview2']

For example, if you have a design topLib/topCell/schematic, use the following command in the
terminal window to create a config view:
cdsCreateConfig -lib topLib -cell topCell -view schematic

To view the various options available with the cdsCreateConfig utility, type the following command
in the terminal window.
cdsCreateConfig -help

Related Topics
cdsCreateConfig
Introduction to Virtuoso SystemVerilog Netlister

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Introduction to Virtuoso SystemVerilog Netlister--Migrating SystemVerilog Integration Designs to
SystemVerilog Designs

SystemVerilog Netlister Batch Mode

Migrating SystemVerilog Integration Designs to

SystemVerilog Designs
Convert commands used in the Virtuoso Verilog Environment for SystemVerilog Integration
Environment (SI) to a format supported by SystemVerilog Netlister by using the si2runsv utility.
You can run SystemVerilog Netlister by using the following command:
si [run directory] [-batch [-command commandName]]

For example:
si dir1 -batch -command netlist

Alternatively, SystemVerilog Netlister uses the following command:

runsv -lib lib -cell cell -view configView -netlist -state stateName

To convert a SystemVerilog Integration environment command to a SystemVerilog Netlister

command:
1. Run the following command to generate a script file:
si2runsv

This command generates a runsv_xxxfile script file.

2. Run the following command to run SystemVerilog Netlister using this script file:
si2runsv dir1 -batch -command netlist

To view the various options available with the si2runsv utility, type the following command in
the terminal window.
si2runsv -help

Related Topics
si2runsv
Introduction to Virtuoso SystemVerilog Netlister
SystemVerilog Netlister Batch Mode

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Introduction to Virtuoso SystemVerilog Netlister--Exporting SystemVerilog Netlister Settings as
Environment Variables

Exporting SystemVerilog Netlister Settings as

Environment Variables
To export the SystemVerilog Netlister settings and GUI options as environment variables:
1. In SystemVerilog Netlister form, choose Commands – Export Environment Variables.
The Export Environment Variables Form opens.
2. Specify the name of a new or an existing file in the Save to file field.
3. Click OK.
The settings from the SystemVerilog Netlister form are exported to the specified file.

Related Topics
Export Environment Variables Form
SystemVerilog Netlister Graphical User Interface

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 Virtuoso SystemVerilog Netlister User Guide
Netlist Generation

2
Netlist Generation

Use the SystemVerilog Netlister to specify a design, configure the netlist generation options,
configure design variables, netlist the design, view the netlist, and manage the states. You can
generate a netlist, which contains connectivity information of a design, after you have specified the
design. Configure the netlist generation options before you generate the netlist. When you generate
the netlist, SystemVerilog Netlister creates a netlist file of your design based on the settings that you
specify and lets you view the netlist file.

Related Topics
Specifying a Design for Netlist Generation
Configuring Netlist Generation Options
ATPG Compatible Verilog Netlists
Importing a SystemVerilog Package File
Specifying Additional xrun Arguments in SystemVerilog Netlister
DataType Propagation
Netlist Customization Using the .simrc File

Netlist Generation Flow in SystemVerilog Netlister

The following diagram depicts the overall netlist generation flow.

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Netlist Generation--Netlist Generation Flow in SystemVerilog Netlister

To know about any issues that you might encounter while using SystemVerilog Netlister, refer to the
log in the Virtuoso CIW. The status of the last operation is also visible on the SystemVerilog
Netlister window.

Related Topics
Specifying a Design for Netlist Generation
ATPG Compatible Verilog Netlists
Importing a SystemVerilog Package File
Specifying Additional xrun Arguments in SystemVerilog Netlister
DataType Propagation
Netlist Customization Using the .simrc File

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Netlist Generation--Specifying a Design for Netlist Generation

Specifying a Design for Netlist Generation

To start netlist generation by specifying a design:
1. Open the SystemVerilog Netlister window.
2. Click Browse in the Design group box.
The Select Design/Directory Form appears.

3. Select a library from the Library list.

The cells in the specified library appear in the Cell list.
4. Select a cell from the Cell list.
The views in the specified cell appear in the View list.
5. Select a config view from the View list.
6. Specify a new project directory name in the Project directory field, if required.
The default project directory name is sv-netlist.
7. Click OK to select the design.
The CIW displays an appropriate message to indicate that the design specification is successful.

Related Topics
Launching SystemVerilog Netlister

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Netlist Generation--Configuring Netlist Generation Options

SystemVerilog Netlister Graphical User Interface

Select Design/Directory Form
State Management

Configuring Netlist Generation Options

Before you generate the netlist of a design, ensure that you configure the netlist generation options,
as required. SystemVerilog Netlister generates the netlist based on how you configure these
options. By default, the netlist file is stored in the <projectDir>/<lib>_<cell>_<view>/netlist/
directory.
For example:
projectDir/lib_cell_view/netlist/netlist.sv

To configure netlist generation options, based on which the SystemVerilog Netlister generates a
netlist:
1. Launch SystemVerilog Netlister.
2. In the Settings group box, click Open Option Form to set additional options.
The SystemVerilog Netlister Options Form appears with the Netlister tab selected.

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Netlist Generation--Configuring Netlist Generation Options

3. In the Netlister and Miscellaneous tabs of the SystemVerilog Netlister Options form, specify
the required values or options and click OK.
For Verilog cellviews, specify the values or options on the Verilog tab of the SystemVerilog
Netlister Options form.
The SystemVerilog Netlister options are successfully configured.

Related Topics
SystemVerilog Netlister Options Form
Launching SystemVerilog Netlister
SystemVerilog Netlister Graphical User Interface
Generating and Regenerating a Netlist
Viewing a Netlist

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Netlist Generation--Configuring Design Variables

Configuring Design Variables

You can add, delete, or change design variables in your netlisting settings in SystemVerilog
Netlister after choosing your design.
To set up a design variable:
1. Click Design Variables in the SystemVerilog Netlister window.
The Editing Design Variables Form opens.

2. Specify a name for the design variable in the Name field.

3. Specify a value for the design variable in the Value (Expr) field.
4. Click Add to add a variable.
The design variable appears in the Design Variables list on the right and is saved in the
cds_globals.sv file.

5. Click Delete to delete a design variable by selecting the variable name from the Design
Variables list box.
6. Click Change to change the name or value of a design variable by selecting the variable
name from the Design Variables list box.
Edit the name or the value of the design variable, as required.
7. Click OK.
The design variable is updated as specified.

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Netlist Generation--Generating and Regenerating a Netlist

Related Topics
Launching SystemVerilog Netlister
SystemVerilog Netlister Graphical User Interface
Editing Design Variables Form

Generating and Regenerating a Netlist

To generate a netlist of a selected design:
After setting up options and variables for the selected design, click Netlist in the Actions group
box of the SystemVerilog Netlister window.
SystemVerilog Netlister does the following:

Generates the netlist and stores it in the <projDir>/<lib>_<cell>_<view>/netlist

directory.
Enables the View button to allow viewing the netlist file.

By default, SystemVerilog Netlister creates the netlist.sv file in the ./sv-

netlist/<lib>_<cell>_<view>/netlist directory.

To regenerate the netlist:

In the Actions group box, select one of the following:
Incremental: Netlists only the changes that you make to the design or the settings. In
case of large designs, this mode of netlist generation highly improves the performance.
All: Recreates the complete netlist. In case of large designs, this mode of netlist
generation might decrease the performance.

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Netlist Generation--Viewing a Netlist

Related Topics

SystemVerilog Netlister Graphical User Interface

Launching SystemVerilog Netlister
Netlist Generation Flow in SystemVerilog Netlister

Viewing a Netlist
A netlist contains the connectivity information of a design. To view the netlist of your design:
In the Actions group box of the SystemVerilog Netlister window, click View.
The netlist.sv file opens.

The following figure illustrates how SystemVerilog Netlister displays the netlist file:

Related Topics
Launching SystemVerilog Netlister
SystemVerilog Netlister Graphical User Interface
Netlist Generation Flow in SystemVerilog Netlister

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Netlist Generation--State Management

State Management
You can save the current state of your settings or load saved states of settings in SystemVerilog
Netlister. It is useful when you want to avoid repeated setups of netlisting settings.
To save a state with the specified settings:
1. In the Settings group box of the SystemVerilog Netlister window, click Save State. The Save
State form appears.

2. In the State field, specify a new name for the current state.
3. Click OK.
The current settings are saved as a state in SystemVerilog Netlister.
To load a saved state when you launch SystemVerilog Netlister:
1. In the Settings group box of the SystemVerilog Netlister window, click Load State. The Load
State form appears.

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Netlist Generation--ATPG Compatible Verilog Netlists

2. In the State list, select the name of the state that you want to load.
3. Click OK.
The saved state is loaded in SystemVerilog Netlister.

Related Topics
Save State Form
Load State Form
Launching SystemVerilog Netlister
SystemVerilog Netlister Graphical User Interface

ATPG Compatible Verilog Netlists

The primary responsibility of engineers is to deliver scan patterns with complete confidence in their
accuracy. Automatic Test Pattern Generation (ATPG) tools are used to generate scan patterns.
Scan pattern generation as a process requires three inputs: the netlist of the design, ATPG tool
configuration files, and the definition of the library cells used.
However, due to limited support for behavioral constructs, usually ATPG tools cannot use Verilog
definitions of library cells except Verilog-1995 structural netlists. As a result, the library cells must
be defined in a tool-specific language or in a simpler, structural form of Verilog.
Virtuoso SystemVerilog Netlister lets you generate netlists of Verilog text files that are compatible

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Netlist Generation--Generating ATPG Compatible Verilog Netlists

with the ATPG technology. These netlists let you find an input or test sequence in Verilog text files.
The ATPG functionality within Virtuoso SystemVerilog Netlister has the following main features:
All text views must be Verilog constructs. Views created in other languages are not supported.
All nets are defined as wire in the netlist.
All parameters of cells or instances are ignored and are not printed in netlist.
All instance arrays are expanded by default.
Aliases can be printed using tran statements instead of using cds_alias, cds_thru, or assign
statements.
Generates a single netlist file. This netlist file contains the Verilog modules created from the
schematic and the Verilog modules from the text views. Cells with same names from different
libraries and different views are generated in a single netlist file with unique names.

Related Topics
Generating ATPG Compatible Verilog Netlists
Verilog Tab
enableVerilogATPG
useTranForCdsAliasThru
vlogCompatVersion

Generating ATPG Compatible Verilog Netlists

To generate an ATPG compatible netlist using the SystemVerilog Netlister graphical interface:
1. Launch SystemVerilog Netlister.
2. Click Browse in the Design group box to specify a design.
3. Click the Open Option Form button in the Settings group box to specify the netlisting options.
The SystemVerilog Netlister Options form appears.
4. Select the Verilog tab.
5. Select Create ATPG compatible netlist.
6. Click OK.

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Netlist Generation--Importing a SystemVerilog Package File

7. Click the Netlist button in the Actions group box.

The ATPG compatible netlist is generated.
To generate an ATPG compatible netlist using the SystemVerilog Netlister batch mode:
1. Include the following in the .cdsinit file.
envSetVal("digitalSim.netlisterOpts" "enableVerilogATPG" 'boolean t)

2. Run the following command in the terminal window.

runsv -lib topLib -cell topCell -view config_sv -netlist -rundir runsv_run

The ATPG compatible netlist is generated.

Related Topics

ATPG Compatible Verilog Netlists

Verilog Tab
enableVerilogATPG
useTranForCdsAliasThru
vlogCompatVersion

Importing a SystemVerilog Package File

Before you import SystemVerilog package files into your design for netlisting, ensure that your
design has a package file, for example, global_package.sv, and a systemVerilog view that has
imported this package file.
To import a package:
1. In the Library Manager window:
a. Create a new systemVerilogPackage view by choosing File – New – Cell View.
The New File form opens.
b. Specify the library and cell name in their respective fields.
c. In the View list, select systemVerilogPackage.

d. Click OK.
The New File form closes, and the View list in the Library Manager shows the new view.

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Netlist Generation--Importing a SystemVerilog Package File

e. Double-click the systemVerilogPackage view.

The view opens with an empty package module in Virtuoso Text Editor.
2. In the Virtuoso Text Editor window:
a. Choose File – Open.
The Open File form opens.
b. Select the global_package.sv package file and open it in a new tab.
c. Copy the contents of the package file and paste them into the package module of the
systemVerilogPackage view.

d. Click the Check and Save button on the toolbar.

Correct any errors that are reported.
e. Open the systemVerilog view in a new tab.
This is the view that has imported the package file.
f. Click the Check and Save icon on the toolbar.
Ensure that no errors are reported.
3. In the SystemVerilog Netlister window:
a. In the Setting group box, click Open Option Form.
This opens the SystemVerilog Netlister Options form and shows the Netlister tab.
b. On the Netlister page, select Enable auto package importing.
c. Click OK to close the SystemVerilog Netlister Options form.
d. In the Action group box, click Netlist.
Ensure that no errors are reported.
The package file is imported into your design.

Related Topics

Launching SystemVerilog Netlister

SystemVerilog Netlister Graphical User Interface
SystemVerilog Netlister Options Form

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Netlist Generation--Specifying Additional xrun Arguments in SystemVerilog Netlister

Specifying Additional xrun Arguments in

SystemVerilog Netlister
To specify additional xrun arguments in the netlisting settings in SystemVerilog Netlister:
1. In the SystemVerilog Netlister window, click Browse to specify a design.
The fields in the window are populated with the design details.
2. Click Open Options Form to access the netlisting settings.
3. In the Open Options Form window, click the Miscellaneous tab.
4. In the Miscellaneous page, click Additional Arguments.
The Additional Arguments form opens.

5. Specify valid xrun arguments in the Additional Arguments form.

These arguments are appended to the xrunArgs file that is generated. If Create binding files
for xrun only is enabled, SystemVerilog Netlister appends these additional arguments to both
the xrunArgs and xrunArgs_vy files.

6. Click OK.
The Additional Arguments form closes.

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Netlist Generation--DataType Propagation

Related Topics

Launching SystemVerilog Netlister

SystemVerilog Netlister Graphical User Interface
Additional Arguments Form

DataType Propagation
The SystemVerilog Netlister allows you to modify the dataType, portKind, and isUnpacked
properties, which are specific to an instance.
The datatype can be propagated from the following:
From text views
From instance ports on the symbol (place master).
From instance ports in the schematic
When ignoreDataType is set to t, the dataType, portKind, and isUnpacked properties are ignored.
Instead, the dataType information that is propagated from the bottom-level cell to the top-level cell is
considered.
You can add the ignoreDataType property on a specific instance terminal in the schematic. If this
property is selected, the SystemVerilog Netlister will not print the Master Value and the Local Value.
Additionally, you can modify the local values of the dataType, portKind, and isUnpacked port
properties that are associated with a specific instance of a cell.
The following table clearly describes the impact of enabling and disabling the ignoreDataType
property on the port of an instance in different scenarios:

Condition Additional Result

Condition

ignoreDataType The master values and local values of dataType,

= t portKind, and isUnpacked are ignored. Instead,
dataType information propagated from the bottom
cell to the top cell is used.

ignoreDataType The local value of The local value of the specific instance is used
= nil dataType is set to cu instead of the value set on the symbol cell.
stom_value.

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Netlist Generation--DataType Propagation

ignoreDataType The local values are The master value of the symbol cell property is
= nil not set for dataType, used.
portKind, and
isUnpacked.

Example
Consider the input port I2 in the following schematic and the related condition scenarios that follow.

When ignoreDataType is set to t on the port of an instance

When you set ignoreDataType to t on I2, the master and local values of dataType and
portKind are ignored. In such a case, dataType information that is propagated from the
bottom-level cell to the top-level cell is used.

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Netlist Generation--DataType Propagation

The following example shows how the netlist displays the port information in this scenario:
module tb_w_voltage (
output wire logic VOUT0,
output wire logic VOUT1,
output wire logic VOUT2,
input wire logic GNDA_ADC,
input voltage VIN0,
input voltage VIN1
);
Here, the wire logic value is derived from the dataType property of the bottom-level cell.

When ignoreDataType is set to nil and the local value of dataType is set to
custom_value
When you set ignoreDataType to nil on I2 and the local value dataType to myvoltage, the
local value myvoltage of the specific instance is used, instead of the master value voltage that
is set on the symbol cell.

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The following example shows how the netlist displays the port information in this scenario:
module tb_w_voltage (
output wire logic VOUT0,
output wire logic VOUT1,
output wire logic VOUT2,
input myvoltage GNDA_ADC,
input voltage VIN0,
input voltage VIN1
);
Here, the local value overrides the master value.
When ignoreDataType is set to nil and the local value of dataType is not set
When you set ignoreDataType to nil on I2 and the local values of dataType and portKind are
not set, the master value voltage of the symbol cell property is used.

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Netlist Generation--DataType Propagation

The following example shows how the netlist displays the port information in this scenario:
module tb_w_voltage(
output wire logic VOUT0,
output wire logic VOUT1,
output wire logic VOUT2,
input voltage GNDA_ADC,
input voltage VIN0,
input voltage VIN1
);
Here, the property of the symbol cell (master value) is used.

Related Topics

Launching SystemVerilog Netlister

SystemVerilog Netlister Graphical User Interface

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Netlist Generation--Netlist Customization Using the .simrc File

Netlist Customization Using the .simrc File

SystemVerilog Netlister supports customizing netlist generation by setting the following variables in
the .simrc file.

SystemVerilog Netlister might not always support all the variables in the .simrc file that are
supported by the SI Netlister.

Variable Description

hnlGetSimulator Returns SystemVerilog Netlister for SystemVerilog Netlister.

hnlUserShortCVList Allows specifying a shorting list that contains devices that need to be
shorted.
Example: hnlUserShortCVList=list(list(<libName> <cellName>))

simVerilogEnableEscapeNameMapping

Includes escaped names in the netlist. It also allows you to escape

names that are reserved keywords in SystemVerilog.
Default value is t.
Example: If you have a module "assign" in your design, and you set
simVerilogEnableEscapeNameMapping to t, it is mapped to "\assign" in
the netlist.

simSVPortPropertyList

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Netlist Generation--Netlist Customization Using the .simrc File

When enabled, allows specifying the dataType and portKind properties

on a symbol cell. For example:
simSVPortPropertyList = '( ("analogLib" "res" "symbol" "PLUS
real var" "MINUS wrealdriver nil") )

Here,
"analogLib" indicates the library name

"res" indicates the cell name

"symbol" indicates the view name

"PLUS real var" indicates that datatype is set to real, and portKind
is set to var on port PLUS;

"MINUS wrealdriver nil" indicates that only the datatype property is

set to wrealdriver on port MINUS, leaving the portKind property blank.

vlogExpandIteratedInst

When set to nil, allows instances in the array in the following format:
"I_iter[0:2]"

When set to t, allows splitting iterated instances in the following format:

I_iter_1 …
I_iter_2 …
I_iter_3 …

hnlVerilogDumpIncludeFilesInNetlist ​

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When set to t, copies the content of an included HDL file directly to the
netlist, instead of inserting an `include statement.
The contents of the text cellviews in the design hierarchy are copied to
the netlist. Any file specified in the Pre-Module Include File or In-Module
Include File option of the SystemVerilog Netlister Options form is also
copied to the netlist.
This variable works only in single netlist file mode. It does not support
recursive inclusion of text files. Consider that fileA.sv includes
fileB.sv. If you copy the contents of fileA.sv in the netlist using this
variable, the contents of fileB.sv will not be copied in the netlist.
Default: nil

simVerilogGenerateSingleNetlistFile ​

A flag to generate a single Verilog netlist containing multiple modules

instead of one netlist per module. By default, this flag is set to nil. If set
to t, the netlister generates a single Verilog netlist file in the current
simulation run directory with the name netlist.

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hnlUserStopCVList List of user specified cellviews, which are treated as stop views while
netlisting a design. You can specify this list in the .simrc file. Although
instances of such a cellview appear in a netlist, the cellview module is
not printed in the netlist.
In the example below, all the cellviews in the libN library will be treated
as stop views. However, in the lib1 library, only the cell1, cell2, and
cell3 cellviews will be treated as stop views.

hnlUserStopCVList = list

;;; all cells from this library

"libN"
;;; cell1, cell2 and cell3 from lib1 list("lib1" "cell1"
"cell2" "cell3"s)

The list should have only one entry for each library, listing all the
cellviews that need to be treated as stop views.

vlogifDeclareGlobalNetLocal

A flag to declare global signals locally. When you disable this flag, the
netlister uses the default signals (Global Power Nets and Global
Grounds Nets). If the vlogifDeclareGlobalNetLocal flag is set to nil,
global signals are declared in the cds_globals module.

The SystemVerilog Netlister does not support the hnlUserStubCVList variable.

Related Topics

The .simrc File

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SystemVerilog Netlister Forms

3
SystemVerilog Netlister Forms

This chapter describes the various forms in the SystemVerilog Netlister environment. These
include:
Additional Arguments Form
Editing Design Variables Form
Export Environment Variables Form
Load State Form
Save State Form
Select Design/Directory Form
SystemVerilog Netlister Graphical User Interface
SystemVerilog Netlister Options Form

Additional Arguments Form

The following table describes the columns available in the Additional Arguments form:

Field Description

Enable Enables the selected xrun argument.

Additional Specifies the name of the xrun argument. Click the field to add a new argument
Argument name or edit an existing argument name.

Related Topics

SystemVerilog Netlister Forms

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SystemVerilog Netlister Forms--Editing Design Variables Form

Editing Design Variables Form

The following table describes the fields and buttons available in the Editing Design Variables
form:

Field Description

Name Specifies a name for the design variable.

Value(Expr) Specifies a value for the design variable.

Add Lets you add a variable.

Delete Lets you delete a variable.

Change Specifies the name of the xrun argument. Click the field to add a new argument
name or edit an existing argument name.

Design Lists the design variables that exist in the design.

Variables

Related Topics
SystemVerilog Netlister Forms

Export Environment Variables Form

The following table describes the field available in the Export Environment Variables form.

Field Description

Save Lets you specify the file to which the GUI settings and options available in the
to file SystemVerilog Netlister form are exported as environment variables in a format similar
to that of the .cdsinit file.

Related Topics
SystemVerilog Netlister Graphical User Interface
Exporting SystemVerilog Netlister Settings as Environment Variables

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SystemVerilog Netlister Forms--Load State Form

SystemVerilog Netlister Forms

Load State Form

Use the Load State form to load previously saved settings or a state to the current setup. The form
contains the following fields and lists:

Field Description

Library Specifies the name of the library that contains the design.

Cell Specifies the name of the cell in the selected library for which the state needs to be
saved.

State Specifies the name of the state that must be saved.

Cells Lists the names of all cells in the selected library.

Related Topics
SystemVerilog Netlister Forms

Save State Form

Use the Save State form to save the settings from the current setup as a state. The form contains the
following fields and lists:

Field Description

Library Specifies the name of the library that contains the design.

Cell Specifies the name of the cell in the selected library for which the state needs to be
saved.

State Specifies the name of the state that must be saved.

Cells Lists the names of all cells in the selected library.

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SystemVerilog Netlister Forms--Select Design/Directory Form

Related Topics
SystemVerilog Netlister Forms

Select Design/Directory Form

The Select Design/Directory form contains the following fields:

Field Description

Library Specifies the name of the library that contains the design.

Cell Specifies the name of the cell in the selected library that contains the design.

View Specifies the view in the selected library and cell.

Project directory

Specifies the name of the project directory. If the project directory name already exists,
a dialog box is displayed to confirm if the previous project directory must be
overwritten. If you choose not to overwrite the project directory, specify a new name in
the text field.
The default project directory name is sv-netlist.

The project directory contains various subdirectories. When you select a library,
cell, and view in the Select Design/Directory window, a new subdirectory is
created in the project directory. The subdirectory derives its name from the
library, cell, and view names that you select in the design. For example, the
typical directory structure of a design is as follows: projectDir/lib_cell _view /netl
ist

Related Topics
SystemVerilog Netlister Forms

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SystemVerilog Netlister Forms--SystemVerilog Netlister Graphical User Interface

SystemVerilog Netlister Graphical User Interface

The graphical user interface of SystemVerilog Netlister can be categorized into the following main
sections:

Section Description

Menus Displays the Commands and Help menus.

Commands: Contains the following commands:
HDL Package Setup: Opens the Virtuoso HDL Package Setup form.
Export Environment Variables: Opens the Export Environment Variables form.
Close: Exits the graphical user interface of SystemVerilog Netlister.
Help: Opens product documentation.

Design Specifies the library, cell, and view of the top-level design.

You can select only configuration views.

Setting Specifies the options and design variables required for netlist generation.

Actions Specifies the netlisting actions. You can generate or regenerate a netlist to view the
netlisting results.

Status Displays the current status of the selected item.

bar

Related Topics
Specifying a Design for Netlist Generation
Configuring Netlist Generation Options
Configuring Design Variables
Netlist Generation Flow in SystemVerilog Netlister
Export Environment Variables Form

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SystemVerilog Netlister Forms--SystemVerilog Netlister Options Form

SystemVerilog Netlister Options Form

The SystemVerilog Netlister Options form lets you specify the options for running SystemVerilog
Netlister. The form contains the following tabs.

Tab Description

Netlister Tab Lets you specify port declaration format, default nettype, enablement
of datatype and array type propagation, auto-package import,
merging text files to a single netlist, and values for global ground and
power nets and pre-module and in-module include files.

Miscellaneous Lets you specify the hdl.var file, pre-compiled libraries, creation of
Tab argument files, creation of binding files for xrun, printing the global
time scale, and additional arguments.

Verilog Tab Lets you specify options for generating Verilog netlists.

Netlister Tab
Merge text source to single netlistThe following table describes the fields available on the Netlister
tab of the SystemVerilog Netlister Options form.

Field Description

Port Specifies one of the following port declaration formats:

Declaration
Non-ANSI (default)
Format
ANSI
When hnlPrintNonAnsiSV is set to nil in the .simrc file and datatype
propagation is enabled, port declaration can be done only in ANSI format.

Default Specifies one of the following nettypes to netlist the nets on the schematic:
Nettype
interconnect (default): If no nettype is propagated, the net and the bus are
declared explicitly as interconnect.
wire: A net without another explicitly set type is not declared. Here, only the
bus is declared. Single-bit wires are not saved in the declaration because
Xcelium resolves signals that are not explicitly declared to be of type wire.

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Enable Enables datatype propagation. It is not selected by default.

Datatype
Selecting this check box allows the propagation of both packed or unpacked
Propagation
and datatype or portKind properties. When not selected and netType properties
are not set on the schematic nets, the default nettype that is currently set is
printed in the netlist.
Datatype propagation and default net type selection result in the following
scenarios:
When the netType property is explicitly placed on a net and Enable Datatype
Propagation is selected, the propagated datatype is ignored and the explicit
nettype defined on the net is printed in the generated netlist. A warning is
displayed in the CIW if there is a conflict between the nettype set on
schematic net and the propagated nettype.
When datatype propagation is enabled and netType property is not set on
schematic nets, the propagated datatype or portKind properties for these
nets are printed in netlist.
When datatype propagation is disabled, and netType property is set on
schematic nets, the value of netType property is printed for these nets in the
netlist. Otherwise, the default netType is printed.

When datatype propagation is enabled, and a net has a propagated

datatype as well as a netType property placed on it, the netType property
value is printed for the net. To print the propagated datatype while ignoring
the netType property set on nets, specify the netType value to be ignored in
the netTypes to ignore on schematic nets field.

Enable Array Enables array type propagation. It is not selected by default.

Type
Selecting this check box disables the Enable Datatype Propagation check box
Propagation
and allows recognition of packed and unpacked arrays. As a result, the
Only
SystemVerilog Netlister prints a bus connected to a port of type real or a
nettype, as unpacked, and propagates the unpacked property up to the top
level. However, the datatype of the port is not propagated.

Expand Prints iterated instances in expanded form in the netlist.

Iterated
Instances

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Enable auto Enables the auto-package handling feature, which allows SystemVerilog
package Netlister to automatically search and find the SystemVerilog package files on
importing which the systemverilog modules in the design depend. It is not selected by
default.
Alternatively, you can manually pre-compile a package into a library that you
define.

Merge text Merges the text files to create a single and self-contained netlist.sv file. This
source to file includes the netlist from the schematic and the original source files from the
single netlist text view.
If you select the Merge text source to single netlist check box, the contents of the
cds_alias.sv or the cds_globals.sv file are printed in the netlist.sv file.

However, deselecting the Merge text source to single netlist check box results
in the following:
The absolute path of cds_alias.sv is printed in textInputs but removed from
the netlist.sv file.

The absolute path of cds_global.sv is printed in xrunArgs but removed from

the netlist.sv file.

When simVerilogGenerateSingleNetlistFile is set to t in the .simrc file, it

generates a single merged netlist, including cds_alias.sv and
cds_globals.sv, if these files exist. When set to nil, it generates a split
netlist.
When Pre-Module Include File or In-Module include File and Merge text
source to single netlist are selected, the contents of Pre-Module Include File
or In-Module Include File are saved in netlist.sv.

Rename Detects the cell name conflicts in schematic, Verilog, or SystemVerilog cells
cells with and renames the cells with naming conflicts in a single netlist file.
naming
conflicts This option is enabled only when Merge text source to single netlist check box
is selected.

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Print Prints the Verilog-2001 directives ‘begin_keywords "1364-2001" and

keyword ‘end_keywords for every text module of a verilog view in a single netlist file.
directives for
Verilog The option is enabled only when Merge text source to single netlist check box is
modules selected.

Output Specifies whether to save the design hierarchy details with the instances and
design components information for non-ATPG netlisting mode.
hierarchies
in XML
format

Split Netlist Generates split netlists for all modules in the design. For example, if the cell
File contains multiple modules, such as module1, module2...moduleN, instead of a
single netlist, separate netlists named module1.sv, module2.sv....moduleN.sv are
generated. By default, the option is deselected.

netTypes to Specifies the net types that must be ignored during netlising.
ignore on
schematic
nets

supply0 Specifies a value to set the global ground net. This value is saved in the
cds_globals.sv file.

This option supports only global signals in the design. Cross-checking with the
schematic is not supported.

supply1 Specifies a value to set the global power net. This value is saved in the
cds_globals.sv file.

This option supports only global signals in the design. Cross-checking with the
schematic is not supported.

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Pre-Module Specifies the file that the netlister must use as the include file before the module
Include File declaration in the netlist file generated for each hierarchical cellview.
To print the contents of the include file in the generated netlist file instead of
using the file inclusion directive 'include, set
hnlVerilogDumpIncludeFilesInNetlist to t.

When Merge text source to single netlist is selected, the contents of the
include file are also printed in a single netlist file even if
hnlVerilogDumpIncludeFilesInNetlist is not set.

Flag: vlogifPreModuleIncludeFile

In-Module Specifies the file that the netlister must use as an include file immediately after
Include File the module declaration in the netlist file generated for each hierarchical
cellview.
To print the contents of the include file in the generated netlist file instead of
using the file inclusion directive 'include, set
hnlVerilogDumpIncludeFilesInNetlist to t.

When Merge text source to single netlist is selected, the contents of the
include file are also printed in a single netlist file even if
hnlVerilogDumpIncludeFilesInNetlist is not set.

Flag: vlogifInModuleIncludeFile

Suppress Ignores the specified SystemVerilog Netlister messages of INFO or WARNING type
specific that start with the prefix VSVN-, AMS- and, VLOGNET- and does not print them in the
netlister log file and the CIW.
info/warnings
You can specify multiple SystemVerilog Netlister messages of INFO or WARNING
type as space-separated values.
The following example ignores the specified messages and does not print them
in the log file and the CIW.
VSVN-1206 VLOGNET-55

Netlist File Specifies the name of the generated netlist file. The default name of the
Name generated netlist is netlist.sv.

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SystemVerilog Netlister Forms--SystemVerilog Netlister Options Form

Miscellaneous Tab
The following table describes the fields available on the Miscellaneous tab of the SystemVerilog
Netlister Options form.

Field Description

hdl.var file Specifies the name of an hdl.var file to include the simulation options.
For more details on the hdl.var file, see The hdl.var File.

Pre- Specifies the name of a pre-compiled library. If you have a package definition, you
compiled can pre-compile the package into the same library or different libraries.
libraries
(-reflib) To manage text views of a design, pre-compile all the packages into a
library. You can use –reflib to include all the libraries that contain the pre-
compiled packages required in the design.

Create Creates the xrunArgs file and other standard binding files. This file includes
arguments netlist.sv, config.sv, textInputs, binding files, and other files, such as
file cds_globals.sv and cds_alias.sv. These files are generated during netlisting and
are needed for simulations.

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Create Select this check box only if you use xrun. Selecting this check box automatically
binding selects the Create arguments file check box and creates two sets of binding files in
files for the netlist directory: xrunArgs, xrunArgs_vy (compatible with Xcelium), and the
xrun only hdl.var, cds_xrun.lib and lib.map files.

Both xrunArgs and xrunArgs_vy include the following:

xrun argument vcfg_inst_precedence
xrun argument compcnfg
config.sv file

textInputs file

Additionally:
xrunArgs includes the lib.map file.

xrunArgs_vy includes the hdl.var and cdslib or cds_xrun.lib file.

If you specify an hdl.var file in the Miscellaneous tab of the SystemVerilog

Netlister Options form, this file is included in the hdl.var file that SystemVerilog
Netlister generates.

You do not need to select this check box if you use a third-party simulation
tool.

Print Prints the global timescale. By default, SystemVerilog Netlister does not print the
global timescale globally.
timescale
Enabling Print global timescale prints the following:
'timescale on the module header of each schematic cell in netlist

-timescale in the xrunArgs file if Create arguments file is enabled

Global sim Specifies the simulation time in global timescale. The possible values are 1, 10,
time and 100. The default is 1.
This field is enabled only when Print global timescale is selected.

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Unit for Specifies the unit to be used for simulation time in global timescale. The possible
global sim values are s, ms, us, ns, ps, fs. The default is ns.
time
This field is enabled only when Print global timescale is selected.

Global sim Specifies the simulation precision in global timescale. The possible values are 1,
precision 10, and 100. The default is 1.

This field is enabled only when Print global timescale is selected.

Unit for Specifies the unit to be used for simulation precision in global timescale. The
global sim possible values are s, ms, us, ns, ps, fs. The default is ns.
precision
This field is enabled only when Print global timescale is selected.

Additional Specifies additional xrun arguments.

Arguments

Related Topics

The hdl.var File

hdlVarFile
Importing a SystemVerilog Package File
Specifying Additional xrun Arguments in SystemVerilog Netlister
simVerilogGenerateSingleNetlistFile
hnlVerilogDumpIncludeFilesInNetlist

Verilog Tab
The following table describes the fields available on the Verilog tab of the SystemVerilog Netlister
Options form.

Field Description

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Create Enables the creation of ATPG compatible netlists in Virtuoso SystemVerilog

ATPG Netlister.
compatible
When the Create ATPG compatible netlist check box is selected, no changes are
netlist
made in the XML file. The file contains the instance information in a hierarchical
format under the <root> node, irrespective of whether the Output design
hierarchies in XML format check box is selected or not.

Use tran Prints tran statements for aliases or patches instead of using the cds_alias and
statement cds_thru and cds_thrualias constructs. All buses and concatenated bundles are
for aliasing expanded and printed in tran statements.

Text Checks the Verilog IEEE Standard compliance for text source in the design using
source Verilog command-line compilation options.
compliance
Possible values are as follows:
with xrun
None: Compiles text source files using xrun default standard.
Verilog-2001: Compiles text source files using the xrun option, -v2001.

Verilog-1995: Compiles text source files using the xrun option, -v1995.

The selected option is added to the xrun command line for mapi compilation
during netlisting. It is also printed in the xrunArgs files if the Create arguments file
option is enabled.

Add prefix Adds a predefined prefix to cell names in the generated netlist.
to cell
Possible values are as follows:
names
None: Default. Does not add prefix to cell names.
All: Adds the prefix specified in the Cell prefix name field to all cell names,
including the top cell and non-textual stopping cells. These non-textual
stopping cells are cells without module definitions.
Keep name of top cell and symbol cells: Adds the prefix specified in the Cell
prefix name field to all cell names, excluding names of the top cell and non-
textual stopping cells. These non-textual stopping cells are cells without
module definitions.

Cell prefix Specifies a prefix string for cell names. The prefix must start with either an
name alphabetic character or an underscore and the remaining string may contain only
alphanumeric characters or underscores.

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Related Topics

ATPG Compatible Verilog Netlists

Generating ATPG Compatible Verilog Netlists
enableVerilogATPG
useTranForCdsAliasThru
vlogCompatVersion
addPrefixToCells
cellPrefixName

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Environment Variables

4
Environment Variables

This chapter describes the environment variables that control the characteristics of the
SystemVerilog Netlister environment.

Compiler

createXrunArgs createXrunBinding hdlVarFile

refLib reUseHdlCompilationSetup

Elaborator

enableTimeScale simPrecision simPrecisionUnit

simTime simTimeUnit

NC-Verilog

addArgTableList vlogCompatVersion

Netlister

addPrefixToCells cellPrefixName defaultNettype

enableDataPropagate enableVerilogATPG expandIterateInst

genUniqCellNameIfConflict isPortInANSIFormat mergedNetlist

netlistNoWarn nettypesToIgnore outputXmlFile

printDirectivesForVerilog2001 printParamForTextInst termDirectionMismatch

termMismatch useTranForCdsAliasThru vlogSupply0Sigs

vlogSupply1Sigs

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Environment Variables--addArgTableList

addArgTableList
digitalSim.ncverilogOpts addArgTableList string ""

Description

Controls the default setting for the Create arguments file check box in the SystemVerilog Netlister
Options form.
The default is "".

GUI Equivalent

Command Open Options Form

Form Field Create arguments file

Examples
envGetVal("digitalSim.ncverilogOpts" "addArgTableList")

envSetVal("digitalSim.ncverilogOpts" "addArgTableList" 'string "argList1")

Related Topics
Configuring Netlist Generation Options

addPrefixToCells
digitalSim.netlisterOpts addPrefixToCells string { "None" | "All" | "Keep name of top
cell and symbol cells" }

Description
Adds a predefined prefix to cell names in the generated netlist.
Possible values are as follows:
None: Default. Does not add a prefix to cell names, even if it is defined using the Cell prefix

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Environment Variables--cellPrefixName

name field or the cellPrefixName environment variable.

All: Addsthe prefix specified using the Cell prefix name field or the cellPrefixName
environment variable to all cell names, including the top cell and non-textual stopping cells.
These non-textual stopping cells are cells without module definitions.
Keep name of top cell and symbol cells: Adds the prefix specified in the Cell prefix name
field or the cellPrefixName environment variable to all cell names, excluding names of the top
cell and non-textual stopping cells. These non-textual stopping cells are cells without module
definitions.
The default is "None".

GUI Equivalent

Command Open Options Form

Form Option Add prefix to cell names

Examples
envGetVal("digitalSim.netlisterOpts" "addPrefixToCells")

envSetVal("digitalSim.netlisterOpts" "addPrefixToCells" 'string "All")

envSetVal("digitalSim.netlisterOpts" "addPrefixToCells" 'string "Keep name of top cell

and symbol cells")

Related Topics

Configuring Netlist Generation Options

cellPrefixName
digitalSim.netlisterOpts cellPrefixName string { "prefixstring" }

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Environment Variables--createXrunArgs

Description
Specifies a prefix for cell names. The prefix must start with either an alphabetic character or an
underscore and the remaining string may contain only alphanumeric characters or underscores.
This setting applies to the selection made using the Add prefix to cell names check box in the
Verilog tab of the SystemVerilog Netlister Options form or the addPrefixToCells environment
variable.
The default is "".

GUI Equivalent

Command Open Options Form

Form Option Cell prefix name

Examples
envGetVal("digitalSim.netlisterOpts" "cellPrefixName")

envSetVal("digitalSim.netlisterOpts" "cellPrefixName" 'string "cds_")

Related Topics
Configuring Netlist Generation Options

createXrunArgs
digitalSim.compilerOpts createXrunArgs boolean { t | nil }

Description
Controls the default setting for the Create arguments file check box in the SystemVerilog Netlister
Options form.

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Environment Variables--createXrunBinding

The default is nil.

GUI Equivalent

Command Open Options Form

Form Field Create arguments file

Examples
envGetVal("digitalSim.compilerOpts" "createXrunArgs"

envSetVal("digitalSim.compilerOpts" "createXrunArgs" 'boolean t)

Related Topics
Configuring Netlist Generation Options

createXrunBinding
digitalSim.compilerOpts createXrunBinding boolean { t | nil }

Description

Creates the hdl.var and cds_xrun.lib files in the netlist directory when you use xrun.
The default is nil.

GUI Equivalent

Command Open Options Form

Form Field Create binding files for xrun only

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Environment Variables--defaultNettype

Examples
envGetVal("digitalSim.compilerOpts" "createXrunBinding")

envSetVal("digitalSim.compilerOpts" "createXrunBinding" 'boolean t)

Related Topics
Configuring Netlist Generation Options

defaultNettype
digitalSim.netlisterOpts defaultNettype string { "interconnect" | "wire" }

Description
Sets the default net type to netlist nets on the schematic.
interconnect prints all interconnects in the netlist.

wire prints all wires and ports in the netlist.

The default is interconnect.

GUI Equivalent

Command Open Options Form – Netlister

Form Field Default Nettype

Examples
envGetVal("digitalSim.netlisterOpts" "defaultNettype")envSetVal("digitalSim.netlisterOpts"
"defaultNettype" 'string "wire")

Related Topics
Configuring Netlist Generation Options

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Environment Variables--enableDataPropagate

enableDataPropagate
digitalSim.netlisterOpts enableDataPropagate boolean { t | nil }

Description
Controls the datatype propagation in SystemVerilog Netlister. The default is nil.

GUI Equivalent

Command Open Options Form – Netlister

Form Field Enable Datatype Propagation

Examples
envGetVal("digitalSim.netlisterOpts" "enableDataPropagate")

envSetVal("digitalSim.netlisterOpts" "enableDataPropagate" 'boolean t)

Related Topics

Configuring Netlist Generation Options

enableVerilogATPG
digitalSim.netlisterOpts enableVerilogATPG boolean { t | nil }

Description
Enables the creation of ATPG compatible netlists in Virtuoso SystemVerilog Netlister.
The default is nil.

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Environment Variables--expandIterateInst

GUI Equivalent

Command Open Options Form – Verilog

Form Field Create ATPG compatible netlist

Examples
envGetVal("digitalSim.netlisterOpts" "enableVerilogATPG")

envSetVal("digitalSim.netlisterOpts" "enableVerilogATPG" 'boolean t)

Related Topics

Configuring Netlist Generation Options

expandIterateInst
digitalSim.netlisterOpts expandIterateInst boolean { t | nil }

Description

Prints all iterated instances in expanded form in the netlist.

The default is nil.

GUI Equivalent

Command Open Options Form – Netlister

Form Field Expand Iterated Instances

Examples
envGetVal("digitalSim.netlisterOpts" "expandIterateInst")

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Environment Variables--enableTimeScale

envSetVal("digitalSim.netlisterOpts" "expandIterateInst" 'boolean t)

Related Topics

Configuring Netlist Generation Options

enableTimeScale
digitalSim.elabOpts enableTimeScale boolean { t | nil }

Description
Enables printing the global time scale.
The default is nil.

GUI Equivalent

Command Open Options Form – Miscellaneous

Form Field Print Global Time Scale

Examples
envGetVal("digitalSim.elabOpts" "enableTimeScale")

envSetVal("digitalSim.elabOpts" "enableTimeScale" 'boolean t)

Related Topics

Configuring Netlist Generation Options

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Environment Variables--hdlVarFile

hdlVarFile
digitalSim.compilerOpts hdlVarFile string { "pathName" }

Description

Specifies the location of the hdl.var file.

The default is "".

GUI Equivalent

Command Open Options Form – Miscellaneous

Form Field hdl.var file

Examples
envGetVal("digitalSim.compilerOpts" "hdlVarFile")

envSetVal("digitalSim.compilerOpts" "hdlVarFile" 'string "/myDesigns/user1/hdl.var")

Related Topics
Configuring Netlist Generation Options
The hdl.var File
SystemVerilog Netlister Options Form

isPortInANSIFormat
digitalSim.netlisterOpts isPortInANSIFormat string { "Non-ANSI" | "ANSI" }

Description

Controls if the port declaration is in Non-ANSI or ANSI format.

The default is Non-ANSI.

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Environment Variables--mergedNetlist

GUI Equivalent

Command Open Options Form – Netlister

Form Field Port Declaration Format

Examples
envGetVal("digitalSim.netlisterOpts" "isPortInANSIFormat")

envSetVal("digitalSim.netlisterOpts" "isPortInANSIFormat" 'string "ANSI")

Related Topics
Configuring Netlist Generation Options

mergedNetlist
digitalSim.netlisterOpts mergedNetlist boolean { t | nil }

Description

Merges the text files to create a single and self-contained netlist. This netlist includes the netlist
from the schematic and the original source files from the text view.
The default is nil.

GUI Equivalent

Command Open Options Form – Netlister

Form Field Merge text source to single netlist

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Environment Variables--nettypesToIgnore

Examples
envGetVal("digitalSim.netlisterOpts" "mergedNetlist")

envSetVal("digitalSim.netlisterOpts" "mergedNetlist" 'boolean t)

Related Topics
Configuring Netlist Generation Options

nettypesToIgnore
digitalSim.netlisterOpts nettypesToIgnore string ""

Description
Controls the net types to be ignored.
The default is "".

GUI Equivalent

Command Open Options Form – Netlister

Form Field netTypes to ignore on schematic nets

Examples
envGetVal("digitalSim.netlisterOpts" "nettypesToIgnore")

envSetVal("digitalSim.netlisterOpts" "nettypesToIgnore" 'string "wired")

Related Topics
Configuring Netlist Generation Options

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Environment Variables--refLib

refLib
digitalSim.compilerOpts refLib string ""

Description
Allows the selection of a pre-compiled library from a specific location. If you have a package
definition, you can pre-compile the package into a single library or multiple libraries.
The default is "".

GUI Equivalent

Command Open Options Form – Netlister

Form Field Pre-compiled libraries (-reflib)

Examples
envGetVal("digitalSim.compilerOpts" "refLib")

envSetVal("digitalSim.compilerOpts" "refLib" 'string "/myDesigns/user1/")

Related Topics

Configuring Netlist Generation Options

reUseHdlCompilationSetup
digitalSim.compilerOpts reUseHdlCompilationSetup boolean { t | nil }

Description
Controls whether the HDL package setup is reused by Virtuoso SystemVerilog Netlister.
The default is nil.

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Environment Variables--simPrecision

GUI Equivalent

Command Open Options Form – Miscellaneous

Form Field Reuse HDL package setup

Examples
envGetVal("digitalSim.compilerOpts" "reUseHdlCompilationSetup")

envSetVal("digitalSim.compilerOpts" "reUseHdlCompilationSetup" 'boolean t)

Related Topics

Configuring Netlist Generation Options

simPrecision
digitalSim.elabOpts simPrecision int pre-defined_numeric_value

Description

Specifies the simulation precision in global timescale. Possible values are 1, 10, and 100.
The default is 1.

GUI Equivalent

Command Open Options Form – Miscellaneous

Form Field Global sim precision

Examples
envGetVal("digitalSim.elabOpts" "simPrecision")

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Environment Variables--simPrecisionUnit

envSetVal("digitalSim.elabOpts" "simPrecision" 'int 100)

Related Topics

Configuring Netlist Generation Options

simPrecisionUnit
digitalSim.elabOpts simPrecisionUnit string { "s" | "ms" | "us" | "ns" | "ps" | "fs"}

Description

Specifies the unit to be used for simulation precision in global timescale.

The default is "ns".

GUI Equivalent

Command Open Options Form – Miscellaneous

Form Field Unit for global sim precision

Examples
envGetVal("digitalSim.elabOpts" "simPrecisionUnit")

envSetVal("digitalSim.elabOpts" "simPrecisionUnit" 'string "s")

envSetVal("digitalSim.elabOpts" "simPrecisionUnit" 'string "ms")

envSetVal("digitalSim.elabOpts" "simPrecisionUnit" 'string "us")

envSetVal("digitalSim.elabOpts" "simPrecisionUnit" 'string "ps")

envSetVal("digitalSim.elabOpts" "simPrecisionUnit" 'string "fs")

Related Topics

Configuring Netlist Generation Options

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Environment Variables--simTime

simTime
digitalSim.elabOpts simTime int pre-defined_numeric_value

Description
Specifies the simulation time in global timescale. Possible values are 1, 10, and 100.
The default is 1.

GUI Equivalent

Command Open Options Form – Miscellaneous

Form Field Global sim time

Examples
envGetVal("digitalSim.elabOpts" "simTime")

envSetVal("digitalSim.elabOpts" "simTime" 'int 100)

Related Topics

Configuring Netlist Generation Options

simTimeUnit
digitalSim.elabOpts simTimeUnit string { "s" | "ms" | "us" | "ns" | "ps" | "fs"}

Description
Specifies the unit to be used for simulation time in global timescale.
The default is "ns".

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Environment Variables--termMismatch

GUI Equivalent

Command Open Options Form – Miscellaneous

Form Field Unit for global sim time

Examples
envGetVal("digitalSim.elabOpts" "simTimeUnit")

envSetVal("digitalSim.elabOpts" "simTimeUnit" 'string "s")

envSetVal("digitalSim.elabOpts" "simTimeUnit" 'string "ms")

envSetVal("digitalSim.elabOpts" "simTimeUnit" 'string "us")

envSetVal("digitalSim.elabOpts" "simTimeUnit" 'string "ps")

envSetVal("digitalSim.elabOpts" "simTimeUnit" 'string "fs")

Related Topics

Configuring Netlist Generation Options

termMismatch
digitalSim.netlisterOpts termMismatch string { "ignore" | "warning" | "error" }

Description

Controls the tool behavior when terminal mismatch is found between the switch master and the
place master. The valid values are ignore, warning, and error,
ignore: Ignores any terminal mismatch found between the switch master and place master in
the text view and continues netlisting.
warning: Displays a warning message when terminal mismatch is found between the switch
master and place master in the text view and continues netlisting.
error: Displays an error if terminal mismatch is found between the switch master and place
master in the text view and stops netlisting.

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Environment Variables--termDirectionMismatch

The default is error.

GUI Equivalent

None

Examples
envGetVal("digitalSim.netlisterOpts" "termMismatch")

envSetVal("digitalSim.netlisterOpts" "termMismatch" 'string "ignore")

envSetVal("digitalSim.netlisterOpts" "termMismatch" 'string "warning")

Related Topics

Configuring Netlist Generation Options

termDirectionMismatch
digitalSim.netlisterOpts termDirectionMismatch string { "ignore" | "warning" | "error" }

Description

Controls the tool behavior when mismatch in terminals directions is found between the switch
master and the place master. The valid values are ignore, warning, and error,
ignore:Ignores any mismatch in terminals directions found between the switch master and
place master in the text view and continues netlisting.
warning: Displays a warning message when mismatch in terminals directions is found
between the switch master and place master in the text view and continues netlisting.
error: Displays an error if mismatch in terminals directions is found between the switch
master and place master in the text view and stops netlisting.
The default is error.

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Environment Variables--useTranForCdsAliasThru

GUI Equivalent
None

Examples
envGetVal("digitalSim.netlisterOpts" "termDirectionMismatch")

envSetVal("digitalSim.netlisterOpts" "termDirectionMismatch" 'string "ignore")

envSetVal("digitalSim.netlisterOpts" "termDirectionMismatch" 'string "warning")

Related Topics

Configuring Netlist Generation Options

useTranForCdsAliasThru
digitalSim.netlisterOpts useTranForCdsAliasThru boolean { t | nil }

Description
Prints tran statements for aliases or patches instead of using the cds_alias and cds_thru
constructs. This option is only available when the Create ATPG compatible netlist option is enabled
on the Verilog tab of the Virtuoso SystemVerilog Netlister Options form.
The default is nil.

GUI Equivalent

Command Open Options Form – Verilog

Form Field Use tran statement for aliasing

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Environment Variables--vlogCompatVersion

Examples
envGetVal("digitalSim.netlisterOpts" "useTranForCdsAliasThru")

envSetVal("digitalSim.netlisterOpts" "useTranForCdsAliasThru" 'boolean t)

Related Topics

Configuring Netlist Generation Options

vlogCompatVersion
digitalSim.ncverilogOpts vlogCompatVersion string { "None" | "Verilog-2001" | "Verilog-1995"}

Description
Checks the text source compliance with Verilog IEEE Standard in the design using Verilog
command-line compilation options.
Possible values are:
None: Compiles text source files using xrun default standard.

Verilog-2001: Compiles text source files using the xrun option, -v2001.

Verilog-1995: Compiles text source files using the xrun option, -v1995.

The default is None.

GUI Equivalent

Command Open Options Form – Verilog

Form Field Text source compliance with xrun

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Environment Variables--vlogSupply0Sigs

Examples
envGetVal("digitalSim.ncverilogOpts" "vlogCompatVersion")

envSetVal("digitalSim.ncverilogOpts" "vlogCompatVersion" 'string "Verilog-2001")

envSetVal("digitalSim.ncverilogOpts" "vlogCompatVersion" 'string "Verilog-1995")

Related Topics

Configuring Netlist Generation Options

vlogSupply0Sigs
digitalSim.netlisterOpts vlogSupply0Sigs string "name_of_global_ground_net"

Description

Specifies the global ground net.

The default is "".

GUI Equivalent

Command Open Options Form – Netlister

Form Field supply0

Examples
envGetVal("digitalSim.netlisterOpts" "vlogSupply0Sigs")

envSetVal("digitalSim.netlisterOpts" "vlogSupply0Sigs" 'string "I18")

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Environment Variables--vlogSupply1Sigs

Related Topics

Configuring Netlist Generation Options

vlogSupply1Sigs
digitalSim.netlisterOpts vlogSupply1Sigs string "name_of_global_power_net"

Description

Specifies the global power net.

The default is "".

GUI Equivalent

Command Open Options Form – Netlister

Form Field supply1

Examples
envGetVal("digitalSim.netlisterOpts" "vlogSupply1Sigs")

envSetVal("digitalSim.netlisterOpts" "vlogSupply1Sigs" 'string "V2")

Related Topics

Configuring Netlist Generation Options

outputXmlFile
digitalSim.netlisterOpts outputXmlFile boolean { t | nil }

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Environment Variables--printDirectivesForVerilog2001

Description

Specifies whether to save the design hierarchy details with the instances and components
information for non-ATPG netlisting mode.
The default value is nil.

GUI Equivalent

Command Open Options Form – Netlister

Form Field Output design hierarchies in XML format

Examples
envGetVal("digitalSim.netlisterOpts" "outputXmlFile")

envSetVal("digitalSim.netlisterOpts" "outputXmlFile" 'boolean t)

Related Topics

Configuring Netlist Generation Options

printDirectivesForVerilog2001
digitalSim.netlisterOpts printDirectivesForVerilog2001 boolean { t | nil }

Description

Prints the Verilog-2001 directives ‘begin_keywords "1364-2001" and ‘end_keywords for every text
module of a verilog view in a single netlist file.
This option is enabled only when mergedNetlist environment variable is set to t.
The default value is nil.

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Environment Variables--printParamForTextInst

GUI Equivalent

Command Open Options Form – Netlister

Form Field Print keyword directives for Verilog modules

Examples
envGetVal("digitalSim.netlisterOpts" "printDirectivesForVerilog2001")

envSetVal("digitalSim.netlisterOpts" "printDirectivesForVerilog2001" 'boolean t)

Related Topics

Configuring Netlist Generation Options

printParamForTextInst
digitalSim.netlisterOpts printParamForTextInst string { "overridden" | "all" }

Description
Prints the parameter value on the instance line of the text modules. The valid values are overridden
and all.

overridden: The netister compares the parameter value that is set on the instance and its
default value defined in the text view. If these values are same, the netlister does not print
anything. Else, the netlister prints the value that is set on the instance.
all: The netlister prints all the parameter values that are set on the instance.

The default is overridden.

GUI Equivalent

None

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Environment Variables--netlistNoWarn

Examples
envGetVal("digitalSim.netlisterOpts" "printParamForTextInst")

envSetVal("digitalSim.netlisterOpts" "printParamForTextInst" 'string "all")

Related Topics

Configuring Netlist Generation Options

netlistNoWarn
digitalSim.netlisterOpts netlistNoWarn string ""

Description

Suppresses the specified SystemVerilog Netlister messages of INFO or WARNING type that start with
the prefix VSVN-, AMS- and, VLOGNET- and are printed in the log file or in the CIW.
You can separate multiple values by spaces.
The default value is "".

GUI Equivalent

Command Open Options Form – Netlister

Form Field Suppress specific netlister info/warnings

Examples
envGetVal("digitalSim.ncverilogOpts" "netlistNoWarn")

envSetVal("digitalSim.ncverilogOpts" "netlistNoWarn" 'string "VSVN-1206 VLOGNET-55")

Related Topics

Configuring Netlist Generation Options

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Environment Variables--genUniqCellNameIfConflict

genUniqCellNameIfConflict
digitalSim.netlisterOpts genUniqCellNameIfConflict boolean { t | nil }

Description

Detects the cell name conflicts in schematic, Verilog, or SystemVerilog cells and renames the cells
with naming conflicts in a single netlist file.
This option is enabled only when the mergedNetlist is set to t.
The default value is nil.

GUI Equivalent

Command Open Options Form – Netlister

Form Field Rename cells with naming conflicts

Examples
envGetVal("digitalSim.netlisterOpts" "getUniqCellNameIfConflict")

envSetVal("digitalSim.netlisterOpts" "getUniqCellNameIfConflict" 'boolean t)

Related Topics

Configuring Netlist Generation Options

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SKILL Functions and Flags

5
SKILL Functions and Flags

This section provides syntax, descriptions, and examples for the Cadence SKILL functions and
SKILL flags associated with the Virtuoso SystemVerilog Netlister (SystemVerilog Netlister) flow.

SKILL Functions
asiDigitalSimAutoloadProc
simDeRegPostNetlistTrigger
simDeRegPreNetlistTrigger
simPostNetlistTriggerList
simPreNetlistTriggerList
simRegPostNetlistTrigger
simRegPreNetlistTrigger

SKILL Flags
hnlUseSchematicForSystemVerilogView
hnlVerilogIgnoreCVTermNameList

asiDigitalSimAutoloadProc
asiDigitalSimAutoloadProc(
)
=> t / nil

Description

Automatically loads the context for class and tool initialization when you launch SystemVerilog
Netlister.

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SKILL Functions and Flags--SKILL Flags

Arguments

None

Value Returned

t The function call is successful.

nil The function is unsuccessful.

Example

The following example shows using the function:

asiDigitalSimAutoloadProc( )
=> t

SKILL Flags
The following SKILL flags are supported in the Virtuoso SystemVerilog Netlister:

hnlUseSchematicForSystemVerilogView ​

Supports printing inherited connections from the schematic when the

instances are bound to a SystemVerilog view.
hnlVerilogIgnoreCVTermNameList ​

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SKILL Functions and Flags--SKILL Flags

Ignores terminals and pin names in the specified list of library and cell names
during Verilog or SystemVerilog netlist generation. The terminal and pin
names added with the cellname in the ignore list are not printed in the netlist
generated by SystemVerilog Netlister.
These terminals and pins can be from a schematic view, symbol view, or a
stopping view.

To set this flag in .simrc, si.env, or Virtuoso CIW, specify libraries and cells
from which the terminals are to be ignored, as follows:

hnlVerilogIgnoreCVTermNameList = list(list(lib1 cell1 pin1) list(lib2 cell2

terminal2)...

Related Topics
hnlUseSchematicForSystemVerilogView

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Batch Mode Options in SystemVerilog Netlister

6
Batch Mode Options in SystemVerilog
Netlister

SystemVerilog Netlister can be launched in batch mode using the following commands:
runsv
cdsCreateConfig
si2runsv

runsv
Use the runsv command with the following options:
runsv
[-help | -version | -W] |
runsv -lib <libName>
-cell <cellName>
-view <viewName>
action_options [setup_options]
[netlisting_options]
[simulation_options]

The following table describes the various options that can be used with the runsv command.

Option Description
-help Displays the tool help.
-version Prints the program version.
-W Prints the program sub-version.
-usage Displays the syntactical usage to indicate how the tool works under various
conditions.

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Batch Mode Options in SystemVerilog Netlister--runsv

-nocdsinit Skips reading the .cdsinit file and uses the SKILL search path.

-lib <libN Specifies the library name of the configuration.

ame>

-cell <cellName>

Specifies the cell name of the configuration.

-view <viewName>

Specifies the view name of the configuration.

-mlcvfile <filename>

Specifies a netlist file that contains multiple cellviews.

The format for each instance line is as follows:
libName1.cellName1[:cellName2:cellName3].configName1
[libName2.cellName4[:cellName5:cellName6].configName2].

Action Options
-netlist [ skip | incremental | all ]

Runs the netlister in the specified mode.

Default: incremental.

-log <logFileName>

Writes the output log messages to <logFileName>

Default: ./runsv.log.

-rundir <runDir>

Specifies the run directory path to use. Netlisting takes place in <runDir>/netlist.

-cdsenv <filePath>

Specifies the .cdsenv file to use.

-merge [ default | unified ]

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Batch Mode Options in SystemVerilog Netlister--runsv

Specifies whether to merge all text and schematic cells into a single netlist file.
Possible values are:
default: Merges all text and schematic cells without naming conflicts into a
single netlist file. For cells with same names, only one cell is merged into the
single netlist. Other cells with naming conflicts are not merged, but are saved in
a separate.sv file.
-merge default is equivalent to enabling Merge text source to single netlist in
the SystemVerilog Netlister Options form.
GUI equivalent: Merge text source to single netlist
unified: Merges all text and schematic cells into a single netlist file. Cells with
naming conflict are renamed to unique cell names before they are merged in a
single netlist. No configuration file is generated as netlist.sv file is self-
contained.
-merge unified is equivalent to enabling Merge text source to single netlist and
Renaming cells with naming conflicts in the SystemVerilog Netlister Options
form.
GUI equivalent: Merge text source to single netlist and Rename cells with
naming conflicts

-export Enables the Virtuoso IP export reuse flow.

This flow lets you replace one or more of the instantiated blocks in a digital-
centric, command-line flow with its HED-configured equivalent. The flow
automatically builds a SystemVerilog (SV) configuration or uses an existing SV
configuration to set up the entire design in its modified form.
The SystemVerilog Netlister lets you export a DUT IP block, which includes the
netlist, text files, and configuration, and reuse it in different testbenches for running
simulations. The netlister assists in design simulation without requiring
configuration details that are needed to configure the complete design on the
System-on-Chip (SoC) level.
The generated export files are placed in the directory specified through the -
rundir option.

- Enables an in-memory check for the schematic connectivity before proceeding to

forcecheck netlisting.

IP Export Reuse Options

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Batch Mode Options in SystemVerilog Netlister--runsv

-v2001configname <configName>

Specifies the configuration name to be used for the SystemVerilog configuration

file generation.

-testbenchtopcell <topCellName>

Specifies the name of the top-module cell for testbench which is used for the
SystemVerilog configuration file generation.
-iplabel <labelName>

Specifies the name of the label which is used in the config.sv file.

-iphierpathtoiptopcell <instanceHierPath>

Specifies the hierarchy path from the top-module cell to the current IP.

-ipencrypt [yes | no]

Enables encryption for the exported IP.

-iplabelAddOnLib [yes | no]

Adds the specified IP label name as the prefix to the Virtuoso Studio library name.

Example
To generate the netlist using the configuration mylib.top:config with the settings specified in the
.cdsenv file, use the following batch mode command:

runsv -lib mylib -cell top -view config -netlist -rundir top_run1 -cdsenv .cdsenv

By default, environment variables specified in file paths are expanded in the runSimulation
file which is created by the runsv command. If you want the runSimulation file to be portable,
enclose the file paths with the ' character so that the environment variables in the file paths
are not expanded in the runSimulation file. The relative paths specified using the ~ or .
characters are resolved with respect to the directory from which you run the runsv command.

Related Topics

SystemVerilog Netlister Batch Mode

SystemVerilog Netlister Options Form

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Batch Mode Options in SystemVerilog Netlister--cdsCreateConfig

cdsCreateConfig
Use the cdsCreateConfig utility with the following options:
cdsCreateConfig
-lib topLibName
-cell topCellName
-view topViewName
[-config newConfigName]
[-liblist 'l_lib']
[-viewlist 'l_view']
[-stoplist 'l_stopview']

The following table describes the various options that can be used with the cdsCreateConfig
utility.

Option Description

-help Displays the cdsCreateConfig help.

-V | -version Prints the utility version.

-W Prints the utility sub-version.

-lib <libName> Specifies the top library name of the configuration.

-cell Specifies the top cell name of the configuration.

<cellName>

-view Specifies the top view name of the configuration.

<viewName>

Optional Options

-config <"newConfigName">

Specifies the name of the config view that needs to be created.

-liblist <'lib1 lib2 ...'>

Specifies the names of the libraries that are bound to the new config view.

-viewlist <'view1 view2 ...'>

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Batch Mode Options in SystemVerilog Netlister--si2runsv

Specifies the names of the views that are bound to the new config view.

-stoplist <'stopview1 stopview2 ...'>

Specifies the names of the stop views that are bound to the new config
view.

Related Topics
SystemVerilog Netlister Batch Mode
SystemVerilog Config Views

si2runsv
The si2runsv utility can be used with the following options:
si2runsv
[run directory]
[-batch [-command commandName]]
[-cdslib path]

The following table describes the various options that can be used with the si2runsv command.

Option Description
-help | -h Displays the si2runsv help.

-V | -version Prints the utility version.

-W Prints the program sub-version.

<rundirectory> Specifies the name of the run directory. Ensure that the run directory includes
the si.env file with the necessary configurations.

-batch Specifies the batch simulation mode.

-command <commandName>

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Batch Mode Options in SystemVerilog Netlister--si2runsv

Specifies the command to generate a netlist or simulate a design. This option

can only be specified with the -batch option.
You typically use the following option with -command for SystemVerilog
designs:
-command netlist

This instructs the simulation system to netlist the design.

-cdslib path Specifies the path where the .cdslib file is located.

Related Topics
SystemVerilog Netlister Batch Mode
Migrating SystemVerilog Integration Designs to SystemVerilog Designs

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