CS232: Computer Architecture II
Spring 2012
Intel i7 Quad-core
1
Who we are
Lecturer:
Prof. Craig Zilles zilles@illinois.edu
Teaching Assistants/Section Instructor: Room 0212 SC
Aparna Sasidharan
Pritam Sukumar
Charles Tucker
http://www.cs.illinois.edu/class/cs232
— MP 1 released on Thursday, due next Thursday.
• Make sure you have an EWS account!
2
What is computer architecture about?
Computer architecture is about building and analyzing computer systems
Processor Memory
HLL Compiler ASM
Input/Output
Instruction Set Architecture is bridge between hardware and software
— Study the MIPS ISA in detail
— Learn what compilers do when they translate high-level code into
assembly (we won’t learn how they do it)
— Learn how HLL program constructs are represented to the machine
Key techniques: Pipelining, Caching, Virtual Memory
Tuning complex code for performance
Hardware support for parallelism
3
Instruction set architectures
Software
ISA
Hardware
The ISA is an interface between software and hardware
— the hardware “promises” to implement all ISA instructions
— the software uses ISA primitives to build complex programs
Later in the semester, we’ll see how the ISA affects the hardware design
4
Why MIPS?
We study the MIPS instruction set architecture to illustrate concepts in
assembly language and machine organization
— concepts are not MIPS-specific
— MIPS is just convenient because it is real, yet simple (unlike x86)
MIPS ISA is used in many places, primarily in embedded systems
— routers from Cisco
— game machines like the Nintendo 64 and Sony Playstation 2 & PSP
5
What you will need to learn for Exam 1
You must become “fluent” in MIPS assembly:
— Translate from C++ to MIPS and MIPS to C++
Example: Translate the following recursive C++ function into MIPS
int pow(int n, int m) { How are arguments passed?
if (m == 1)
How are values returned?
return n;
return n * pow(n, m-1);
} How are complex expressions
broken into simple instructions?
How is recursion done?
6
MIPS: register-to-register, three address
MIPS is a register-to-register, or load/store, architecture
— destination and sources of instructions must all be registers
— special instructions to access main memory (later)
MIPS uses three-address instructions for data manipulation
— each ALU instruction contains a destination and two sources
For example, an addition instruction (a = b + c) has the form:
operation operands
add a, b, c
destination sources
7
MIPS register file
MIPS processors have 32 registers, each of which holds a 32-bit value
— register addresses are 5 bits long
More registers might seem better, but there is a limit to the goodness:
— more expensive: because of registers themselves, plus extra hardware
like muxes to select individual registers
— instruction lengths may be affected 32
D data
Write
5
D address
32 × 32 Register File
5 5
A address B address
A data B data
32 32
8
MIPS register names
MIPS register names begin with a $. There are two naming conventions:
— by number:
$0 $1 $2 … $31
— by (mostly) two-character names, such as:
$a0-$a3 $s0-$s7 $t0-$t9 $sp $ra
Not all of the registers are equivalent:
— e.g., register $0 or $zero always contains the value 0
— some have special uses, by convention ($sp holds “stack pointer”)
You have to be a little careful in picking registers for your programs
— for now, stick to the registers $t0-$t9
9
Basic arithmetic and logic operations
The basic integer arithmetic operations include the following:
add sub mul div
And here are a few bitwise operations:
and or xor nor
Remember that these all require three register operands; for example:
add $t0, $t1, $t2 # $t0 = $t1 + $t2
mul $s1, $s1, $a0 # $s1 = $s1 x $a0
Note: a full MIPS ISA reference can be found in Appendix
A (linked from website)
10
Larger expressions
Complex arithmetic expressions may require multiple MIPS operations
Example: t0 = (t1 + t2) × (t3 - t4)
add $t0, $t1, $t2 # $t0 contains $t1 + $t2
sub $t6, $t3, $t4 # temp value $t6 = $t3 - $t4
mul $t0, $t0, $t6 # $t0 contains the final product
Temporary registers may be necessary, since each MIPS instructions can
access only two source registers and one destination
— in this example, we could re-use $t3 instead of introducing $t6
— must be careful not to modify registers that are needed again later
11
How are registers initialized?
Special MIPS instructions allow you to specify a signed constant, or
“immediate” value, for the second source instead of a register
— e.g., here is the immediate add instruction, addi:
addi $t0, $t1, 4 # $t0 = $t1 + 4
Immediate operands can be used in conjunction with the $zero register
to write constants into registers:
addi $t0, $0, 4 # $t0 = 4
Shorthand: li $t0, 4 # $t0 = 4
(pseudo-instruction)
12
Our first MIPS program
Let’s translate the following C++ program into MIPS:
void main() {
int i = 516;
int j = i*(i+1)/2;
i = i + j;
}
main: # start of main
li $t0, 516 # i = 516
addi $t1, $t0, 1 # i + 1
mul $t1, $t0, $t1 # i * (i + 1)
li $t2, 2
div $t1, $t1, $t2 # j = i*(i+1)/2
add $t0, $t0, $t1 # i = i + j
jr $ra # return
13
CS232 ToDo List!
1. Get on Piazza: All course announcements will be on Piazza. Use the
following URL to enroll in Piazza. Contact the professor or one of the
TAs if you wish to use an alternate email address:
http://piazza.com/illinois/spring2012/cs232
2. Make sure you have a working EWS account: We will use some tools on
EWS, so make sure you can access EWS. Let us know if you have access
problems.
3. (For Friday's lecture!) Review/learn hexadecimal notation and bit-
wise logical and shifting operations: Become familiar with hex and the
basic bit-wise logical shifting operations, using either the attached
resources, other references on the web, or this video which explains bit-
wise logical operations. This knowledge will be assumed for Friday's
lecture, so ask clarifiying questions in Piazza if you have them.
http://www.youtube.com/watch?v=d0AwjSpNXR0
4. Bring a pen/pencil to every lecture and discussion section.
February 12, 2003 Performance 14
