IET Circuits, Devices & Systems

Research Article

Approach for low power high speed 4-bit flash ISSN 1751-858X
Received on 20th October 2018
Revised 17th September 2019
analogue to digital converter Accepted on 14th October 2019
E-First on 15th June 2020
doi: 10.1049/iet-cds.2018.5504
www.ietdl.org

Bagher Razavi1, Mohammad Bagher Tavakoli1 , Farbod Setoudeh2

1Department of Electrical Engineering, Islamic Azad University of Arak, Arak, Iran
2Department of Electrical Engineering, Arak University of technology, Arak, Iran
E-mail: m-tavakoli@iau-arak.ac.ir

Abstract: In this study a new structure was presented to design and simulate a considerably low power and high-speed 4-bit
flash analogue to digital converter based on TSMC 0.18 µm complementary metal-oxide semiconductor (CMOS) technology. In
this structure, in order to reduce the power consumption in the proposed comparator, the reference voltage was removed and
replaced with the threshold voltage of CMOS transistors. This method has reduced the power consumption greatly. Additionally,
by employing reversible logic in the 2:1 multiplier, the power consumption and the number of stages were dropped and obtaining
a faster converter was considered as the other breakthrough. The simulation was carried out in 1.8 V supply voltage and power
consumption of 330 µW while the sampling rate was equal to 2GSample/s.

1 Introduction voltages and it is difficult to produce multiple reference voltages in

flash converter. The **threshold inverter quantisation (TIQ)-based
In terms of speed and power consumption in mobile equipment, ADC overcomes these problems. TIQ-based ADC does not require
analogue to digital converters (ADCs) have attracted more any resistor ladder; hence it is more power and space efficient [15–
attention due to their important role in modern telecommunication. 20].
Following the rapid advances made in complementary metal-oxide In addition, in recent years, researchers have focused on
semiconductor (CMOS) technology, less power and less cost are designing circuits to reduce energy dissipation, optimise power
needed to analyse signals in the digital world. Indeed, ADCs act as consumption, reduce the area of the circuit to the Nano-scale, and
a connection between the real world, analogue, and the world of minimise the heat generated by the circuit.
digital processing. Reversible logic plays an important role in the design of digital
ADCs have a crucial role in electronics, telecommunication and circuits. In designed circuits by non-reversible logic; the number of
control systems and ADCs with low power consumption are more inputs in the circuit is larger than the number of outputs. Therefore,
in demand in today's digital world [1–3]. In order to enhance the during processing, a number of bits containing information are lost
speed and decline the power consumption, not only the transistor and their electrical energy will be released as heat energy. Although
size reduction but finding proper algorithms is feasible although the thermal energy generated by the loss of a bit of information will
achieving lower power algorithms is laborious. Furthermore,
have a value of 2.9×10−21 J, and this amount is low at small scale;
occupation on the chip should not be ignored while ADCs are
however, given the Moore law that the number of transistors and
being designed [4, 5].
elements in digital circuits is rising by almost 100% every 18
Many studies have been conducted on the design and
months, in the not too distant future and integrated on a large scale,
construction of ADC. As a result of them, various techniques have
the waste of electrical energy and the resulting heat generates a
been developed for converting analogue to digital data. There are
major challenge in designing circuits. The reversibility in the
various types of ADCs. Among these, six types of conventional
calculation means that no information will be lost during
Nyquist Rate ADC architectures are most popular including flash,
processing, and the number of outputs is equal to the number of
interpolating and folding, sub-ranging and two-step, pipelined,
inputs [21]. A logical gate with N inputs and N outputs is called
Successive Approximation Register (SAR) and time-interleaved
reversible if and only if there is a peer-to-peer relationship between
[6].
the input and output vectors of the gate. In fact, in reversible logic
The structure of a flash converter, which is known as a
gates, each input vector is mapped to a unique vector in the output.
completely parallel structure, is the fastest structure essentially and
Hence, the values of the output signals can be retrieved from the
generally, the structure is very simple [6, 7]. The N-bit flash
input vector pattern and vice versa, the values of each input vector
converter is made up of 2N−1 comparator and 2N−1 levels of also can be retrieved from its similar vector in the output [22].
reference. Each comparator compares the input signal with a As a result, designing a minimum area occupation on a chip
reference level and any comparator indicates that the input signal is ADC with higher speed and lower power consumption is a major
larger than or less than the comparator reference and the output challenge which is caused mostly by comparators in ADCs [18]. In
array which is contained of the 2N−1 digital values is often called this paper, in order to achieve high accuracy and low power
the Thermometer Code, because the pattern is similar to a mercury consumption, a combination of a new multi-technic is proposed. In
level in a mercuric thermometer. As a matter of fact, after the next section, first we will review the structure of the flash
comparison, there are a number of zeroes and ones in the output. ADC, then a modified TIQ comparator is proposed and
The boundary value between zero and one represents the signal corresponding required analyses are conducted, after that,
level [8, 9]. reversible logic will be used to reduce power consumption, lower
Comparators and reference voltage are the most important parts the delay and increase the speed. Finally, the structure of the
of the flash converter .In order to minimise the power consumption proposed flash ADC is presented and its various stages are
and optimise the comparator circuit many research works have examined. The simulation results are also shown separately.
been conducted in this field and different types of comparators Ultimately the 4-bit flash convertible circuit is simulated and
have been designed [10–14]. However, comparators need reference outputs are displayed.

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 3.1 Comparator
The flash structure suffers from a huge problem with a large
number of comparators. Each of these comparators also needs a
reference voltage for comparison, which increases both power
consumption and high occupied area. As a result, in this paper, a
design is used in which the introduced comparators no longer need
a reference voltage and resistance array and they perform the
comparison by varying the dimensions of their transistors to
determine the switching threshold which will reduce the power
consumption and reduce the occupied area. Since there is no static
state in the current and power, and if the comparators do not work,
the current existing in the resistors will no longer exist.
Generally, the comparator circuit compares an input value with
the reference and places the digital value of 0 or 1 in the output.
One of the types of comparators is latch comparators. This
Fig. 1 Structure of a three-bit conventional flash [23] comparator includes a pre-amplifier circuit and a latch circuit.
First, the signal in the pre-amplifier is amplified, and then it is
quantised in the latch. These circuits require a high gain amplifier.
Since the output is important only for digital value and linearity is
not important, high-performance non-linear circuits can be used.
Comparator outputs should also have the ability to drive logical
circuits after that, and the structures used to design the A/D
converters are usually latched comparators, which are completely
differential and dynamic.
In order to achieve high speeds, a bipolar or fully
complementary method can be used.
Another type of the comparator is the TIQ-based comparator.
Fig. 2 Block diagram of the proposed 4-bit flash converter TIQ-based comparator does not require any resistor ladder hence it
is more power and space efficient [15–20].
A modified version of the TIQ-based comparator is proposed in
this paper. The simulation results are better than the previously
reported works and the design of 4-bit flash ADC excels in terms
of speed and power consumption. In this case, the circuit proposed
for the comparator is shown in Fig. 3. This comparator is a variable
switching voltage comparator.
The proposed comparator circuit consists of eight transistors in
two stages and is shown in Fig. 3. Although the number of
transistors has been doubled compared to a traditional TIQ-based
comparator, the proposed comparator consumes less power than
the TIQ-based comparator. By adding M1 and M4, negative
feedback is obtained in the comparator which causes a reduction in
the dynamic drain current of M2 and M3 at the first stage. As a
result, the added transistors lead to a reduction in the power
consumption of the first stage in the proposed comparator. The
similar concept is applicable for the second stage of the
comparator. The second stage is employed to invert the output of
the first stage; in addition, this stage provides a sharper switching
for the logical voltages. Since the drain and gate terminals are at
Fig. 3 Proposed comparator circuit the same potential (VG = VD), M1, M4, M5, and M8 transistors are
always in the saturation state. The saturated transistors play the role
2 Review of the structure flash ADC of active loads, which can be determined by their transconductance
(gm).
The circuit of a conventional three-bit flash is shown in Fig. 1. The
encoder circuit converts the thermometer code from comparators to The aforementioned circuit compares the input voltage with the
binary. Therefore, the speed of this type of converter only depends threshold voltage of the whole circuit and determines the output.
on the comparators or the sampling circuit. That is why the flash The switching threshold for the circuit of Fig. 3 is obtained as
ADC can be very fast [6]. follows: the change threshold or VM is defined at a point where Vin
As mentioned in the previous section, the major challenge in = Vout. This value can be obtained graphically through inside of the
flash ADCs is the comparators and reference voltages of them graph of the voltage transfer properties (Fig. 4), where the line is
causing the greatest impact power consumption, area occupation on Vin = Vout. In this area, both the NMOS and PMOS transistors are
a chip and limited speed, the second problem is the encoders' delay. in saturated state because VDS = VGS.
Above-mentioned setbacks are conducted in a number of papers For convenience, the circuit of Fig. 5 (four transistors) is
[10–20]. In this paper, both the above-mentioned problems are considered, and after calculating the switching threshold, this value
covered and a new flash ADC is presented. is generalised to the eight transistor modes. An analytical
expression for VM is that its value is obtained by equating the
3 Proposed flash ADC currents passing through the transistors.
Here, it is assumed that the supply voltage is high enough to
In Fig. 2 the structure of the proposed 4-bit flash converter is
allow the component to enter the saturation state quickly
shown. In this structure, the introduced comparison blocks and the
(VDSAT<VM−VT). For convenience, the channel length modulation
new encoder block employed are used. For a better understanding
of the performance regarding the type of 4-bit converted flash, each effect is not considered. The current of the two transistors is
of the stages is analysed and simulated individually. brought together, and because their currents are opposite, they will
be zero as

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 V DSATn
knV DSATn V M − V Tn − + k pV DSTp
2
(1)
V DSATp
V M − V DD − V T p − =0
2

where VM is the switching threshold voltage. Equation (1) can be

used to extract the required ratio of the size of the PMOS transistor
to the NMOS, which adjusts the switching threshold to the desired
VM value. So we have

(W /L) p k′nV DSATn V M − V Tn − (V DSATn /2)

= (2)
(W /L)n k′ pV DSATp V DD − V M + V T p + (V DSATp /2)

By assigning VM and solving the equation around it, the relation (3)
is obtained
Fig. 4 VTC static CMOS inverter
V Tn + (V DSATn /2) + r V DD + V T p + (V DSATp /2)
VM =
1+r
(3)
k pV DSATp vSATpW p
with r = =
knV DSATn vSATnW n

Suppose both NMOS and PMOS transistors have the same oxide
thickness. For large values of VDD (compared to threshold and
saturation voltages), (3) is summarised below

rV DD
VM ≃ (4)
1+r

Equation (4) proposing the switching threshold is determined by

the ratio r, which compares the excitation lengths associated with
the NMOS and PMOS transistors. By introducing r in (4) we have

rmn1
V M ≃ V DD (5)
rmn1 + rmp1 Fig. 5 TIQ comparator circuit

Generally, the optimal value for VM is considered around the

middle of the switching voltage or V DD /2, because these results are
comparable to the low and high noise margins. This requires the
value of r being equal to 1, which is equivalent to the size of the
PMOS transistor piece, so that

V DSATnk′n
(W /L) p = (W /L)n × (6)
V DSATp k′ p

Moving VM upwards (VDD) requires a larger amount of r, which

means to increase the size of the PMOS transistor. As the size of
the NMOS increases, the switching threshold becomes closer to
zero (ground). By adding four transistors to the circuit of Fig. 5 and
taking into account (5), it appears that the impedance generated by
these transistors should also be applied to the equation, so we have
Fig. 6 Result of comparator simulation for WM1, M2, M5, M6 = 1 u and
rm3 + (1/gm4)
V M = V DD (7) WM3, M4, M7, M8 = 5 u
rm2 + (1/gm1) + rm3 + (1/gm4)
By determining the proper size of the transistors (W), a comparator
For different values of W/L in the transistors of the first stage of the can be designed with just one input and without reference voltage.
comparator circuit (M1, M2, M3 and M4) the input voltage is If the input reaches a certain threshold voltage, the output mode
compared with the switching voltage (VM). Since the transient will be changed. In the design of the corresponding W-size
voltage according to (7) is related to the threshold voltage, the circuitry, all up together transistors and down together transistors
action is compared with the threshold voltages, which will result in are identical. The simulation result of the comparator output for
a reduction in the power consumption and the area occupancy. The WM1, M2, M5, M6 = 1 u and WM3, M4, M7, M8 = 5 u is shown in Fig. 6.
VM computed above is defined for high power supply and low According to the preceding definition for VM, where the input
channel length. If the supply voltage is low or the length of the voltage in Fig. 6 is equal to the output voltage. It is shown in Fig. 6
channel increases, the saturation velocity will not occur for NMOS at the point where these two voltages are equal; the switching
and PMOS transistors (VM−VT<VDSAT). Accordingly, we will have threshold voltage is equal to 0.83 V. Also, for WM1, M2, M5, M6 = 5 u
and WM3, M4, M7, M8 = 1 u, the switching threshold voltage
V Tn + r(V DD + V T p) −k p according to Fig. 7 is equal to 1.05 V.
VM = with r = (8)
1+r kn According to the definition of a 4-bit flash ADC, 15
comparators are required. Fig. 8 shows the values of the

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Fig. 7 Result of comparator simulation for WM1, M2, M5, M6 = 5 u and
Fig. 10 Result of comparator mismatch with Cadence simulator for WM1,
WM3, M4, M7, M8 = 1 u
M2, M5, M6 = 5 u and WM3, M4, M7, M8 = 1 u

Fig. 8 Values of the comparator switching threshold voltage depending on

the transistors’ size

Table 1 Results obtained by the comparision of the

proposed comparator and TIQ comparator
Parameter Proposed comparator TIQ comparator Fig. 11 Histogram of the threshold voltage variations of a comparator for
mismatch analysis with Cadence simulator
power conception, µw 7.5 331
delay, ns 0.1 0.075
shown in Fig. 5, are compared and the results are shown in Table 1.
technology, µm 0.18 0.18
power supply, V 1.8 1.8
number of transistors 8 4 3.2 Mismatch analysis
Production process impacts on the performance parameters; in this
section, some important side effects are investigated. Cadence
simulator is employed for analysis of random mismatch by Monte
Carlo method simulation [20, 24]. To obtain high precision and
reliable circuit random mismatch MOS technology is considered
[25]. The proposed comparator circuit (Fig. 3) is simulated with
200 Monte Carlo runs at 27°C for mismatch analysis and the
results are shown in Figs. 9 and 10.
According to the preceding definition for VM the input voltage
in Fig. 9 is equal to the output voltage. In Fig. 9 at the point where
these two voltages are equal; the switching threshold voltage is
equal to 0.836 V. Also, for WM1, M2, M5, M6 = 5 u and WM3, M4, M7,
M8 = 1 u, the switching threshold voltage according to Fig. 10 is
equal to 1.053 V.
Fig. 11 shows the histogram of the threshold voltage variation
of a single comparator out of 200 Monte Carlo runs at 27°C and
the mean value is 1.41829 mv and the standard deviation value is
134.949 p, the magnification of x-axis is shown in Fig. 11.
Fig. 9 Result of comparator mismatch with Cadence simulator for WM1, Consequently, the results of simulation verify almost no
M2, M5, M6 = 1 u and WM3, M4, M7, M8 = 5 u considerable effect on VM as is shown in both Figs. 9 and 10, the
VM variation is negligible. Since the proposed comparators are
comparator switching threshold voltage depending on the fabricated in an integrated circuit, all conditions on the chip for a
transistors' size. single ADC are almost identical to all parts of the device, therefore
To investigate the better performance of the proposed all of the VMs have a low dependency on the production process
comparator, with diode-connected transistors shown in Fig. 3, and and the all differentiate VMs are relatively constant to each other,
comparator based on TIQ, without diode-connected transistors and the simulation results showing the correct state of mismatch

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 Fig. 14 Reversible proposed multiplexer response

3.4 Encoder block

In order to convert the output of the comparator (thermometer
Fig. 12 Encoder block diagram code), it is necessary to have a logic circuit to convert the output to
binary code using Encoder block. In Fig. 12 an encoding block is
used in the ADC.
Fig. 12 shows the encoder block which consists of several 2:1
multiplexer circuits. These multiplexer circuits that are formed of
transmission transistors (reversible) consist of inputs A and B, and
their output is represented by Y. The circuit also includes a
selection input. Fig. 13 shows the proposed multiplexer circuit.
Therefore, the proposed multiplexer is designed to be reversible
and has three output modes, and it is necessary to have a one-to-
one correspondence between the inputs and outputs. In this
structure, the output of the multiplexer is designed using two
transistors. The outputs of G1 and G2 are intended for the
reversibility of the multiplexer. G1 output is considered equal to
selector input. When the input is equal to 0, the PMOS transistor is
turned on and the NMOS transistor turns off and the input A will be
passed to the output. When the input is selected 1, the NMOS
transistor is on, and the PMOS transistor is turned off and input B
will be passed to the output. Also, when input is equal to 0, G2 = B,
and if the input is selected 1, G2 = A. Table 2 shows the
performance of a reversible multiplexer circuit.
Table 2 shows the simulation, that illustrates correctly the
performance of the multiplexer circuit and Fig. 14 shows the
simulation of the time response of the multiplexer circuit.
Fig. 15 shows the internal schematic representation of the
proposed 4-bit flash converter and in Fig. 16 the final output of the
4-bit flash ADC with (V slope) input is shown.
Finally, in Fig. 17 the power spectral density of the proposed 4-
bit flash ADC is shown.
Fig. 13 Reversible multiplexer circuit
In the proposed flash ADC, the maximum sampling frequency
is equal to 2 GHz (fs = 2 GHz). Considering the Nyquist theorem
for this proposed circuit structure. Finally the observed mismatch effective resolution bandwidth (ERBW) is equal to 1 GHz
can be compensated by an external offset voltage [26]. (ERBW>fs/2). For the full-resolution output (4-bit resolution) the
maximum input frequency of the proposed converter is 50 MHz.
For a fair comparison between the proposed converter and the
3.3 Gain booster converters presented so far, the figure of merit criterion (FOM) is
The second stage in Fig. 3 is employed to invert the output of the defined so that the proposed scheme can be compared to other
first stage; in addition, this stage provides a sharper switching for designs. This fitness criterion is defined as
the logical voltages in comparators and make a gain booster role in
this floor.

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Table 2 Correct table of reversible multiplexer circuit
S A B G1 Y G2
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 0
0 1 1 0 1 1
1 0 0 1 0 0
1 0 1 1 1 0
1 1 0 1 0 1
1 1 1 1 1 1

Table 3 Comparison of the proposed flash converter with related works

References Resolution, bit Power Power supply, V Technology, µm Sampling rate Input Freq. Delay FoM (fJ/conv.)
[27] 4 368 mW 1.8 0.18 — 87.19 MHz 1.9 ms —
[28] 4 1.4 mW 1.2 0.09 1 GS/s — 1.8 ns 87.5
[29] 4 1.19 mW 1.8 0.18 — — — —
[30] 4 3.9 mW 1.8 0.18 400 MS/s 1.71 MHz — 609.3
[31] 4 0.75 mw 2 0.18 — — 9.012 ms —
[32] 4 4.43 mW 1.8 0.18 700 MS/s — — 395.5
[33] 5 16.33 mW ±0.8 0.065 3 GS/s — 1.542 ps 170.1
[34] 5 2.424 mW 1.2 0.09 3 GS/s — — 25.25
proposed 4 330 µW 1.8 0.18 2 GS/s 50 MHz 0.3 ns 10.97

Fig. 16 Output waveform of the proposed 4-bit flash with (V slope) input

Fig. 15 Internal schematic representation of the 4-bit flash drive Fig. 17 Power spectral density of the proposed 4-bit flash ADC

P In (10), SNDR is signal-to-noise and distortion ratio [1, 3 and 20].

FOM = ENOB (9) The proposed ADC in this paper achieves an SNDR value of 25.3
2 × fs dB with a Nyquist input frequency. By using (10), the ENOB is
calculated and the result is 3.91 bits, then FOM is calculated and
In (9), P is the power consumption, fs is the sampling rate and the result is 10.97. Table 3 presents the results of several published
ENOB is the effective number of bits. The overall accuracy of the papers in recent years and the proposed design.
converter is characterised by ENOB, which is obtained as

SNDR − 1.76 SNDR − 1.76

ENOB = = (10)
10log 4 6.02

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