EXPERIMENT NO.
Objective: Design Fulladder by using various abstraction level of Verilog HDL. Also write
testbench code for Fulladder.
Apparatus/ Tool: Xilinx ISE Design/ Modelsim/EDA Playground
Program:
Design Code of Full Adder
// DATA LEVEL MODELLING
module FA_DM (S, C, A, B, Cin);
input A, B, Cin;
output S, C;
assign S = A ^B ^ Cin;
assign C= A&B | Cin&(A^B);
endmodule
// Gate Level Module
module FA_GM (S, C, A, B, Cin);
input A, B, Cin;
output S, C;
wire w1, w2, w3;
xor (w1, A, B);
xor (Sum, w1, Cin);
and (w2, A, B);
and (w3, w1, Cin);
or (C, w2, w3);
endmodule
// Instantiation of Half Adder
module FA_HA (S, C, A, B, Cin);
input A, B, Cin;
output S, C;
// Instantiation of HA
HA H1(w1, w2, A, B);
HA H2(S, w3,w1,Cin);
or (C, w3,w2);
endmodule
Test Bench code of Full Adder
Module tb_FA( );
reg A, B, Cin;
Wire S, C;
// instantiation Full Adder Design Call
FA_DM H1(S, C, A, B, Cin);
Initial begin
A=1’b0; B=1’b0; Cin=1’b0;
#10
$display (“ A= %b, B=%b, Cin=%b, S=%b, C=%b”, A,B,Cin,S,C);
A=1’b0; B=1’b0; Cin=1’b1;
#10
$display (“ A= %b, B=%b, Cin=%b, S=%b, C=%b”, A,B,Cin,S,C);
A=1’b0; B=1’b1; Cin=1’b0;
#10
$display (“ A= %b, B=%b, Cin=%b, S=%b, C=%b”, A,B,Cin,S,C);
A=1’b0; B=1’b1; Cin=1’b1;
#10
$display (“ A= %b, B=%b, Cin=%b, S=%b, C=%b”, A,B,Cin,S,C);
A=1’b1; B=1’b0; Cin=1’b0;
#10
$display (“ A= %b, B=%b, Cin=%b, S=%b, C=%b”, A,B,Cin,S,C);
A=1’b1; B=1’b0; Cin=1’b1;
#10
$display (“ A= %b, B=%b, Cin=%b, S=%b, C=%b”, A,B,Cin,S,C);
A=1’b1; B=1’b1; Cin=1’b0;
#10
$display (“ A= %b, B=%b, Cin=%b, S=%b, C=%b”, A,B,Cin,S,C);
A=1’b1; B=1’b1; Cin=1’b1;
#10
$display (“ A= %b, B=%b, Cin=%b, S=%b, C=%b”, A,B,Cin,S,C);
end
endmodule
Circuit Diagram:
Procedure:
Step 1: Write Verilog code on EDA Tool
Step 2 : Run the Verilog code
Step 3 : Create RTL schematic of given Verilog and take screen shot
Step 4 : Write the Test bench code on EDA Tool
Step 5 : Check syntax
Step 6 : Simulate the testbench of digital circuit
Step 7 : Check the output waveform and take the screen shot
Result:
Conclusion: The design of Verilog code completed successfully with represent output in
waveform.
EXPERIMENT NO. 2
Objective: Design all logic gates by Verilog HDL. Also write testbench code for all logic
gates.
Apparatus/ Tool: Xilinx ISE Design/ Modelsim/EDA Playground
Program:
//Data Flow modelling
module allgate( Y0,Y1,Y2, Y3,Y4,Y5,Y6,Y7, A,B);
input A, B;
output Y0,Y1,Y2,Y3,Y4,Y5,Y6,Y7;
// Not Gate
assign Y0 = ~A;
// AND Gate
assign Y1= A&B;
// OR Gate
assign Y2= A|B;
// XOR Gate
assign Y3= A^B;
// NAND Gate
assign Y4= ~(A&B);
// NOR Gate
assign Y5= ~(A |B);
//Buffer
assign Y6 = A;
//XNOR
assign Y7= ~(A^B);
endmodule
Test Bench code of All Gates
Module tb_allgate( );
reg A, B;
Wire Y0,Y1,Y2,Y3,Y4,Y5,Y6,Y7;
// instantiation Full Adder Design Call
allgate H2(Y0,Y1,Y2,Y3,Y4,Y5,Y6,Y7, A,B);
Initial begin
A=1’b1; B=1’b1;
#10
$display (“A= %b, B=%b, Y0=%b”, A,B,Y0);
A=1’b1; B=1’b1;
#10
$display (“A= %b, B=%b, Y1=%b”, A,B,Y1);
A=1’b1; B=1’b1;
#10
$display (“ A= %b, B=%b, Y2=%b”, A,B,Y2);
A=1’b1; B=1’b1;
#10
$display (“A= %b, B=%b, Y3=%b”, A,B,Y3);
A=1’b1; B=1’b1;
#10
$display (“ A= %b, B=%b, Y4=%b”, A,B,Y4);
A=1’b1; B=1’b1;
#10
$display (“A= %b, B=%b, Y5=%b”, A,B,Y5);
A=1’b1; B=1’b1;
#10
$display (“ A= %b, B=%b, Y6=%b, ”, A,B,Y6);
A=1’b1; B=1’b1;
#10
$display (“ A= %b, B=%b, Y7=%b, ”, A,B,Y7);
end
endmodule
Circuit Diagram
RTL Schematic (if available):
Procedure:
Step 1: Write Verilog code on EDA Tool
Step 2 : Run the Verilog code
Step 3 : Create RTL schematic of given Verilog and take screen shot
Step 4 : Write the Test bench code on EDA Tool
Step 5 : Check syntax
Step 6 : Simulate the testbench of digital circuit
Step 7 : Check the output waveform and take the screen shot
Result:
Conclusion: The design of Verilog code completed successfully with represent output in
waveform.
EXPERIMENT NO. 3(a)
Objective: Design 8:1 Multiplexer by using Verilog HDL. Write testbench code for 8:1 Multiplexor. Attach
output waveform and result of Multiplexer.
Apparatus/ Tool: Xilinx ISE Design/ Modelsim/EDA Playground
Program:
// Behavioural Level modelling
module mux(input wire [7:0] data_in, input wire [2:0] sel, output reg out);
always @(*) begin
if (sel == 3'b000)
out = data_in[0];
else if (sel == 3'b001)
out = data_in[1];
else if (sel == 3'b010)
out = data_in[2];
else if (sel == 3'b011)
out = data_in[3];
else if (sel == 3'b100)
out = data_in[4];
else if (sel == 3'b101)
out = data_in[5];
else if (sel == 3'b110)
out = data_in[6];
else // sel == 3'b111
out = data_in[7];
end
endmodule
Test Bench code of MUX
module test_bench();
reg [7:0] I;
reg [2:0] S;
wire Y;
// instantiation Mux 8:1 Design Call
mux H3(I,S,Y);
initial begin
I=8'b00000001; S=3'b000;
#10
$display ("I= %b, S=%b, Y=%b", I,S,Y);
I=8'b00000010; S=3'b001;
#10
$display ("I= %b, S=%b, Y=%b", I,S,Y);
I=8'b00000100; S=3'b010;
#10
$display ("I= %b, S=%b, Y=%b", I,S,Y);
I=8'b00001000; S=3'b011;
#10
$display ("I= %b, S=%b, Y=%b", I,S,Y);
I=8'b00010000; S=3'b100;
#10
$display ("I= %b, S=%b, Y=%b", I,S,Y);
I=8'b00100001; S=3'b101;
#10
$display ("I= %b, S=%b, Y=%b", I,S,Y);
I=8'b01000000; S=3'b110;
#10
$display ("I= %b, S=%b, Y=%b", I,S,Y);
I=8'b10000000; S=3'b111;
#10
$display ("I= %b, S=%b, Y=%b", I,S,Y);
end
endmodule
Procedure:
Result:
Conclusion:
EXPERIMENT NO. 3(b)
Objective: Design 1:8 Demultiplexer by using Verilog HDL. Write testbench code for 1:8
Multiplexor. Attach output waveform and result of Demultiplexer.
Apparatus/ Tool: Xilinx ISE Design/ Modelsim/EDA Playground/Verilator
Program:
//Design code for 1:8 Demux
module demux_1_8 (Y,S,I);
input I;
input [2:0] S;
output reg [7:0] Y;
always @(*) begin
// Assign din to the selected output
case (S)
3'b000: Y[0] = I;
3'b001: Y[1] = I;;
3'b010: Y[2] = I;
3'b011: Y[3] = I;
3'b100: Y[4] = I;
3'b101: Y[5] = I;
3'b110: Y[6] = I;
3'b111: Y[7] = I;
endcase
end
endmodule
//Testbench code
module tb1_8;
reg I;
reg [2:0] S;
wire [7:0] Y;
// Instantiate the demux module
demux_1_8 H1(.I(I), .S(S), .Y(Y));
initial begin
// Monitor changes
$monitor("Time=%0t, I=%b, S=%b ,Y=%b", $time, I, S, Y);
// Test cases
I = 1; S = 3'b000; #10;
I = 1; S = 3'b001; #10;
I= 1; S= 3'b010; #10;
I = 1; S = 3'b011; #10;
I = 1; S= 3'b100; #10;
I = 1; S = 3'b101; #10;
I = 1; S = 3'b110; #10;
I = 1; S = 3'b111;
end
endmodule
Procedure:
Result:
Conclusion:
Precaution:
EXPERIMENT NO. 4(a)
Objective: Design 3:8 decoder using Verilog HDL. Also write testbench code for decoder.
Attach output waveform and result of Decoder.
Apparatus/ Tool: Xilinx ISE Design/ Modelsim/EDA Playground/Verilator
Program:
//Design Code for 3to8 Decoder
module decoder (Y,I, E);
input [2:0] I;
input E;
output reg [7:0] Y;
always @(*) begin
case (I)
3'b000 : Y <= 8'b00000001;
3'b001 : Y <= 8'b00000010;
3'b010 : Y <= 8'b00000100;
3'b011 : Y <= 8'b00001000;
3'b100 : Y <= 8'b00010000;
3'b101 : Y <= 8'b00100000;
3'b110 : Y <= 8'b01000000;
3'b111 : Y <= 8'b10000000;
endcase
end
endmodule
//Testbench code for 3to8 decoder
module tb_dec();
reg [2:0] I;
wire [7:0] Y;
reg E;
integer i;
dec3_8 D1(Y,I,E);
initial begin
$monitor( "E=%b, I=%d, Y=%b ", E, I, Y);
for ( i=0; i<16; i=i+1)
begin
{E,I} = i;
#1;
end
end
endmodule
Procedure:
Observation Table (if available)
Result:
Conclusion:
Precaution:
EXPERIMENT NO. 4(b)
Objective: Design 8:3 encoder using Verilog HDL. Also write testbench code for
encoder. Attach output waveform and result of encoder.
Apparatus/ Tool: Xilinx ISE Design/ Modelsim/EDA Playground/Verilator
Program:
//Design Code for 8to3 Encoder
module encoder(Y,I, E);
input [7:0]I ;
input E;
output reg [2:0] Y;
always @(*) begin
case (I)
8'b00000001: Y<= 3'b000;
8'b00000010: Y <= 3'b001;
8'b00000100: Y <= 3'b010;
8'b00001000: Y <= 3'b011;
8'b00010000: Y <= 3'b100;
8'b00100000: Y <= 3'b101;
8'b01000000: Y <= 3'b110;
8'b10000000: Y <= 3'b111;
default: Y<= 3'bxx;
endcase
end
endmodule
//Testbench code for encoder
module test_enc();
reg [7:0] I;
reg E;
wire [2:0] Y;
encoder h9(Y,I,E);
initial begin
I=8'b00000000;
E=1'b1;
#10 I=8'b00000001;
#10 I=8'b00000010;
#10 I=8'b00000100;
#10 I=8'b00001000;
#10 I=8'b00010000;
#10 I=8'b00100000;
#10 I=8'b01000000;
#10 I=8'b10000000;
end
endmodule
Circuit Diagram (if available): Draw any circuit diagram on blank side of Journal by using
pencil only.
RTL Schematic (if available): Draw any circuit diagram on blank side of Journal by using
pencil only/ Paste the image
Procedure:
Observation Table (if available)
Result:
Conclusion:
Precaution:
EXPERIMENT NO. 5
Objective: Design of 4 bit binary to gray code converter by using Verilog HDL. Also write
testbench code for gray code converter. Attach output waveform and result of gray code.
Apparatus/ Tool: Xilinx ISE Design/ Modelsim/EDA Playground
Program:
// dataflow Level modelling
module bin_gray_4bit(I,g);
input [3:0] I;
output [3:0] g;
assign g[3] = I[3];
assign g[2] = I[3] ^ I[2];
assign g[1] = I[2] ^ I[1];
assign g[0] = I[1] ^ I[0];
endmodule
Test Bench code of All Gates
module tb_bg();;
reg [3:0] I;
wire [3:0] g;
//instance declaration
bg_4bit h1(.I(I), .g(g));
initial begin
$monitor ("I = %b, g = %b", I, g);
I= 4'b0000; #10;
I= 4'b0001; #10;
I= 4'b0010; #10;
I= 4'b0011; #10;
I= 4'b0100; #10;
I= 4'b0101; #10;
I= 4'b0110; #10;
I= 4'b0111; #10;
I = 4'b1000; #10;
I = 4'b1001; #10;
I = 4'b1010; #10;
I = 4'b1011; #10;
I = 4'b1100; #10;
I = 4'b1101; #10;
I = 4'b1110; #10;
I = 4'b1111; #10;
$stop;
end
endmodule
Circuit Diagram (if available): Draw any circuit diagram on blank side of Journal by using
pencil only.
RTL Schematic (if available): Draw any circuit diagram on blank side of Journal by using
pencil only/ Paste the image
Procedure:
Observation Table (if available)
Result:
Conclusion:
EXPERIMENT NO. 6
Objective: Design of 4-bit comparator using Verilog HDL. Also write testbench code for
Comparator. Attach output waveform and result of Comparator.
Apparatus/ Tool: Xilinx ISE Design/ Modelsim/EDA Playground
Program:
module comp_4bit (Y1,Y2,Y3,A,B);
input [3:0] A, B,
output reg Y1,Y2,Y3;
always @(*) begin
Y1 <= (A > B) ? 1 : 0;
Y2 <= (A == B) ? 1 : 0;
Y3 <= (A < B) ? 1 : 0;
end
endmodule
Test Bench code of All Gates
module tb_comp_4bit ();
reg [3:0] A, B;
wire Y1, Y2, Y3;
comp_4bit h5 ( .A(A), .B(B), .Y1(Y1),.Y2(Y2), .Y3(Y3)); initial begin
// $monitor("A = %b, B = %b , Y1=%b, Y2=%b,Y3=%b”, A,B, Y1,Y2,Y3);
A = 4'b0000; B = 4'b0000; #10;
A = 4'b0001; B = 4'b0000; #10;
A = 4'b0010; B = 4'b0011; #10;
A = 4'b0100; B = 4'b0100; #10;
A = 4'b1001; B = 4'b0110; #10;
A = 4'b1111; B = 4'b1111; #10;
A = 4'b1010; B = 4'b1100; #10;
$stop;
End
endmodule
Procedure:
Result:
Conclusion:
EXPERIMENT NO. 7
Objective: Design flip flop (D-FF, T-FF and JK-FF) by using Verilog HDL. Also write
testbench code for Flip flop. Attach the output waveform and result of D-FF, T-FF and JK-FF.
Apparatus/ Tool: Xilinx ISE Design/ Modelsim/EDA Playground
Program:
// DFF
module D_FF(clk, rst, d, q);
input wire clk, rst, d;
output reg q;
always @(posedge clk) begin //behavioral modeling
if (rst == 1) q <= 0;
else q <= d;
end
endmodule
Test Bench code of D-Flip flop
module tb_D_FF();
reg clk;
reg rst;
reg d;
wire q;
//instantite design
D_FF D1(clk, rst, d, q);
always #5 clk = ~clk; // 10ns clock period
initial begin
clk = 0;
rst = 1;
d = 0;
// Reset pulse
#10;
rst = 0;
// Apply test values
#10 d = 1;
#10 d = 0;
#10 d = 1;
#10 d = 1;
#10 d = 0;
// Finish simulation
#20;
$finish;
end
initial begin
$monitor("Time=%0t | rst=%b | d=%b | q=%b", $time, rst, d, q);
end
endmodule
// TFF
module T_FF (
input wire clk,
input wire rst, // asynchronous reset
input wire t,
output reg q
);
always @(posedge clk or posedge rst) begin
if (rst)
q <= 0;
else if (t)
q <= ~q;
// else q remains unchanged
end
endmodule
//Testbench TFF
module tb_TFF;
reg clk;
reg rst;
reg t;
wire q;
// Instantiate the T Flip-Flop
T_FF uut (
.clk(clk),
.rst(rst),
.t(t),
.q(q)
);
// Clock generation: 10ns period
always #5 clk = ~clk;
initial begin
// Initialize inputs
clk = 0;
rst = 1;
t = 0;
// Apply reset
#10 rst = 0;
// Toggle T and observe
#10 t = 1;
#20 t = 1;
#20 t = 0;
#20 t = 1;
#20 t = 1;
// End simulation
#20;
$finish;
end
initial begin
$monitor("Time=%0t | rst=%b | t=%b | q=%b", $time, rst, t, q);
end
endmodule
// JK FF
module jk_ff(
output reg q,
output reg qb,
input j,
input k,
input clk
);
always @(posedge clk) begin
// TRUTH TABLE OF JK FF
if (j == 0 && k == 0)
begin
q <= q;
qb <= ~qb;
end
else if (j == 0 && k == 1)
begin
q <= 0;
qb <= 1;
end
else if (j == 1 && k == 0)
begin
q <= 1;
qb <= 0;
end
else if (j == 1 && k == 1)
begin
q <= ~q;
qb <= qb;
end
end
endmodule
//Testbench JK FF
module jk_ff_tb;
wire q; // Output Q
wire qb; // Output Q-bar
reg j; // Input J
reg k; // Input K
reg clk; // Clock input
jk_ff uut (q, qb, j, k, clk); // Instantiation of the JK flip-flop module
initial begin
j = 0;
k = 0;
clk = 0;
#1000 $finish; // Finishes simulation after 1000 time units
end
// Clock toggling process
always #30 clk = ~clk; // Toggles the clock every 30 time units
// K input toggling process
always #50 k = ~k; // Toggles the K input every 50 time units
// J input toggling process
always #100 j = ~j; // Toggles the J input every 100 time units
endmodule
Circuit Diagram (if available): Draw any circuit diagram on blank side of Journal by using
pencil only.
RTL Schematic (if available): Draw any circuit diagram on blank side of Journal by using
pencil only/ Paste the image
Procedure:
Result:
Conclusion:
EXPERIMENT NO: 8
Objective: Design 4 bit Synchronous and Asynchronous up-counter by using Verilog HDL.
Also write testbench code for Synchronous and asynchronous up- counter. Attach the output
waveform and result of counter.
Apparatus/ Tool: Xilinx ISE Design/ Modelsim/EDA Playground
Program:
Design code for Synchnrouns counter :
module counter (input clk, up input rstn, output reg[3:0] out);
always @ (posedge clk) begin
if (! rstn)
out <= 0;
else
out <= out + 1;
end
endmodule
Test Bench code of Synchronous counter :
module tb_counter;
reg clk; // Declare an internal TB variable called clk to drive clock to the design
reg rstn; // Declare an internal TB variable called rstn to drive active low reset to
design
wire [3:0] out; // Declare a wire to connect to design output
// Instantiate counter design and connect with Testbench variables
counter c0 ( .clk (clk),
.rstn (rstn),
.out (out));
// Generate a clock that should be driven to design
// This clock will flip its value every 5ns -> time period = 10ns -> freq = 100 MHz
always #5 clk = ~clk;
// This initial block forms the stimulus of the testbench
initial begin
// 1. Initialize testbench variables to 0 at start of simulation
clk <= 0;
rstn <= 0;
// 2. Drive rest of the stimulus, reset is asserted in between
#20 rstn <= 1;
#80 rstn <= 0;
#50 rstn <= 1;
// 3. Finish the stimulus after 200ns
#20 $finish;
end
endmodule
Design Asynchronous counter Code :
module async( input wire clk,input wire reset,output reg [3:0] q );
always @(posedge clk or posedge reset) begin
if (reset)
q <= 4'b0000; // Reset the counter to 0
else
q <= q + 1; // Increment the counter
end
endmodule
Test bench code Asynchronous counter
`timescale 1ns / 1ps
module tb_async_up_counter;
reg clk;
reg rst;
wire [3:0] q;
// Instantiate the Unit Under Test (UUT)
async_up_counter uut (.clk(clk), .rst(rst), .q(q));
// Clock Generation: 10 ns period (100 MHz)
initial begin
clk = 0;
forever #5 clk = ~clk; // Toggle every 5 ns
end
// Test Sequence
initial begin
// Initialize Inputs
rst = 1;
// Hold reset for some time
#15;
rst = 0;
// Let the counter run for a while
#200;
// Apply reset again
rst = 1;
#10;
rst = 0;
// Continue simulation
#100;
$finish; // End simulation
end
// Monitor output
initial begin
$monitor("Time = %0t | rst = %b | q = %b", $time, rst, q);
end
endmodule
Result:
Conclusion:
EXPERIMENT NO: 9
Objective: Design of sequence detector 101 using state machine using Verilog HDL. Also
write a testbench code for sequence detector. Attach the output waveform and result of
register.
Apparatus/ Tool: Xilinx ISE Design/ Modelsim/EDA Playground
Program:
module seq_detector_101 (input clk, input rst, input in, output reg detected );
// State encoding
typedef enum reg [1:0] {
S0 = 2'b00,
S1 = 2'b01,
S2 = 2'b10,
S3 = 2'b11
} state_t;
state_t current_state, next_state;
// State transition logic (next state)
always @(*) begin
case (current_state)
S0: next_state = (in == 1) ? S1 : S0;
S1: next_state = (in == 0) ? S2 : S1;
S2: next_state = (in == 1) ? S3 : S0;
S3: next_state = (in == 1) ? S1 : S2;
default: next_state = S0;
endcase
end
// State register
always @(posedge clk or posedge rst) begin
if (rst)
current_state <= S0;
else
current_state <= next_state;
end
// Output logic (Moore machine: output depends on current state)
always @(*) begin
case (current_state)
S3: detected = 1;
default: detected = 0;
endcase
end
endmodule
Testbench code for 101 Sequence
`timescale 1ns / 1ps
module tb_seq_detector_101;
reg clk;
reg rst;
reg in;
wire detected;
// Instantiate the sequence detector module
seq_detector_101 uut (.clk(clk),.rst(rst),.in(in), .detected(detected));
// Clock generation (10 ns period)
initial begin
clk = 0;
forever #5 clk = ~clk;
end
// Stimulus
initial begin
// Monitor signal values
$monitor("Time=%0t | rst=%b | in=%b | detected=%b", $time, rst, in, detected);
// Initialize
rst = 1;
in = 0;
#12;
rst = 0;
// Apply input sequence: e.g., 1 0 1 1 0 1 (should detect "101" twice)
#10 in = 1; // 1
#10 in = 0; // 10
#10 in = 1; // 101 → should detect here
#10 in = 1; // overlaps, starts new 1
#10 in = 0; // 10
#10 in = 1; // 101 → should detect again
#10 in = 0; // 0
#10 in = 0; // 0
#10 in = 1; // 1
#20 $finish;
end
endmodule
Procedure:
Result:
Conclusion:
EXPERIMENT NO: 10
Objective: Design & simulate all basic logic gates layout and optimized the input and output
waveforms .
Apparatus :
Layout Design :
Observation Table (if available)
Result:
Conclus
EXPERIMENT NO: 11
Objective : Design & simulate CMOS inverter, CMOS NAND Gates & CMOS NOR layout.
Apparatus :
Layout Design :
Procedure :
Result :
Conclusion:
EXPERIMENT NO.12
Objective : Design & simulate CMOS inverter, CMOS NAND Gates & CMOS NOR layout.
Apparatus :
Layout Design :
Procedure :
Result :
Conclusion:
Experiment No 12
Objective : Design and simulate D Flip-Flops Manual Layout Generation
Apparatus :
Layout Design:
Procedure :
Result :
Conclusion:
