ECE 3103

Digital Electronics
Sequential Logic Circuits

Course Teacher
Dr Rafia Nishat Toma
Associate Professor
ECE Discipline,
Khulna University
Syllabus (Section A)
• Information & Digital Systems
✓ Introduction to digital systems, number systems, weighted and non-weighted
codes, code conversion, binary addition and subtraction, 2‟s complement method.
• Boolean Algebra
✓ Digital logic, Boolean algebra, Boolean function, canonical forms, Karnaugh
maps, minimization of Boolean functions, logic gates and their truth tables, design
methodologies,
• Combinational Logic Circuits
✓ Combinational logic circuit design, arithmetic and data handling logic
circuits, decoder, encoder, multiplexer, demultiplexer.
• Sequential Logic Circuits
✓ SR, JK, T, and D flip-flops, master-slave JK flip-flop, timing diagrams of
different flip-flops, edge-triggered and level triggered timing diagrams, counters, registers,
memory, finite state machine, asynchronous & synchronous sequential systems, reliable
design and fault diagnosis.
2
 Outline
Sequential Logic Circuits

❑ Definition of Flip-flop
❑ S-R, J-K, T, D, and Master-Slave J-K Flip-flops
❑ Conversion from One-type of Flip-flop to Another-type
of Flip-flop
 Flip-flops

❑ Flip-flop:
• The most important memory element is the flip-flop, which is made up of an
assembly of logic gates. Even though a logic gate, by itself, has no storage
capability, several can be connected together in ways that permit information
to be stored.
• Several different gate arrangements are used to produce these flip-flops
(abbreviated as FF). It can be obtained by using NAND and NOR gates. It is a
1-bit memory cell.
• Figure 1 is the general type of symbol used for a flip-flop. It shows two
outputs, labeled Q and Q , that are the inverse of each other.
• Note that the HIGH or 1 state (Q = 1 or Q = 0 )
is also referred to as the SET state. In a similar
way, the LOW or 0 state (Q = 0 or Q = 1 ) is
also referred to as the CLEAR or RESET
state.
• As we shall see, many FFs will have a SET
input and/or a CLEAR (RESET) input that is
used to drive the FF into a specific output state. 4
Figure 1. General flip-flop symbol.
 Flip-flops

❑ NAND Gate Latch:

• The most basic FF circuit can be constructed from either two NAND gates or
two NOR gates. The NAND gate version, called a NAND gate latch or simply
a latch, is shown in Figure 2(a).
• The two NAND gates are cross-coupled so that the output of NAND-1 is
connected to one of the inputs of NAND-2, and vice-versa. The gate outputs,
labeled Q and Q , respectively, are the latch outputs. Under normal conditions,
these outputs will always be the inverse of each other.
• There are Two Latch Inputs:
(1) The SET input is the input that sets Q to the 1 state
(2) The CLEAR input is the input that clears Q to the 0 state

Figure 2. A NAND gate latch.

 Flip-flops

❑ NAND Gate Latch:

• The SET and RESET inputs are both normally resting in the HIGH state,
and one of them will be pulsed LOW whenever we want to change the latch
outputs.
• But there are two equally likely output states when SET = RESET = 1. One
possibility is shown in Figure 2(a), where we have Q = 0 and Q = 0..
• The second possibility is shown in Figure 2(b), where Q = 1 and Q = 1 We shall soon
see, the one that actually exists will depend on what has occurred previously at the
inputs.
• The Function Table for the NAND gate latch is shown in Figure 3.

Figure 3. Function diagram of NAND gate latch.

 Flip-flops

❑ Summary of NAND Gate Latch:

(1) SET = RESET = 1: This condition is the normal resting state, and it
has no effect on the output state. The Q and Q outputs will remain in
whatever state they were in prior to this input condition.
(2) SET = 0, RESET = 1: This will always cause the output to go to the
Q = 1 state, where it will remain even after SET returns HIGH. This is
called setting the latch.
(3) SET = 1, RESET = 0: This will produce the Q = 0 state, where the
output will remain even after CLEAR returns HIGH. This is called
clearing or resetting the latch.
(4) SET = RESET = 0: This condition tries to set and clear the latch at
the same time and can produce ambiguous results. It should not be used.
 Flip-flops

❑ NOR Gate Latch:

• Two cross-coupled NOR gates can be used as a NOR gate latch. The
arrangement, shown in Figure 4(a), is similar to the NAND latch except that
the Q and Q outputs have reversed positions.

Figure 4. (a) NOR gate latch; (b) function table; (c) simplified block symbol.
• The analysis of the operation of the NOR latch can be performed in exactly the
same manner as for the NAND latch. The results are shown in Figure 4(b) and
are summarized as follows:
(1) SET = CLEAR = 0: This is the normal resting state for the NOR gate
latch and it has no effect on the output state. Q and Q will remain in
whatever state they were in prior to the occurrence of this input condition.
 Flip-flops

❑ NOR Gate Latch:

(2) SET = 1, CLEAR/RESET = 0: This will always set Q = 1, where it
will remain even after SET returns to 0.
(3) SET = 0, CLEAR/RESET = 1: This will always clear Q = 0, where it
will remain even after CLEAR returns to 0.
(4) SET = 1, CLER/RESET = 1: This condition tries to set and clear the
latch at the same time and it produces Q = Q = 0. If the inputs are
returned to 0 simultaneously, the resulting output state is unpredictable.
This input condition should not be used.

• The simplified block symbol for the NOR latch is shown in Figure 4(c) with S
and R inputs with no bubbles; this indicates that these inputs are active-HIGH.

• The NOR latch can be considered as S-R flip-flop.

 Flip-flops

❑ Clock Signals and Clocked Flip-flops:

• Digital systems can operate either asynchronously or synchronously. In
asynchronous systems, the outputs of logic circuits can change state any time
one or more of the inputs change. An asynchronous system is generally more
difficult to design and troubleshoot than a synchronous system.
• In synchronous systems, the exact time at which any output can change states
are determined by a signal commonly called the clock. This clock signal is
generally a rectangular pulse train or a square wave as shown in Figure 6.

Figure 5. Clock signal. (a) Rectangular pulse; (b) square wave.

 Flip-flops

❑ Clock Signals and Clocked Flip-flops:

• The clock signal is distributed to all parts of the system, and most of the
system outputs can change state only when the clock makes a transition. When
the clock goes from a 0 to a 1, this is called positive-going transition (PGT);
when the clock goes from a 1 to a 0, this is called negative-going transition
(NGT).
• Most digital systems are principally synchronous, since synchronous circuits
are easier to design and troubleshoot (the circuit outputs can change only at
specific instants of time). The synchronizing action of the clock signals is
accomplished through the use of clocked flip-flops that are designed to change
states on one or the other of the clock’s transition.
 Flip-flops

❑ Clock Signals and Clocked Flip-flops:

✓ Clocked Flip-flops:-
• Several types of clocked FFs are used in a wide range of applications. Before
we begin our study of the different clocked FFs, we will describe the principal
ideas that are common to all of them.
(1) Clocked FFs have a clock input that is typically labeled CLK, CK, or CP.
We will normally use CLK, as shown in Figure 7. In most clocked
FFs, the CLK input is edge-triggered, which means that it is activated by a
signal transition, that is indicated by the presence of a small triangle on the
CLK input. Figure 7(a) is a FF with a small triangle on its CLK input to
indicate that this input is activated only when a positive-going transition
(PGT) occurs; in Figure 7(b) the FF symbol has a bubble as well as a
triangle on its CLK input. This signifies that the CLK input is activated
only when a negative-going transition (NGT) occurs.
(2) Clocked FFs also have one or more control inputs that can have
various names, depending on their operation. The control inputs will have
no effect on Q until the active clock transition occurs. For this reason, they
are called synchronous control inputs.
 Flip-flops

❑ Clock Signals and Clocked Flip-flops:

✓ Clocked Flip-flops:-

Figure 6. Clocked FFs have a clock input that is active on either (a) PGT; (b) NGT.
 Flip-flops

❑ S-R/S-C Latch/Flip-flop:

Trigger

(a) (b) (c)

Figure 7. (a) Excitation table of S-R/S-C latch; (b) K-map of latch output Q* of S-R latch; (c) symbol
of S-R latch.

 The characteristic equation of the S-R latch is ~ Q = S + RQ

 Flip-flops

❑ S-R/S-C Latch/Flip-flop:
 Flip-flops
❑ Clocked S-C/S-R Flip-flop:
• Figure 8(a) shows the logic symbol for a clocked S-C flip-flop that is
triggered by the positive-going edge of the clock signal. This means that the FF can
change states only when a signal applied to its clock input makes a transition from
0 to 1. The truth table in Figure 8(b) shows how the FF output will respond to
the PGT at the CLK input for the various combinations of S and R inputs. The
waveforms in Figure 8(c) illustrate the operation of the clocked S-R flip-flop. The
logic diagram of the clocked S-R FF is shown in Figure 8(d).

(b)
Figure 8. Clocked S-R flip-flop. (a) Symbol; (b) truth table.
 Flip-flops

❑ Clocked S-C/S-R Flip-flop:

(d)

(e)
Figure 9. Clocked S-R flip-flop. (c) Waveforms; (d) logic diagram; (c) K-map for Q*.
• Here initially all inputs are 0 and Q output is assumed to be 0.
• The characteristic equation for clocked S-R FF is: Q = S + RQ
 Flip-flops
❑ Clocked J-K Flip-flop:
• Figure 10(a) shows a clocked J-K flip-flop that is triggered by the positive-
going edge of the clock signal. The J and K inputs control the state of the FF in the
same ways as the S and R inputs do for the clocked S-R flip-flop except for one major
difference: the J = K = 1 conditions does not result in an ambiguous output.
• This FF can change states only when a signal applied to its CLK input makes a
transition from 0 to 1. The truth table for clocked J-K FF is illustrated in
Figure 10(b). The waveforms in Figures 10(c) show the operation of the
clocked J-K FF. Logic diagram of clocked J-K FF is shown in Figure 10(d).

(a) (b)
Figure 10. Clocked J-K flip-flop. (a) Symbol; (b) truth table.
 Flip-flops
❑ Clocked J-K Flip-flop:

(d)

(c) (e)
Figure 11. Clocked J-K flip-flop. (c) Waveforms; (d) logic diagram; (e) K-map for Q*.
• Figure 11(e) represents the k-map for clocked J-K FF. The characteristic
equation of clocked J-K FF becomes: Q = JQ + KQ

• Here initially in Figure 11(c)) all inputs are 0, and the Q output is assumed to be 1.
 Flip-flops

❑ Clocked J-K Flip-flop:

 Flip-flops
❑ Clocked D Flip-flop:
• The D flip-flop is a modification of the clocked S-R FF. Figure 12(a) shows the
logic symbol used to represent clocked D FF. Figure 12(b) shows the
truth table for clocked D flip-flop. Figure 12(c) shows the logic diagram for a
clocked D FF. The D inputs go directly to the S input and its complement is
applied to the R input.
• When the clock input is at 0, gates 1 and 2 have a 1 in their outputs, regardless of the
value of the other inputs. The D input is sampled during the occurrence of a clock
pulse. If it is 1, then the flip-flop will go to the SET state (unless it was already SET).
If it is 0, the flip-flop will go to the RESET state.

(a) (b)
Figure 12. Clocked D flip-flop. (a) Symbol; (b) truth table.
 Flip-flops
❑ Clocked D Flip-flop:
• Figure 13(d) represents the k-map for the clocked D flip-flop. The
waveforms of Figure 13(e) illustrates the operation of clocked D flip-flop.

(c)

(d) (e)
Figure 13. Clocked D flip-flop. (c) Logic diagram; (d) k-map for Q*; (e) waveforms.
• The characteristic equation of the clocked D flip-flop is: Q = D
 Flip-flops

❑ Clocked D Flip-flop:
 Flip-flops
❑ Clocked T Flip-flop:
• The T flip-flop is a single-input version of the clocked J-K flip-flop. Figure
14(a) shows the logic symbol used to represent the clocked T flip-flop. The
clocked T flip-flop is obtained from a clocked J-K flip-flop if both inputs are
tied together. The designation T comes from the ability of the flip-flop the
“toggle” or change state.
• Figure 14(b) represents the truth table for clocked T flip-flop. Regardless of the
present state of the flip-flop, it assumes the complement state when the
clock pulse occurs while input T is logic-1.

(a) (b)
Figure 14. Clocked T flip-flop. (a) Symbol; (b) truth table.
 Flip-flops
❑ Clocked T Flip-flop:
• Figure 15(c) shows the logic diagram for clocked T flip-flop. Figure 15(d)
shows the k-map for clocked T flip-flop. The waveforms of clocked T flip-
flop is illustrated in Figure 15(e).

(c)

(d) (e)
Figure 15. Clocked T flip-flop. (c) Logic diagram; (d) k-map; (e) waveforms.
• The characteristic equation of the clocked T flip-flop is: Q = TQ + TQ = T  Q
 Flip-flops

❑ Clocked T Flip-flop:
 Flip-flops

❑ Conversion from One Type of Flip-flip to Another Type:

 Flip-flops

❑ Conversion from One Type of Flip-flip to Another Type:

✓ Conversion from an S-R Flip-flop to a J-K Flip-flop:-
• The truth table of S-R and J-K flip-flops are given in Figure 16(a). Figure 16(b)
and 16(c) represent the k-maps for the conversion.

(b)

(a) (c)
Figure 16. Conversion from S-R to J-K. (a) Truth table; (b) k-map for S; (c) k-map for R.
 Flip-flops

❑ Conversion from One Type of Flip-flip to Another Type:

✓ Conversion from an S-R Flip-flop to a J-K Flip-flop:-
• Then S = JQ and R = KQ

Figure 17. Conversion from S-R to J-K. (d) logic diagram of J-K flip-flop.
 Flip-flops

❑ Conversion from One Type of Flip-flip to Another Type:

✓ Conversion from an S-R Flip-flop to a D Flip-flop:-
• The truth table of S-R and D flip-flops are given in Figure 18(a). Figure
18(b) and 18(c) represent the k-maps for the conversion.

(a) (b) (c)

Figure 18. Conversion from S-R to D. (a) Truth table; (b) k-map for S; (c) k-map for R.

• Thus, S = D and R = D .
 Flip-flops

❑ Conversion from One Type of Flip-flip to Another Type:

✓ Conversion from a J-K Flip-flop to a D Flip-flop:-
• The truth table of J-K and D flip-flops are given in Figure 19(a). Figure
19(b) and 19(c) represent the k-maps for the conversion.

(a) (b) (c)

Figure 19. Conversion from J-K to D. (a) Truth table; (b) k-map for J; (c) k-map for K.

• Thus, J = D and K = D .
 Flip-flops

❑ Conversion from One Type of Flip-flip to Another Type:

✓ Conversion from a T Flip-flop to an S-R Flip-flop:-
• The truth table of T and S-R flip-flops are given in Figure 20(a). Figure
20(b) and 20(c) represent the k-maps for the conversion.

(a) (b)
Figure 20. Conversion from T to S-R. (a) Truth table; (b) k-map for T.
• Thus, T = SQ + RQ
 Flip-flops

❑ Conversion from One Type of Flip-flip to Another Type:

✓ Conversion from a J-K Flip-flop to an S-R Flip-flop:-
• The truth table of J-K and S-R flip-flops are given in Figure 21(a). Figure
21(b) and 21(c) represent the k-maps for the conversion.

(b)

(a) (c)
Figure 21. Conversion from J-K to S-R. (a) Truth table; (b) k-map for J; (c) k-map for K.
• Thus, J = S and K = R.
 Flip-flops
❑ Setup Time:
• The setup time, ts, is the time interval immediately preceding the active
transition of the CLK signal during which the control input must be
maintained at the proper level, as shown in Figure 22(a).
❑ Hold Time:
• The hold time, tH, is the time interval immediately following the active
transition of the CLK signal during which the control input must be
maintained at the proper level, as shown in Figure 22(b).

Figure 22. (a) Setup time; (b) hold time.

 Flip-flops

❑ Asynchronous Inputs:
• For the clocked flip-flops such as S, R, J, K, D, and T inputs have been
referred to as control inputs. These inputs are also called synchronous inputs,
because their effect on the FF output is synchronized with the CLK input.
• Most clocked FFs also have one or more asynchronous inputs, which operate
independently of the synchronous inputs and clock input. These asynchronous
inputs can be used to set the FF to the 1 state or clear the FF to the 0 state at
any time, regardless of the conditions at the other inputs, which can be used to
override all other inputs in order to place the FF in one state or the other.
• Figure 23(a) shows a J-K flip-flop with two asynchronous inputs, designated as
PRE and CLR (these asynchronous inputs are active-LOW). The
accompanying truth table (Figure 23(b) summarizes how they affect the FF
output. Let’s examine various cases:
(1) PRE = CLR = 1: Asynchronous inputs are inactive and the FF is free
to respond to the J, K, and CLK inputs; in other words, the clocked
operation can take place.
(2) PRE = 0;CLR = 1:The PRE (PRESET) is activated and Q is
immediately SET to 1 no matter what conditions are present at the J, K,
and CLK inputs.
 Flip-flops

❑ Asynchronous Inputs:
(3) PRE = 1;CLR = 0 : The CLR (CLEAR) is activated and Q is
immediately cleared to 0 independent of the conditions on the J, K, or
CLK inputs.
(4) PRE = CLR = 0: This condition should not be used, since it can
result in an ambiguous response.

Figure 23. Clocked J-K flip-flop with asynchronous inputs. (a) symbol; (b) truth table.
 Flip-flops

❑ Potential Timing Problem in Flip-flop Circuits:

• In many digital circuits, the output of one FF is connected either directly or
through logic gates to the input of another FF, and both FFs are triggered by
the same clock signal. This presents a potential timing problem. A typical
situation is illustrated in Figure 24, where the output of Q1 is connected to the
J input of Q2 and both FFs are clocked by the same signal at their CLK
inputs.

Figure 24. Timing problem in the flip-flop circuits.

 Flip-flops

❑ Potential Timing Problem in Flip-flop Circuits:

• The Potential Timing Problem is This: Since Q1 will change on the NGT of the
clock pulse, the J2 input of Q2 will be changing as it receives the same NGT. This
could lead to an unpredictable response at Q2.
• Let’s assume that initially Q1 = 1 and Q2 = 0. Thus, the Q1 FF has J1 = K1 = 1, and Q2
has J2 = Q1 = 1, K2 = 0 prior to the NGT of the clock pulse. When the NGT occurs, Q1
will toggle to the LOW state, but it will not actually go LOW until after its
propagation delay tPHL. The same NGT will reliably clock Q2 to the HIGH state
provided that tPHL is greater than Q2’s hold time requirement., tH. If this condition is not
met, the response of the Q2 will be unpredictable.
• Fortunately all modern edge-triggered FFs have hold time requirements that are 5 ns or
less; most have tH = 0. For these FFs, situations like that of Figure 24 will not be a
problem.
• From now, we will assume that the FF’s hold time requirement is short enough to
respond reliably to the following rule:
“The FF output will go to a state determined by the logic levels present at its
synchronous control inputs just prior to the active clock transition.”
• If we apply apply this rule to Figure 24, it says that Q2 will go to a state determined by
the J2 = 1, K2 = 0 condition that is present just prior to the NGT of the clock pulse. The
fact that J2 is changing in response to the same NGT has no effect.
 Flip-flops

❑ The Race-around Conditions:

(a) (b)
Figure 25. (a) race-around condition for J-K flip-flop (b) Solve with Master-slave J-K flip-flop .
 Flip-flops
❑ Master-Slave Flip-flops:
• A Master-Slave flip-flop actually contains two FFs-a Master and a Slave. On
the rising edge of the CLK signal, the levels on control inputs (D, J, K) are
used to determine the output of the Master. When the CLK signal goes LOW,
the state of the Master is transferred to the Slave, whose outputs are Q and Q .
Thus Q and Q change just after the NGT of the clock (Figure 26).
• These Master-Slave FFs function very much like the negative-edge-triggered
FFs except for one major disadvantage: The control inputs must be held stable
while CLK is HIGH, or unpredictable may occur. This problem of Master-
Slave FFs has been overcome with an improved Master-Slave version called
a Master-Slave data lockout. The Master-Slave FF has become obsolete,
although you may encounter it in older equipment.

Figure 26. Logic diagram of Master-Slave S-R flip-flop.

 Flip-flops

❑ The Master-Slave J-K Flip-flop:

• A Master-Slave J-K flip-flop is a cascade of two S-R flip-flops with feedback from the
outputs of the second to the inputs of the first as illustrated in Figure 27(a). Positive clock
pulses are applied to the first flip-flop and the clock pulses are inverted before these are applied
to the second flip-flop.

(b)

(a) (c)
Figure 27. Master-slave J-K flip-flop. (a) Logic diagram; (b) symbol; (c) truth table.
 Flip-flops

❑ The Master-Slave J-K Flip-flop:

References
1 “Digital Systems: Principles and Applications,” Neal S. Widmer, Gregory L.
Moss, and Ronald J. Tocci, 12th Ed., Pearson (2018).

2 “Digital Logic Circuit Analysis and Design,” Victor P. Nelson, H. Troy

Nagle, Bill D. Carroll, and David Irwin, 1st Ed., Pearson (1995).

3 “Switching and Finite Automata Theory,” Zvi Kohavi and Niraj

K. Zha, 3rd Ed., Cambridge University Press (2009).

4 “Modern Digital Electronics,” R. P. Jain, 4th Ed., McGraw-Hill (2010).

5 “Digital Electronics: An Introduction to Theory and Practice,”

William H. Gothmann, 2nd Ed., Prentice Hall (1982).

6 Online Resources.