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Expt 7

The document outlines a lab experiment for CSE345 Digital Logic Design at East West University, focusing on Verilog simulation of a sequential circuit. It includes objectives, an introduction to explicit style Verilog coding, a sample Verilog code, and instructions for simulation using Quartus II software. Additionally, it presents pre-lab and post-lab report questions related to the circuit design and simulation tasks.

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2023-2-60-284
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15 views2 pages

Expt 7

The document outlines a lab experiment for CSE345 Digital Logic Design at East West University, focusing on Verilog simulation of a sequential circuit. It includes objectives, an introduction to explicit style Verilog coding, a sample Verilog code, and instructions for simulation using Quartus II software. Additionally, it presents pre-lab and post-lab report questions related to the circuit design and simulation tasks.

Uploaded by

2023-2-60-284
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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East West University

Department of Computer Science and Engineering

Course: CSE345 Digital Logic Design


Expt No.: 7
Title: Verilog Simulation of Sequential Circuit

Objective:
1.​ To learn explicit style Verilog coding of a sequential logic circuit.

Introduction:
Explicit style Verilog description of sequential logic circuit is discussed in Section 14.6 of
textbook 1. The explicit style Verilog code for the sequential logic circuit of Figure 1 is shown below:

module lab7
​ (input x, clock, reset,
​ output reg y);
​ reg [1:0] CS, NS;
​ always@(*)
​ ​ case (CS)
​ ​ 0:​ begin
​ ​ ​ NS = (x == 0) ? 1:0;
​ ​ ​ y = (x == 0) ? 0:1;
​ ​ ​ end
​ ​ 1:​ begin
​ ​ ​ NS = (x == 0) ? 2:3;
​ ​ ​ y = (x == 0) ? 1:0;
​ ​ ​ end
​ ​ 2:​ begin
​ ​ ​ NS = (x == 0) ? 0:1;
​ ​ ​ y = (x == 0) ? 1:0;
​ ​ ​ end
​ ​ 3:​ begin
​ ​ ​ NS = (x == 0) ? 3:2;
​ ​ ​ y = (x == 0) ? 0:1;
​ ​ ​ end
​ ​ endcase
​ always @(posedge clock, negedge reset)
​ ​ if(~reset)
​ ​ ​ CS <= 0;
​ ​ else
​ ​ ​ CS <= NS;
endmodule

Page 1 of 2
Figure 1. Transition diagram of an example sequential logic Circuit.

The simulation output is shown in Figure 2. The CS is first reset to 00 by changing the reset signal
from 1 to 0 and then to 1 (active-LOW reset). For this purpose, two time slots are used. Two time slots
are used per clock for easy observation of the waveforms. There are four CS and the input x has two
possible values. Therefore, there are 4×2 = 8 possibilities of changing the CS. Therefore, 2 + 2×8 = 18
time slots are used in total. The value of the input x is so chosen that all transition of the CS can be
observed.

Figure 2. Simulation output of explicit style Verilog code for the sequential circuit of Figure 1.

Pre-Lab Report Question:


1.​ Write explicit style Verilog code for the sequential logic circuit of Figure 3.

Figure 3: Transition diagram of a sequential logic circuit for lab practice.

Lab Procedure:
1.​ Simulate the Verilog code from your pre-lab report using Quartus II software. Get printout of
Verilog code and simulation output and have it signed by your instructor.

Post-Lab Report Question:


1.​ Write explicit style Verilog code for a ÷4 up/down counter and simulate the Verilog code using
Quartus II software.

Page 2 of 2

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