ISOTMP35-Q1

SNIS234A – OCTOBER 2023 – REVISED JUNE 2024

ISOTMP35-Q1 Automotive ±1.5°C, 3-kVRMS Isolated Temperature Sensor With Analog

Output With < 2 Seconds Response Time and 500VRMS Working Voltage
1 Features 3 Description
• AEC-Q100 qualified with: The ISOTMP35-Q1 is the industry’s first isolated
temperature sensor IC, combining an integrated
– Temperature grade 0: –40°C to 150°C Ambient
isolation barrier, up to 3000VRMS withstand voltage,
Operating Temperature Range
with an analog temperature sensor featuring a
– Device HBM ESD classification level 2
10mV/°C slope from –40°C to 150°C. This integration
– Device CDM ESD classification level C5
enables the sensor to be co-located with high voltage
• Functional Safety-Capable
heat sources (for example: HV FETs, IGBTs, or
– – Documentation available to aid functional HV contactors) without requiring expensive isolation
safety system design circuitry. The direct contact with the high-voltage heat
• Robust integrated isolation barrier: source also provides greater accuracy and faster
– Withstand isolation voltage: 3000VRMS thermal response compared with approaches where
– Isolation working voltage: 500VRMS the sensor is placed further away to meet isolation
• Isolation barrier life: > 50 years requirements.
• Temperature sensor accuracy
– ±0.5°C typical at 25°C Operating from a non-isolated 2.3V to 5.5V supply,
– ±1.5°C maximum from 0°C to 70°C the ISOTMP35-Q1 allows easy integration into
– ±2.0°C maximum from –40°C to 150°C applications where sub-regulated power is not
• Operating supply range: 2.3V to 5.5V available on the high-voltage plane.
• Positive slope sensor gain: 10mV/°C, with 500mV The integrated isolation barrier satisfies UL 1577
offset at 0°C requirements. The surface mount package (7-pin
• Fast thermal response: < 2 seconds SOIC) provides excellent heat flow from the heat
• Short circuit protected output source to the embedded thermal sensor, minimizing
• Low power consumption: 9µA (typical) thermal mass and providing more accurate heat-
• DFQ (SOIC-7) package source measurement. This reduces the need for time-
• Safety-related certifications (planned): consuming thermal modeling and improves system
– 3kVRMS isolation for 1 minute per UL 1577 design margin by reducing mechanical variations due
to manufacturing and assembly.
2 Applications
The ISOTMP35-Q1 class-AB output driver provides
• Silicon Carbide (SiC) PowerFET temperature a strong 500μA maximum output to drive capacitive
monitoring loads up to 1000pF and is designed to directly
• Insulated-Gate Bipolar Transistor (IGBT) interface with analog-to-digital converter (ADC)
PowerFET temperature monitoring sample and hold inputs.
• HEV/EV battery-management system (BMS)
• HEV/EV on-board charger (OBC) & wireless Packaging Information
charger PART NUMBER PACKAGE(1) PACKAGE SIZE(2)
• HEV/EV DC/DC converter ISOTMP35-Q1 DFQ (SOIC, 7) 4.9mm × 6mm
• HEV/EV inverter & motor control
(1) For all available packages, see the orderable addendum at
• Powertrain temperature sensor the end of the data sheet.
(2) The package size (length × width) is a nominal value and
includes pins, where applicable.

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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VDD

Isola on Barrier
TSENSE

Thermal Diodes

Heat only

TSENSE
VOUT

TSENSE

GND

Functional Block Diagram

TI Device
5 TSENSE VOUT 4 VOUT

ISOLATION BARRIER
High GND 3
Voltage 6 TSENSE
Heat GND
NC 2
Source

7 TSENSE VDD 1 VDD

0.1µF
GND
Typical Application

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Table of Contents
1 Features............................................................................1 6.3 Features Description................................................. 11
2 Applications..................................................................... 1 6.4 Device Functional Modes..........................................15
3 Description.......................................................................1 7 Application and Implementation.................................. 15
4 Pin Configuration and Functions...................................4 7.1 Application Information............................................. 15
5 Specifications.................................................................. 5 7.2 Typical Application.................................................... 20
5.1 Absolute Maximum Ratings........................................ 5 7.3 Power Supply Recommendations.............................22
5.2 ESD Ratings............................................................... 5 7.4 Layout....................................................................... 22
5.3 Recommended Operating Conditions.........................5 8 Device and Documentation Support............................23
5.4 Thermal Information....................................................5 8.1 Documentation Support............................................ 23
5.5 Insulation Specification............................................... 6 8.2 Receiving Notification of Documentation Updates....23
5.6 Power Ratings.............................................................7 8.3 Support Resources................................................... 23
5.7 Safety-Related Certifications...................................... 7 8.4 Trademarks............................................................... 23
5.8 Safety Limiting Values.................................................7 8.5 Electrostatic Discharge Caution................................23
5.9 Electrical Characteristics.............................................8 8.6 Glossary....................................................................23
5.10 Typical Characteristics.............................................. 9 9 Revision History............................................................ 23
6 Detailed Description...................................................... 11 10 Mechanical, Packaging, and Orderable
6.1 Overview................................................................... 11 Information.................................................................... 23
6.2 Functional Block Diagram......................................... 11

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4 Pin Configuration and Functions

VDD 1 7 TSENSE

NC 2
6 TSENSE
GND 3

VOUT 4 5 TSENSE

Figure 4-1. DFQ Package 7-Pin SOIC Top View

Table 4-1. Pin Functions

PIN
TYPE(1) DESCRIPTION
NAME DFQ
GND 3 G Ground
NC 2 – No connect

5
TSENSE 6 – Temperature pin connected to high-voltage heat source
7
VDD 1 P Supply voltage
VOUT 4 O Output voltage proportional to temperature

(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.

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5 Specifications
5.1 Absolute Maximum Ratings
Over free-air temperature range unless otherwise noted(1)
MIN MAX UNIT
Supply voltage VDD –0.3 6 V
Output voltage VOUT –0.3 VDD + 0.3 V
Output current VOUT –30 30 mA
Operating junction temperature, TJ –60 155 °C
Storage temperature, Tstg –65 155 °C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

5.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per AEC Q100-002(1)
±2500
HBM ESD Classification Level 2
V(ESD) Electrostatic discharge V
Charged device model (CDM), per AEC Q100-011
±1000
CDM ESD Classification Level C5

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification

5.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VDD Supply voltage 2.3 5.5 V
TA Operating ambient temperature –40 150 °C

5.4 Thermal Information

ISOTMP35-Q1
THERMAL METRIC(1) DFQ (SOIC) UNIT
7 PINS
RθJA Junction-to-ambient thermal resistance 116.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 62.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 38.8 °C/W
RθJB Junction-to-board thermal resistance 41.9 °C/W
ψJT Junction-to-top characterization parameter 38.3 °C/W
ψJB Junction-to-board characterization parameter N/A °C/W
MT Thermal Mass 51.0 mJ/°C

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

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5.5 Insulation Specification

Over free-air temperature range and VDD = 2.3V to 5.5V (unless otherwise noted); Typical specifications are at TA = 25°C and
VDD = 3.3V (unless otherwise noted)
PARAMETER TEST CONDITIONS VALUE UNIT
GENERAL
CLR External Clearance(1) Shortest terminal-to-terminal distance through air >4 mm
Shortest terminal-to-terminal distance across the package
CPG External Creepage(1) >4 mm
surface
DTI Distance through the insulation Minimum internal gap (internal clearance) >17 µm
CTI Comparative tracking index DIN EN 60112; IEC 60112 >400 V
Material Group II
Rated mains voltage ≤ 150VRMS I-IV
Overvoltage category
Rated mains voltage ≤ 300VRMS I-III
DIN EN IEC 60747-17 (VDE 0884-17)
Maximum repetitive peak isolation
VIORM At AC voltage 707 VPK
voltage

Maximum-rated isolation working At AC voltage (sine wave) 500 VRMS

VIOWM
voltage At DC voltage 707 VDC
VTEST = VIOTM, t = 60s (qualification test),
VIOTM Maximum transient isolation voltage 4250 VPK
VTEST = 1.2 × VIOTM, t = 1s (100% production test)
VIMP Maximum impulse voltage(2) Tested in air, 1.2/50-μs waveform per IEC 62368-1 5000 VPK
Tested in oil (qualification test),
VIOSM Maximum surge isolation voltage(3) 6500 VPK
1.2/50-μs waveform per IEC 62368-1
Method a, after input/output safety test subgroups 2 and 3,
≤5
Vpd(ini) = VIOTM, tini = 60s, Vpd(m) = 1.2 × VIORM, tm = 10s
Method a, after environmental tests subgroup 1,
≤5
Vpd(ini) = VIOTM, tini = 60s, Vpd(m) = 1.3 × VIORM, tm = 10s
qpd Apparent charge(4) pC
Method b1, at preconditioning (type test) and routine test,
≤5
Vpd(ini) = VIOTM, tini = 1s, Vpd(m) = 1.5 × VIORM, tm = 1s
Method b2, at routine test (100% production)(6),
≤5
Vpd(ini) = VIOTM = Vpd(m); tini = tm = 1s
Barrier capacitance,
CIO VIO = 0.1VPP at 100kHz 1.4 pF
input to output(5)
VIO = 500V at TA = 25°C >1012
Insulation resistance,
RIO VIO = 500V at 100°C ≤ TA ≤ 125°C >1011 Ω
input to output(5)
VIO = 500V at TA = 150°C >109
Pollution degree 2
Climatic category 55/125/21
UL1577
VTEST = VISO, t = 60s (qualification);
VISO Withstand isolation voltage 3000 VRMS
VTEST = 1.2 × VISO, t = 1s (100% production)

(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Take care
to maintain the creepage and clearance distance of the board design to make sure that the mounting pads of the isolator on the
printed circuit board do not reduce this distance. Creepage and clearance on a printed circuit board become equal in certain cases.
Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.
(2) Testing is carried out in air to determine the surge immunity of the isolation barrier.
(3) Testing is carried out in oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-terminal device.
(6) Either method b1 or b2 is used in production.

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5.6 Power Ratings

VS = 5.5 V, TA = 125℃, TJ = 150℃, device soldered on the device evaluation board.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PD2 Maximum power dissipation by (side-2) VS = 5.5 V, IQ = 17μA, no VOUT load 94 μW

5.7 Safety-Related Certifications

UL
UL 1577 Component Recognition Program Certified according to IEC 62368-1 CB
File number: Pending Certificate number: Pending

5.8 Safety Limiting Values

Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Safety input, output, or supply current
IS RθJA = 116.4°C/W, VI = 5V, TJ = 150°C, TA = 25°C 0.22 A
(side 2)(1)
PS Safety input, output, or total power(1) RθJA = 116.4°C/W, TJ = 150°C, TA = 25°C 1.1 W
TS Safety temperature(1) 150 ℃

(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The
IS and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS must not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Section 5.4 table is that of a device installed on a device evaluation board. Use
these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.

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5.9 Electrical Characteristics

Over free-air temperature range and VDD = 2.3V to 5.5V (unless otherwise noted); Typical specifications are at TA = 25°C and
VDD = 3.3V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TEMPERATURE SENSOR
TERR Temperature accuracy 0°C to 70°C –1.5 ±0.5 1.5 °C
TERR Temperature accuracy -40°C to 150°C –2.5 ±0.5 2.5 °C
PSR DC power supply rejection –0.1 0.02 0.1 °C/V
TSENS Temperature sensitivity TA = -40°C to 150°C 10.00 mV/°C
TLTD Long-term drift(1) 300 hours at 150°C, 5.5V .05 °C
TA = 0°C 500 mV
VOUT Output voltage
TA = 25°C 750 mV
NL Nonlinearity TA = –40°C to 150°C 0.5 °C
τ = 63 %
2-layer 62-mil Rigid PCB
tRESP_D Directional Response time TSENSE = 25°C to 75°C 1600 ms
2oz. Copper
Pins 1 to 4 = 25°C
0.5in x 0.5in, τ = 63 %
tRESP_L Response time (Stirred Liquid) 1600 ms
2-layer 62-mil PCB 25°C to 150°C
ANALOG OUTPUT
ILOAD = 100μA, f = 100Hz 20 Ω
ZOUT Output impedance
ILOAD = 100μA, f = 500Hz 50 Ω
IOUT Output current 500 μA
VCM= 500V, ΔVOUT <
Common Mode Transient
CMTI 200mV, 2μs, CLOAD= 50 kV/μs
Immunity
1nF, RLOAD = 5kΩ
LR Load regulation ILOAD = 0 μA to 500 μA 6 mV
CL Maximum capacitive load 1 nF
POWER SUPPLY
VDD = 3.3V
10 12 μA
IDD Operating current TA = 25°C
TA = –40°C to 150°C 17 μA

(1) Long term stability is determined using accelerated operational life testing at a junction temperature of 150°C.

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5.10 Typical Characteristics

at TA = 25°C (unless otherwise noted)

6
Average
Avg r3V
4 Limits

2
Accuracy (qC)

-2

-4

-6
-50 -25 0 25 50 75 100 125 150
TA (qC) D001

VDD = 2.3 to 5.5V, IOUT = 0µA, CLOAD = 1000pF

IOUT = 0µA, CLOAD = 1000pF
Figure 5-1. Accuracy vs TA Temperature
Figure 5-2. Output Voltage vs Ambient
Temperature
0.1 14
 Accuracy Due to Load (°C)

0.05 12
IDD (A)

0 10

-0.05 8

VDD = 2.3V
VDD = 5.5V VDD = 2.3V
-0.1 6
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
TA (°C) TA (°C)

IOUT = from 0µA to 100µA, CLOAD = 1000pF IOUT = 0µA, CLOAD = 1000pF

Figure 5-3. Changes in Accuracy vs Ambient Figure 5-4. Supply Current vs Temperature
Temperature (Due to Load)

VDD = 2.3V, CLOAD = 1000pF VDD = 2.3 to 5.5V, IOUT = 0µA, CLOAD = 1000pF

Figure 5-5. Load Regulation vs Ambient Figure 5-6. Line Regulation (Δ°C / ΔVDD) vs
Temperature Ambient Temperature

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1 2.25
2
0.8 1.75
1.5
0.6

Voltage (V)
1.25
VOUT (V)

1
0.4
0.75
0.5
0.2
0.25
0
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 -0.25
VDD (V) D008 -1 -0.5 0 0.5 1 1.5 2 2.5 3 3.5
Time (ms)
TA = 25°C
TA = 25°C
Figure 5-7. Output Voltage vs Power Supply
Figure 5-8. Output vs. Settling Time to Step VDD
1.25 175

1 150

125

Temperature (°C)
0.75
Voltage (V)

100
0.5
75
0.25
50

0 25

-0.25 0
-0.25 0.25 0.75 1.25 1.75 2.25 2.75 -2 0 2 4 6 8 10 12 14 16
Time (ms) Time (s)

TA = 25°C, VDD Ramp Rate = 5V/ms 0.5 × 0.5 inch PCB, Air 25°C to Fluid Bath 150°C

Figure 5-9. Output vs. Settling Time to Ramp VDD Figure 5-10. Thermal Response (Air-to-Fluid Bath)
2000 0
1000
500
-20
Output Impedance ()

300
200
AC PSRR (dB)

100
-40
50
30
20
10 -60

5
3
2 -80
1 2 3 5 710 20 50 100 1000 10000 100000 1 2 3 5 10 20 100 1000 10000 100000 1000000
Frequency (Hz) Frequency (Hz)

TA = 25°C, VDD = 5V, IOUT = 100µA TA = 25°C

Figure 5-11. Output Impedance vs Frequency Figure 5-12. PSRR vs Frequency

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50000
40000
30000

Noise Density (nV/Hz)

20000

10000

7000

5000
4000
3000

2000
10 20 30 50 70100 200 500 1000 2000 5000 10000
Frequency (Hz)

TA = 25°C

Figure 5-13. Output Noise Density

6 Detailed Description
6.1 Overview
The ISOTMP35-Q1 is a linear analog output temperature sensor with an output voltage proportional to
temperature. The temperature sensor has an accuracy from 0°C to 70°C of ±1.2°C. The ISOTMP35-Q1 provides
a positive slope output of 10mV/°C over the full –40°C to 150°C and a supply range from 2.3V to 5.5V. A
class-AB output driver provides a maximum output of 500µA to drive capacitive loads up to 1000pF.
6.2 Functional Block Diagram

VDD
Isola on Barrier

TSENSE

Thermal Diodes

Heat only

TSENSE
VOUT

TSENSE

GND
Figure 6-1. Functional Block Diagram

6.3 Features Description

The ISOTMP35-Q1 device combines a robust integrated isolation barrier with a tight accuracy analog output
temperature sensor. All the features related to the analog output, accuracy, output characteristics of the sensor,
and drive characteristic of the output are treated under the analog output section.

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6.3.1 Integrated Isolation Barrier and Thermal Response

The ISOTMP35-Q1 is designed to integrate a robust isolation barrier while maximizing the heat flow. This is
made possible by a SO-7 package designed to provide the 3-kVRMS isolating rating (UL1577) and isolation
mechanism that minimizes the thermal response from the TSENSE pins to the temperature sensor.

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6.3.2 Analog Output

The analog output of the ISOTMP35-Q1 has several characteristics, such as the output accuracy, linearity and
drive capability, that must be understood to design the interface to the rest of the signal chain.
6.3.2.1 Common Mode Transient Immunity (CMTI)
CMTI is the capability of the device to tolerate a rising or falling voltage step on the high voltage pins without
coupling significant disturbance on the output signal. The device is specified for the maximum common-mode
transition rate under which the output signal does not experience a disturbance greater than 200mV lasting
longer than 2µs, as shown in Common-Mode Transient Response with a 50kV/ns common-mode input step.
Here, a 1nF load capacitor is utilized along with a 5kΩ load resistor as the load conditions. Higher edge rates
than the specified CMTI can be supported with sufficient blanking time after common-mode transitions.
1500 1.6
VCM
VOUT
1250 1.2
Common Mode Voltage (V)

1000 0.8

Output Voltage (V)

750 0.4

500 0

250 -0.4

0 -0.8

-250 -1.2
-2 0 2 4 6 8
Time (s)

Figure 6-2. Common-Mode Transient Response

6.3.3 Thermal Response

The SOIC-7 package is designed to maximize the heat flow and minimize the thermal response time from the
TSENSE pins to the temperature sensor, while also providing the 3kVRMS isolation rating (UL1577).
When evaluating thermal response with a thermal contact device, care must be taken to understand the
gradient that is established by the heat source in the application. Traditionally, most temperature sensors are
characterized on the basis of a "stirred-liquid" thermal response test, which sees the totality of the device
submerged into a circulated oil bath at an elevated temperature, which typically provides the best possible
response the device yields, having all parts of the device held to the secondary temperature for the purposes of
establishing a new thermal equilibrium point. This style of test is visualized in Stirred Liquid Thermal Response
Test, and the results of this test are presented in Thermal Response (Air-to-Fluid Bath).

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T = Ta = 25°C
outside of bath

T = TTEST
Heat sourced from
ISOTMP35-Q1 all directions through
liquid submersion

Figure 6-3. Stirred Liquid Thermal Response Test

ISOTMP35-Q1 is also evaluated by means of a "directional" temperature response test, where only the thermally
connected, high-voltage pins of the device are exposed to the elevated temperature, while the remaining low
voltage pins remain in free air at a standard room temperature condition of 25°C. The objective of this form of
thermal response test is to more properly evaluate the thermal conductivity of the device under test, even though
slight error can persist from the reference temperature.

T = Ta = 25°C
Additional thermal gradient from
lower temperature side

ISOTMP35-Q1

T = TTEST
Heat sourced through
2oz. Copper plane

Figure 6-4. Directional Thermal Response Test

This is demonstrated in Figure 6-5, where ISOTMP35-Q1 is shown alongside a standard negative temperature
coefficient (NTC) thermistor, as well as the same NTC adhered via non-conductive thermal epoxy to the high
voltage copper, placed at clearance distance of 4mm from the temperature source. The resulting responses
demonstrate both the superior response time, as well as the accuracy of the ISOTMP35-Q1 device. The
reference temperature in this test is 75°C.

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80
76
72
68
64
Temperature (°C) 60
56
52
48
44
40
36
32
28 NTC without Epoxy
24 NTC with Epoxy
ISOTMP35B
20
0 20 40 60 80 100 120 140 160 180 200
Time (s)

Figure 6-5. ISOTMP35-Q1 Directional Thermal Response

6.4 Device Functional Modes

The singular functional mode of the ISOTMP35-Q1 is an analog output directly proportional to temperature.
7 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

7.1 Application Information

The features of the ISOTMP35-Q1 make the device versatile for various high voltage temperature-sensing
applications. The ISOTMP35-Q1 can operated down to a 2.3V supply with 9µA current consumption. As a result,
the device is also well designed for battery applications where a number of these batteries can be stacked for
high voltage output.
7.1.1 Output Voltage Linearity
As illustrated in Figure 5-2, the ISOTMP35-Q1 device exhibit a linear output of 10mV/°C. For temperature above
100°C, a small gain shift (TC) is present on the output (VOUT). When small shifts are expected, a piecewise linear
function provides the best accuracy and is used for the device accuracy specifications. Table 7-2 lists the typical
output voltages of the ISOTMP35-Q1 device across the full operating temperature range. The calculated linear
column represents the ideal linear VOUT output response with respect to temperature, while the piecewise linear
columns indicate the small voltage shift at elevated temperatures.
The piecewise linear function uses three temperature ranges listed in Table 7-1. Use Equation 1 to calculate the
voltage output VOUT of the ISOTMP35-Q1:

VOUT = (TA - TINFL) ✕ TC + VOFFS (1)

where

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• VOUT is the voltage output for a given temperature

• TA is the ambient temperature in°C
• TINFL is the temperature inflection point for a piecewise segment in°C
• TC is the temperature coefficient or gain
• VOFFS is the voltage offset
Use Table 7-2 to calculate the ambient temperature (TA) for a given VOUT voltage output within a piecewise
voltage range (VRANGE). For applications where the accuracy enhancement above 100°C is not required, use the
first row of Table 7-1 for all voltages.

TA = (VOUT - VOFFS) ÷ TC + TINFL (2)

Table 7-1. Piecewise Linear Function Summary
TA RANGE (°C) VRANGE (mV) TINFL (°C) TC (mV/°C) VOFFS (mV)
–40 to 100 < 1500 0 10 500
+100 to 125 1500 to 1752.5 100 10.1 1500
125 to 150 > 1752.5 125 10.6 1752.5

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Table 7-2. Transfer Table

TEMPERATURE (°C) VOUT (mV) CALCULATED VOUT (mV) PIECEWISE LINEAR
LINEAR VALUES VALUES
–40 100 100
–35 150 150
–30 200 200
–25 250 250
–20 300 300
–15 350 350
–10 400 400
–5 450 450
0 500 500
5 550 550
10 600 600
15 650 650
20 700 700
25 750 750
30 800 800
35 850 850
40 900 900
45 950 950
50 1000 1000
55 1050 1050
60 1100 1100
65 1150 1150
70 1200 1200
75 1250 1250
80 1300 1300
85 1350 1350
90 1400 1400
95 1450 1450
100 1500 1500
105 1550 1550.5
110 1600 1601
115 1650 1651.5
120 1700 1702
125 1750 1752.5
130 1800 1805/5
135 1850 1858/5
140 1900 1911.5
145 1950 1964.5
150 2000 2017.5

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7.1.2 Load Regulation

Load regulation is how the analog output voltage of the ISOTMP35-Q1 changes as the output load current
changes, and is measured across temperature. Load regulation is important because when implementing the
ISOTMP35-Q1 with an ADC, the user can use an RC filter on the analog output. Knowing how the output voltage
changes based on the current pulled with different resistive and capacitive loads help the user make accurate
temperature measurements with the ISOTMP35-Q1. See Figure 5-5 for more details on Load Regulation and
Section 7.1.6 for more details on how to use the ISOTMP35-Q1 with an ADC.
7.1.3 Start-Up Settling Time
The ISOTMP35-Q1 can support either a step input power supply or a ramp power supply. When powering
the device, consider the analog output settling time upon start-up. For a step VDD input, start-up time is
approximately 1ms.
The ISOTMP35-Q1 can support either a step input power supply or a ramp power supply. When powering the
ISOTMP35-Q1, the user must keep in mind that the ISOTMP35-Q1 requires time to settle the analog output
upon start-up:
• For a step VDD input, start-up time is approximately 1ms.
• For a ramp VDD input with a ramp rate of 5V/ms, start-up time is approximately 1.25ms.
See Figure 5-8 and Figure 5-9 for more information.
7.1.4 Thermal Response
The 7-pin SOIC package is designed to maximize the heat flow, and minimize the thermal response time, from
the TSENSE pins to the temperature sensor while also providing the 3 kVRMS isolation rating (UL1577).
7.1.5 External Buffer
In case of higher capacitance on the output or a long trace between the sensor and the ADC, a external buffer
can be added. This implementation is shown in Figure 7-1 for the signal to be temperature voltage to be sent
through a differential pair.
ISOTMP35
25

VOUT +
50
25
THP210

Figure 7-1. Buffering Prior to Sending Data Through a Differential Pair

7.1.6 ADC Selection and Impact on Accuracy

When connecting the ISOTMP35-Q1 analog output to an ADC,using an RC filter on the output is important. Most
ADCs have a sampled comparator input structure. When the sampling is active, a switch internal to the ADC
charges an internal capacitor (CSAMPLE). The capacitor requires instantaneous charge from the analog output
source (ISOTMP35-Q1), so this lead to voltage drops on the ISOTMP35-Q1 analog output, which appears as
incorrect temperature reads. By placing a filter capacitor (CFILTER) load on the ISOTMP35 analog output, the
voltage drops are mitigated. This works because CFILTER stores charge from the analog output that the ADC can

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pull from when sampling, so there is no voltage drop on the ISOTMP35-Q1 output. Users can also add RFILTER
to filter out noise on the analog output.
Consider the maximum load capacitance. The ISOTMP35-Q1 has a maximum load capacitance of 1000pF,
therefore the total capacitance on the analog output, including those in the ADC input, must not exceed 1000pF.
When choosing the R and C filter values, the RC time constant changes the settling time of the ISOTMP35-Q1.
ADCs often have customizable sampling rates, so the settling time of the ISOTMP35-Q1 must be less than the
selected sampling time of the ADC. For example, an ADC with a data rate (DR) of 1ksps has a conversion time
of 1ms, therefore any selected R and C filter values must be completely settled within 1ms (5 × R × C < 1/DR).
ADCs often have customizable full scale ranges (FSR), either digitally or through reference voltages. The
ISOTMP35-Q1 at 150°C outputs a maximum voltage of 2017.5mV. When choosing an ADC, there must be a full
scale range option with at least that much range. TI recommends a FSR option of at least 3V to avoid headroom
concerns in this example. To determine the desired ADC resolution, the ADC LSB size must be known. For the
ISOTMP35-Q1, the device does not have an LSB but rather the LSB of the ADC determines the measurement
resolution.
• For example, a 12bit ADC with an FSR of 3.3V, has an LSB size of 806µV. This translates to 80m°C of
temperature resolution. A 16bit ADC with an FSR of 3.3V, has an LSB size of 50µV, which gives 5m°C of
temperature resolution. A 12bit ADC is sufficient for most applications.
• The analog output voltage from the ISOTMP35-Q1 must not exceed the VDD being supplied to the ADC.
Selecting a VDD for the ADC that exceeds the chosen FSR required to fully capture the ISOTMP35-Q1 analog
output range is necessary.
Table 7-3. ADC Settling Times and Cutoff Frequencies
SETTLING TIME SETTLING TIME (5×RC TIME CONSTANT) CUTOFF FREQUENCY (fC = 1/(2πRC))
(µs) & CUTOFF
FREQUENCY 100pF 680pF 1000pF 100pF 680pF 1000pF
(KHz)
1kΩ 0.5µs 3.4µs 5µs 1592kHz 234.2kHz 159.2kHz
4.7kΩ 2.35µs 15.98µs 23.5µs 338.8kHz 49.8kHz 33.88kHz
10kΩ 5µs 34µs 50µs 159.2kHz 23.42kHz 15.92kHz
100kΩ 50µs 340µs 500µs 15.92kHz 2.34kHz 1.592kHz

7.1.7 Implementation Guidelines

Voltage clearance on the line must be respected.
A minimum of two layers is required for the ISOTMP35-Q1. Standard layer stacking can be used for a 4-layer
PCB where the signal traces can run either on the top or bottom layer. Solid ground and power plane must form
the inner layer. See PCB Cross-Section for a depiction of plane and trace clearance under the device.

Keep this space free

10 mils from planes, traces,
pads and vias

Figure 7-2. PCB Cross-Section

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7.1.8 PSRR
Depending on the application, there can be a significant amount of high frequency noise on the power supply
line. If high frequency noise (>100kHz) is present, the user can switch to a 1μF bypass capacitor to provide
additional filtering on the power supply line. Increasing the bypass capacitance or choosing a capacitor with a
lower ESR across frequency improves PSRR performance.
An additional power supply consideration is line regulation. For the ISOTMP35-Q1, line regulation refers to the
change in output temperature with changing power supply. Figure 5-6 shows that, across the entire environment
temperature range, ISOTMP35-Q1 maintains a steady amount change in temperature across VDD.
7.2 Typical Application

ISOTMP35-Q1
5 TSENSE VOUT 4 VOUT

ISOLATION BARRIER
High GND 3
Voltage 6 TSENSE
Heat GND
NC 2
Source

7 TSENSE VDD 1 VDD

0.1µF
GND
Figure 7-3. Typical ISOTMP35-Q1 Circuit

7.2.1 Design Requirements

To design with ISOTMP35-Q1, use the parameters listed in Table 7-4. Most CMOS-based ADCs have a
sampled data comparator input structure. When the ADC charges the sampling capacitor, the capacitor requires
instantaneous charge from the output of the analog temperature sensor, such as the ISOTMP35-Q1. Therefore,
the output impedance of the temperature sensor can affect ADC performance. In most cases, adding an
external capacitor mitigates design challenges. The ISOTMP35-Q1 is specified and characterized with a 1000pF
maximum capacitive load (CLOAD). The CLOAD is a sum of the CFILTER, CMUX and CSAMPLE. TI recommends
maximizing the CFILTER value while allowing for the maximum specified ADC input capacitance (CMUX +
CSAMPLE) to limit the total CLOAD at 1000pF. In most cases, a 680pF CFILTER provides a reasonable allowance for
ADC input capacitance to minimize ADC sampling error and reduce noise coupling. An optional series resistor
(RFILTER) and CFILTER provides additional low-pass filtering to reject system level noise. TI recommends placing
RFILTER and CFILTER as close to the ADC input as possible for optimal performance.
Table 7-4. Design Parameters
PARAMETER VALUE
Supply voltage, VDD 2.3V to 5.5V
Decoupling capacitor between VDD and GND 0.1µF

7.2.2 Detailed Design Procedure

Depending on the input characteristics of the ADC, an external CFILTER can be required. The value of CFILTER
depends on the size of the sampling capacitor (CSAMPLE) and the sampling frequency while observing a
maximum CLOAD of 1000pF. The capacitor requirements can vary because the input stages of all ADCs are
not identical.

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7.2.2.1 Insulation Lifetime

Insulation lifetime projection data is collected by using industry-standard Time Dependent Dielectric Breakdown
(TDDB) test method. In this test, all pins on each side of the barrier are tied together creating a two-terminal
device and high voltage applied between the two sides; See Figure 7-4 for TDDB test setup. The insulation
breakdown data is collected at various high voltages switching at 60Hz over temperature.

VOUT

Time Counter
> 1mA
DUT

VDD

VS

Oven at 150°C
Figure 7-4. Test Setup for Insulation Lifetime Measurement

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7.3 Power Supply Recommendations

To help provide reliable operation at supply voltages, a 0.1µF bypass capacitor is recommended at the VDD
supply pin. Place the capacitor as close to the supply pin as possible. Because there is only a single side power
supply for the ISOTMP35-Q1, there is no need to generate isolated power.
7.4 Layout
7.4.1 Layout Guidelines
A minimum of two layers is required for the ISOTMP35-Q1. For a 4-layer PCB, TI recommends a standard layer
stacking method where the signal traces run either on the top of bottom layer. Solid ground and power plane
must form the inner layer.
7.4.2 Layout Example
Keep space beneath
device free of any
planes, traces, pads and
vias

To VDD Plane

Bypass 1 VDD TSENSE 7

Capacitor Heat
2 NC
To GND Plane TSENSE 6 High Voltage Heat Source
3 GND
Heat
4 VOUT TSENSE 5

Filter Capacitor Load Capacitor

Filter Resistor
To ADC Input

Figure 7-5. Layout Example

Keep this space free

10 mils from planes, traces,
pads and vias

Figure 7-6. Layout Example - PCB Cross-Section

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8 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
8.1 Documentation Support

8.1.1 Related Documentation

For related documentation, see the following:
• Texas Instruments, ISOTMP35 Evaluation Module User's Guide
• Texas Instruments, Circuit for driving an ADC with an instrumentation amplifier in high gain, circuit design
• Texas Instruments, Driving a SAR ADC directly without a front-end buffer circuit (low-power, low-sampling-
speed DAQ), circuit design
8.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
8.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
8.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
8.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

8.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

9 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision * (October 2023) to Revision A (June 2024) Page

• Updated the number format for tables, figures, and cross-references throughout the document...................... 1
• Changed the status of this data sheet to Production Data................................................................................. 1

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 23

Product Folder Links: ISOTMP35-Q1
 PACKAGE OPTION ADDENDUM

www.ti.com 23-May-2025

PACKAGING INFORMATION

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

ISOTMP35BEDFQRQ1 Active Production SOIC (DFQ) | 7 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 150 T3Q
ISOTMP35BEDFQRQ1.A Active Production SOIC (DFQ) | 7 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 150 T3Q
ISOTMP35BEDFQRQ1.B Active Production SOIC (DFQ) | 7 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 150 T3Q

(1)
Status: For more details on status, see our product life cycle.

(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.

(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers
and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF ISOTMP35-Q1 :

• Catalog : ISOTMP35

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 23-May-2025

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 14-Oct-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ISOTMP35BEDFQRQ1 SOIC DFQ 7 3000 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 14-Oct-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ISOTMP35BEDFQRQ1 SOIC DFQ 7 3000 353.0 353.0 32.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DFQ0007A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP .075
[5.80-6.19] [1.91] .004 [0.1] C
PIN 1 ID AREA A
3X .050
[1.27]
1 7

2X .189-.197
.150 [4.81-5.00]
[3.81] NOTE 3

4X (0 -15 )

5
4

6X .012-.020 .150-.157 B .081-.089 .069 MAX

[0.31-0.50] [3.81-3.98] [2.07-2.27] [1.75]
NOTE 4
.010 [0.25] C A B

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4229018/A 10/2022

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. No JEDEC Registration as of September 2022

www.ti.com
 EXAMPLE BOARD LAYOUT
DFQ0007A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

7X (.061 ) SYMM SEE

[1.55] DETAILS

1 7

6X (.024)
[0.6]

SYMM (.093 )
[2.36]

5
4
3X (.050 )
[1.27] (.213) R.002 TYP
[5.4] [0.05]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:12X

METAL SOLDER MASK SOLDER MASK METAL UNDER

OPENING OPENING SOLDER MASK

EXPOSED EXPOSED
METAL METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4229018/A 10/2022

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DFQ0007A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

7X (.061 ) SYMM
[1.55]
1
7

6X (.024)
[0.6]

SYMM (.093 )
[2.36]

5
4
3X (.050 )
[1.27] (R.002 ) TYP
(.213) [0.05]
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:12X

4229018/A 10/2022

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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