Physical Design Q/A

Q1. What are the inputs required for any physical design tool and the outputs generated
from the same?
Inputs for Physical Design :
1. Gate level netlist (.v)
2. Timing, Logical & Power libraries (.lib or .db)
3. Physical library (.lef)
4. Technology file (.tf)
5. TLU + file (.TLUP)
6. Synopsys Design constraints (.sdc)
7. Power specification file (.upf or .cpf)
Outputs for Physical Design :
1. Parasitic format (.spef) : Resistance and Capacitance info of cells and nets.
2. Post routed Netlist (.v) : Can be of flattened or hierarchical , Contains
connectivity info of all cells.
3. Physical Layout (.gds) : Physical Layout info.
4. Design Exchange format (.def) : Contains, row, cell, net placement locations
etc.,.
5. Standard delay format (.sdf) : Timing Details (Except load info)

Q2. What you know about sanity checks?

▪ Sanity Checks mainly checks the quality of netlist in terms of timing
▪ It also consists of checking the issues related to Library files, Timing
Constraints, IOs and Optimization Directives
▪ Some of the Netlist Sanity Checks:

▪ Floating Pins
▪ Unconstrained Pins
▪ Un-driven i/p Ports
▪ Unloaded o/p Ports
▪ Pin direction mismatches
▪ Multiple drivers etc.

Other possible issues include Unconnected/ Wrongly Connected Tie-high/ Tie-low

Pins and Power Pins (since Tie-up or Tie-down connectivity always through Tie-
Cells)

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Q3. What we need to start Floor plan?
To start a floor plan first we need inputs like. v, .lib, .lef, .SDC This is the first major
step in getting your layout done. Your floor plan determines your chip quality. At this step, you
define the size of your chip/block, allocates power routing resources, place the hard macros,
and reserve space for standard cells.

Q4. Styles of PD Implementation?

Flat
▪ Small to Medium ASIC
▪ Better Area Usage Since no reserve space around each sub-design for
power/ground
Hierarchical
▪ For very large design
▪ When sub-systems are design individually
▪ Possible only if a design hierarchy exist

Q5. What are the guidelines to place macros?

▪ Placement of macros are the based on the fly-lines ( its shows the connectivity
b/w macro to macro and macro to pins) so we can minimize the interconnect length
between IO pins and other cells.
▪ Place the macros around to the boundary of the core, leaving some space
between macro to core edge so that during optimization this space will be used for
buffer/inverter insertion and keeping large areas for placement of standard cells during
the placement stage.
▪ Macros that are communicating with pins/ports of core place them near to core
boundary.
▪ Place the macros of same hierarchy together.
▪ Keep the sufficient channel between macros. channel width = (number of pins
* pitch )/ number of layers either horizontal or vertical
▪ Avoids notches while placing macros, if anywhere notches is present then use
hard blockages in that area.
▪ Keep keep-out margin around the four sides of macros so no standard cells will
not sit near to Macro pins. This technique avoids the congestion.
▪ Keep placement blockages at the corners of macros.
▪ For pin side of macros keep larger separation and for non-pin side, we can abut
the macros with their halo so that area will be saved and Halo of two macros can abut
so that no standard cells are placed in between macros.
▪ Between two macros at least one pair of power straps (power and Ground)
should be present.
▪ Lots of iterations happen to get optimum floorplan, the designer takes care of
the design parameter such as power, area, timing and performance during
floorplanning.

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Q6. what happens if pins assign to left and right. (if you have IO pins at top and bottom)?
Actually top level chip will be divided into some blocks, IO pins will be placed
according to the communication between surrounding blocks. If we assign pins to left and right
rather than top and bottom we will face routing issues in further stages.

Q7. How we will assign spacing between two macros?

channel spacing= no of pins*pitch/ (total number of metal layers/2)

Q8. If we do macro abutment, what happens?

There are two cases
1. If two macros communicating only with each other we can abutment the macros
2. If the macros communicating with other cells (std cells and IO ports) then we
must should provide a proper channel spacing between the macros or else, we can see
the routing issue.

Q9. Can we place macros 90 and 270 dergees orientation?

It depends on which technology you are working on. 45nm & below there are
orientation requirements by foundry. Poly orientation should be same throughout the chip. So
Macro poly orientation should match with the poly orientation of the standard cells.

Q10. In power planning for rings and stripes which metal layers used and why?
For rings and stripes we use top metal layers because for top metal layers we have
low resistivity.

Q11. Can we place cells between the space of IO and core boundary?
No, we cannot place cells between the space of IO and core boundary because in
between IO and core boundary power rings will be placed and we may see routing issues.

Q12. What type of congestion you've seen after placement?

1. Congestion near Macro corners due to insufficient placement blockage.
2. Standard cell placement in narrow channels led to congestion.
3. Macros of same partition which are placed far apart can cause timing violation.
4. Macro placement or macro channels is not proper.
5. Placement blockages not given.
6. No Macro to Macro channel space given.
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 7. High cell density.
8. High local utilization.
9. High number of complex cells like AOI/OAI cells which has more pin count
are placed together.
10. Placement of std cells near macros.
11. Logic optimization is not properly done.
12. Pin density is more on edge of block.
13. Buffers added too many while optimization.
14. IO ports are crisscrossed; it needs to be properly aligned in order.

Q13. what are the physical cells?

End Cap cells:
1. These cells prevent the cell damage during fabrication.
2. Used for row connectivity and specifying row ending.
3. To avoid drain and source short.
4. These are used to address boundary N-Well issues for DRC cleanup.
Well Tap cells:
1. These are used to connect VDD and GND to substrate and N-Well respectively
because it results in lesser drift to prevent latch-up.
2. If we keep well taps according to the specified distances, N-Well potential leads
to proper electrical functioning.
3. To limit the resistance between power and ground connections to wells of the
substrate.
De-cap Cells:
1. They are temporary capacitors which are added in the design between power
and ground rails to counter the functional failure due to dynamic IR drop.
2. To avoid the flop which is far from the power source going into metastable state.
Filler Cells:
1. To fill the empty space and provide connectivity of N-wells and implant layers.

Q14. Tell about Non Default Rules?

Double width and double space.
After PNR stage if u will get timing /crosstalk/noise violations which are difficult to fix at
ECO stage we can try this NDR option at routing stage.

USAGE OF NDRs and Example:

When we are routing special nets like clock we would like to provide more width and more
spacing for them. Instead of default of 1 unit spacing and 1 unit width specified in tech file;
But NDR having double spacing and double width. When clock net is routed using NDR it
has better Signal integrity, lesser cross talk, lesser noise, but we cannot increase the spacing
and width because it effects the area of the chip.
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Double spacing: It is used to avoid the cross talk.
Double width: It is used to avoid the EM.

Q15. What is setup and hold?

SETUP: Minimum time required for data stability before the clock edge.
HOLD: Minimum time required for data stability after the clock edge.

Q16. Can we do setup check at placement?

Yes, we will check setup in placement stage, where as we won’t bother about hold because
clock is ideal in placement stage.

Q17. What are all the fixing methods for setup and hold violations?
A. Setup:

1. Upsizing the cells

2. Replace buffer with two inverters
3. HVT to LVT
4. If the net delay is more than the cell delay, break the net and insert the buffer
5. Pin swapping
6. Pulling the launch and pushing the capture
7. Cloning

B. Hold:
1. Inserting the buffers
2. Downsizing the cells
3. LVT to HVT
4. Pushing the launch and pulling the capture

Q18. How do you know you have max cap violation?

report_timing - all_violations

Q19. How Do You Reduce Power Dissipation Using High Vt and Low Vt On Your
Design?
▪ Use HVT cells for timing paths having +ve slacks.
▪ Use LVT cells for timing paths having -ve slacks.

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 ▪ HVT cells have a larger delay but less leakage. +ve slack in a design is not
useful as having only some paths working faster will not help overall design. We are
good if the slack is 0. In such cases give up the slack by using HVT cells but gain on
power dissipation.
▪ LVT cells are very fast but very leaky. Limit the use of LVT cells to only those
paths that have difficulty in closing time.
Q20. What Is Electromigration and How to Fix It?
Electromigration (EM) refer to the phenomenon of movement of metal atoms due to
momentum transfer from conducting electrons to metal atoms. Current conduction over a
period of time in a metal route causes opens or shorts due to EM effect. EM effect cannot be
avoided. In order to minimize its effect, we use wider wires so that even with EM effect wire
stays wide enough to conduct over the lifetime of the IC.

Q21. What Is the Importance of IR Drop Analysis?

IR drop determines the level of voltage at the pins of standard cells. Value of acceptable
IR drop will be decided at the start of the project and it is one of the factors used to determine
the derate value. If the value of IR drop is more than the acceptable value, it calls to change the
derate value. Without this change, timing calculation becomes optimistic.

Q22. If You Have Both IR Drop and Congestion How Will You Fix It?
1. Spread macros
2. Spread standard cells
3. Increase strap width
4. Increase number of straps
5. Use proper blockage

Q23. In A Reg to Reg Path If You Have Setup Problem Where Will You Insert Buffer-
near to Launching Flop or Capture Flop? Why?
▪ Near to capture path.
▪ Because there may be other paths passing through or originating from the flop
nearer to launch flop. Hence buffer insertion may affect other paths also. It may
improve all those paths or degrade. If all those paths have violation, then you may insert
buffer nearer to launch flop provided it improves slack.

Q24. Why Buffers Are Used in Clock Tree?

To balance skew (i.e. flop to flop delay)

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Q25. What Is Cross Talk?
Switching of the signal in one net can interfere neighboring net due to cross coupling
capacitance. This affect is known as cross talk. Cross talk may lead setup or hold violation.

Q26. How Can You Avoid Cross Talk?

▪ Double spacing → more spacing → less capacitance → less cross talk
▪ Multiple vias → less resistance → less RC delay
▪ Shielding → constant cross coupling capacitance → known value of crosstalk
▪ Buffer insertion → boost the victim strength.

Q27. How Shielding Avoids Crosstalk Problem? What Exactly Happens There?
▪ High frequency noise (or glitch) is coupled to VSS (or VDD) since shielded
layers are connected to either VDD or VSS.
▪ Coupling capacitance remains constant with VDD or VSS.

Q28. How Spacing Helps in Reducing Crosstalk Noise?

width is more → more spacing between two conductors → cross coupling capacitance is less
→ less cross talk.

Q29. How Buffer Can Be Used in Victim to Avoid Crosstalk?

Buffer increase victims signal strength; buffers break the net length → victims are more
tolerant to coupled signal from aggressor.

Q30. Why Setup is checked at max corner and Hold at min corner?
For setup, the required time should be more than the arrival time. And setup violates when
arrival time is more. So, setup check is more pessimistic when arrival time is more or when the
launch clock reaches late than the capture clock. That means delay is more. So, setup will be
checked at max delays.

For hold, the arrival time should be more than the required time. And hold violates when
required time is more. So, hold check is more pessimistic when required time is more or when
the launch clock reaches early than the capture clock. That means data arrival time is less. So,
hold will be checked at min delays.

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Q31. Why we are not checking the hold before CTS?
Before CTS, clock is ideal that means exact skew is not there. All the clocks reaching the flops
at the same time. So, we don’t have skew and transition numbers of the clock path, but this
information is sufficient to perform setup analysis since setup violations depends on the data
path delay. Clock is propagated only after CTS (actual clock tree is built, clock buffers are
added & clock tree hierarchy, clock skew, insertion delay comes into picture) and that's why
hold violations are fixed only after CTS.

Q32. Can both Setup and Hold violations occur in same start and end points?
Yes, if they have different combo paths

Q33. What is the derate value that can be used?

▪ For setup check derate data path by 8% to 15%, no derate in the clock path.
▪ For hold check derate clock path by 8% to 15%, no derate in the data path.

Q34. What are the corners you check for timing sign-off? Is there any changes in the
derate value for each corner?
▪ Corners: Worst, Best, Typical.
▪ Same derating value for best and worst. For typical it can be less.

Q35. Where do you get the WLM's? Do you create WLM's? How do you specify?
▪ Wire Load Models (WLM) are available from the library vendors.
▪ We dont create WLM.
▪ WLMs can be specified depending on the area.

Q36.Where do you get the derating value? What are the factors that decide the derating
factor?
▪ Based on the guidelines and suggestions from the library vendor and previous
design experience derating value is decided.
▪ PVT variation is the factor that decides the derating factor.

Q37. Setup Fixes during placement and Setup and hold fixes during CTS?
SETUP FIXES

During Placement Stage:

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 1. Timing path groups
2. Create Bounds
3. If the design is having timing violation, we can rerun place_opt with the -timing
and -effort high options.
4. Change the Floorplan (macros placement, macros spacing and pin orientation)
to meet the better timing.

Q38. Why don’t you derate the clock path by -10% for worst corner analysis?
We can do. But it may not be accurate as the data path derate.

Q39. What are the importance and need of an MMMC file in VLSI physical design?
▪ Multi-Mode Multi corner (MMMC) file during the physical design gives the
analysis of the design over varied modes & corners.
▪ VLSI design can be modeled in either functional or test mode etc., with each
mode at varied process corners.
▪ We need to ensure that the design is stable across all corners, to be specific in
Tech terms PVT Corners (Process, Voltage & Temperature).
▪ During the process flow of physical design, (prescribed Tool-Cadence,
synopsys etc.) MMMC file takes all relevant details for obtaining the desired
design.

Q40. What are Timing DRV/'s, explain the Causes and its fixes?
Timing Drvs :
▪ Max Tran
▪ Max Cap
▪ Max Fanout
Causes:
1. HVT cells give slower transition: The HVT cells have larger threshold
voltages compared to LVTs and RVTs. Hence, they take more time to turn ON resulting
in larger transition time.
2. Weak Driver: The driver won’t be able to drive the load resulting in bad
transition of the driven cell. Thus the delay increases.
3. Load is more: The driving cell cannot drive load more that what it is
characterized for. This is set in .lib using max cap value. If the load that a cell sees
increases beyond its maximum capacitance value, then it causes bad transition and
hence increases delay.
4. Net length is large: Larger the net length, larger the resistance, worser the
transition. Thus results in trans violation. The RC Value of a long net will increase the
load seen by a cell causing max cap violations as well.

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 5. Fanout is too large: If the fanout number increases beyond the limit of what
the driver cell in characterized for, it causes max fanout violations. The increased load
results in max cap violation which indirectly causes max tran violation as well.
Fixes:
Max Tran:
▪ Replace HVT cells with LVT cells.
▪ Up size the driver.
▪ Reduce the net length by adding buffers. Longer the nets, larger the
resistance. Puting a buffer at the middle of a long net splits the resistance into
half.
Max Cap:
▪ Up size the driver.
▪ Split long nets by buffering.
▪ Reduce the load by reducing the fanout (by load spliting)
Max Fanout:
▪ Reduce the fanout by load spliting by buffering or cloning.

Q41. Why do we emphasize on setup violation before CTS and hold violation after CTS?

Q42. What should we do if there is a setup violation after placements even though we
completed the optimization?
Setup violation after placement is nothing but it comes from a really bad placement of modules.
We need to check whether at the macro placement and the module placement and see if
something looks bad. For example, if there’s a module, it's getting split and placed in two or
three different clusters then we may want to attack this with module placement guides or
bounds. Let the tool have the right constraints at place stage, and maybe give another round
with timing effort flag marked as medium or high.

Q43. What is meant by insertion delay in VLSI physical design?

▪ The insertion delay concept comes into picture in clock tree synthesis.
▪ While building the clock tree, cts starts building the clock from the clock source
to the sinks.
▪ Once The clock was build and now the clock signal has to travel from the source
to the sinks. The amount of time taken by the clock signal to travel from source to sinks
is called the insertion delay.

Q44. Why don't we do routing before CTS in VLSI Physical Design?

▪ Routing should be done once your design is at a stage where all of your data
and clock logical nets are balanced and synthesized properly. Laying down the actual
metal routing requires all of the design objects (cells) to be placed at legal sites. Post

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 placement stage is when we reach to that. But it doesn't mean that your design is ready
for routing, you should consider other high fanout nets and clock network signals post
placement. Till this stage clocks are ideal networks (assuming can drive any number of
loads without any buffering).
▪ During logic synthesis we do not balance HFN and Clock nets, so a single clock
port might be driving thousands of flops (with a vIRtual route even after placement).
CTS is the stage where this kind of loading is synthesized into a balanced tree to arrive
with a min skew and latency for all sinks (flops).
▪ Until you finish logical synthesis of clocks, you are not allowed to route
anything. As soon as you finish up with CTS, you can start routing the design clocks
first followed by data signals. Let me know if any clarifications are required.

Q45. What is a path group in VLSI, and why is it done?

▪ The reason why paths are grouped is to guide the efforts of the synthesis engine.
▪ In this case the synthesis engine will spend most of its time on optimizing the
logic of the worst case violators. and once it meets timing will move on to the next
worst case violator and so on.
▪ Now looking at the initial timing report you might have identified
▪ Low violation Paths that did not get optimized because all effort was spent on
high violation paths. Make separate path groups of these two sets.

Q46. What is the benefit of having separate path groups for I/O logic paths in VLSI?

Q47. While fixing timing, how do I find a false path in VLSI design?
It refers to a timing path which is not required to be optimized for timing as it will never be
required to get captured in a limited time when excited in normal working situation of the chip.
In normal scenario, the signal launched from a flip-flop has to get captured at another flip-flop
in only one clock cycle. However, there are certain scenarios where it does not matter at what
time the signal originating from the transmitting flop arrives at the receiving flop. The timing
path resulting in such scenarios is labeled as false path and is not optimized for timing by the
optimization tool.

Q48. What makes meeting timing on clock gating paths very challenging? What makes it
more critical than a regular setup/hold flop to flop timing path?
▪ While building clock tree, we try to balance all the flops. This makes the clock
gate (CG) driving bunch of flops early in clock tree by delay of the CG itself. This
makes the available time to meet setup for clock gating latch clock period minus delay,
and hence making it tighter to meet.
▪ Now if the fanout of cg is more than it's driving capability than a small bigger
tree (or may be 2 parallel buffers) will come, making arrival of Clock at CG even early
and hence making meeting setup more difficult.

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Q49. What is the difference between a static IR drop and a dynamic IR drop analysis?
Static IR drop is the voltage drop, when a constant current draws through the power network
with varying resistance. this IR drop occurs when the circuit is in steady state. Dynamic IR
drop is the drop when the high current draws the power network due to the high switching of
the cell data. Due reduce static, you should increase width of the power network, or a robust
power grid has to be designed, where as to reduce Dynamic IR drop, reduce the toggle rate or
place decap cells near high switching cells

Q50. What is the need of Static IR drop analysis?

IR drop is the voltage drop in metal wires from the power grid before it reaches the VDD pins
of standard cells. Due to the IR drop, there can be timing issues due to the change in VDD
value.

Q51. What is GDSII file?

▪ GDS (Graphic Data Stream) is a file that was developed by calma company in
the year 1971 and the GDS II in the year 1978.
▪ It is a binary file format that represents layout data in a hierarchical format.
▪ Data such as labels, shapes, layer information and other 2D and 3D layout
geometric data.
▪ This file is then provided to the fabrication plant that uses this file to etch the
chip based on the parameters provided in the file.

Q52. What is a SDF file related to VLSI Physical Design?

▪ SDF stands for Standard delay format.
▪ It gives information on the timing data extensively used in backend VLSI design
flows.
▪ SDF gives information about
1. Path delays
2. Interconnect delays
3. Timing constraints
4. Tech parameters affecting delays
5. Cell delays.

Q53. What is DEF file in VLSI?

▪ The Design Exchange File, is an industry standard file that is used for
representing logic and connectivity of an IC in ASCII format.
▪ It generally defines die size, connectivity, pin placement and power domain
information.

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Q54. Explain the types of metal programmable ECO cells?
▪ There are 2 types of programmable ECO cells, one is ECO filler and other is
functional ECO cells. The ECO filler cells are constructed based upon the base layers
known as Front-end-of-line(FOEL), FEOL are implant, diffusion, and poly layers. This
allows any functional ECO to be performed using back-end-of-line layers.
▪ Functional programmable ECO cells include a wide variety of combinational
and sequential cells with multiple drive strengths realized by using width multiples for
filler cells. Their cell has the same FEOL footprint as that of ECO filler cells.
▪ The only difference is that the functional ECO will use ECO filler FEOL layout
and have contact connections to poly-layers and diffusion and metal1 layers for internal
connections in order to construct a functional gate.

Q55. What is +ve unateness, -ve unateness & non-unate?

▪ +ve Unateness: A timing arc is said by +ve unate, if output signal direction is
same as the input signal direction. Examples : AND, OR

▪ -ve Unateness: A timing arc is said to be -ve unate, if output signal direction is
opposite to that of input signal direction. Examples: NOR, NAND, INV.

▪ Non-Unate: In a non-unate timing arc, the output transition cannot be depends

on the direction of change of an input but also depends upon the state of the other inputs.
Example: XOR

Q56. Can we get 0 skew what is the problem?

If skew is 0, then all the flops will trigger at the same time. So power consumption will be
more.

Q57. What's the impact on the timing if you insert inverter on the capture clock pin?
▪ Before inserting inverter, they have full clock cycle available for Setup.
▪ After inserting inverter, it becomes half-cycle path for setup timing calculation
and hence setup timing will be so critical.
▪ But we don’t see any hold timing issue as capture clock comes earlier by half
clock period (i.e. at -ve edge) and launch clock comes after that (i.e.at +ve clock edge).
Hold path will extra half cycle & hence it becomes less critical.
Q58. Difference between clock skew and clock latency?
Clock skew between two flip-flops represents the difference in arrival times of clock
signal at the respective clock pins. If there is a timing path being formed between the two flip-
flops, then we can attribute a sign to the clock skew. In that case, clock skew is given as:
Clock skew = (Arrival time at capture clock pin) - (Arrival time at launch clock pin)
Thus, based upon the sign of clock skew, we get two types of clock skew labelled as positive
skew and negative skew.

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 Clock latency (or clock insertion delay) is defined as the amount of time taken by the
clock signal in traveling from its source to the sinks. Clock latency comprises of two
components - clock source latency and clock network latency.

Clock latency = Source latency + Network latency

Q59. What is Pad limited design and core limited design. Is there any difference in
approaches to handle these?
Pad limited design:
The Area of pad limits the size of die. No of IO pads may be lager. If die area is a
constraint, we can go for staggered IO Pads.
Core limited design:
The Area of core limits the size of die. No of IO pads may be lesser. In these designs in
line IOs can be used

Q60. How will we decide chip core area?

Core Size = (Standard cell area/Standard cell utilization ) + Macro Area + Halos

Die Size = Core Size + IO to Core Clearance + Area of Pad (Including IO Pitch Area) + Area
of Bond longest Pad

Q61. How to arrive at the value of utilization factor and aspect ratio during initial
floorplan?

Q62. What is an HALO? How is it different from the blockage?

Block halos can be specified for hard macros, black boxes, or committed partitions. When you
add a halo to a block, it becomes part of the blocks properties. If you move the block, the halo
moves with it. Blockages can be specified for any part of the design. If we move a block, the
blockage will not

Q63. How much utilization is used in the design?

There is no hard and fast rule, even though if the following values maintained then the design
can be closed without much congestion.
▪ Floor Plan - 70 %
▪ Placement - 75 %
▪ CTS - 80 %
▪ Routing - 85 %
▪ During GDSII Generation – 100 %

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Q64. What is the difference between standard cells and IO cells? Is there any difference
in the IR operating voltages? If so why is it?
▪ Std Cells are logical cells. But the IO cells interact between Core and Outside
world.
▪ IO cells contains some protection circuits like short circuit, over voltage.
▪ There will be difference between Core operating Voltage and IO operating
voltage. That depends on technology library used.

Q65. What is the significance of simultaneous switching output (SSO) file?

Q66. Is there any checklist to be received from the front end related to switching activity
of any nets to be taken care of at the floor planning stage?
Yes. The Switching activities of Macros will be available in checklist; it contains the power
consumption of each macro at different frequencies are also available

Q67. What is power trunk?

Power trunk is the piece of metal connects the IO pad and Core ring.

Q68. How to handle hotspot related to power in a chip?

Increasing the number of power straps or increasing the width of power strap will help us to
reduce hot spot created by voltage drop and to maintain the voltage drop less than 10 %.

Q69. What is power gating?

Power gating is one of power reduction technique. This helps by shutting down the particular
area of chip from utilizing power.

Q70. Whether macro power ring is mandatory or optional?

For hierarchical design the macro power ring is mandatory. For flat design the macro power
ring is optional.

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Q71. If you have both IR drop and congestion how will you fix it?
▪ Spread macros
▪ Spread standard cells
▪ Increase strap width
▪ Increase number of straps
▪ Use proper blockage
Q72. Is increasing power line width and providing more number of straps are the only
solution to IR drop?
▪ Spread macros
▪ Spread standard cells
▪ Use proper blockage
Q73. what is tie-high and tie-low cells and where it is used?

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