EE2026

Digital Design
MODULE INTRODUCTION
Chua Dingjuan elechuad@nus.edu.sg

Slides credit to Prof Massimo Alioto and Prof YP Xu

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Digital Design Page 2

 Course Description
First course on digital systems
oIntroduces fundamental digital logic, digital circuits, and
programmable devices
oThe course also provides an overview of computer systems
oThis course provides students with an understanding of the
building blocks of modern digital systems and methods of
designing, simulating and realizing such systems
oThe emphasis of this module is on understanding the
fundamentals of digital design across different levels of
abstraction using Hardware Description Languages
oDeveloping valuable design skills for the design of digital
systems through FPGAs and state-of-the-art CAD tools, as
required by the job market (exciting projects)
3
Digital Design
Course Team
Lecturer : Dr. Chua Dingjuan

Lab Instructors :
Mr. Christopher Moy, Dr. Goh Shu Ting

Tutors :
Mr. Christopher Moy, Dr. Goh Shu Ting, Mr. Shao YuRui,
Ms. Tuteja Sugandha

Lab Officers:
Mr. Ho Fook Mun, Ms. Chia Meow Hwa and Mdm. Goh Kah
Seok

4
Digital Design
Course Lecture Structure
Contents Some portion of every
Part 1 (Combinational Logic) week’s lecture will be
◦ Number systems + Verilog devoted to Verilog 
◦ Boolean Algebra and logic gates + Verilog
◦ Gate-level design and minimization + Verilog
◦ Combinational logic blocks and design + Verilog

Part 2 (Sequential Logic)

◦ Basic Sequential Logic Blocks - Flip-flops + Verilog
◦ Counters + Verilog
◦ Combining combinational/sequential building blocks + Verilog
◦ Finite State Machines + Verilog

5
Digital Design
Course Organization (Refer Canvas)
Lab
Lecture
Week (E4-03-06 Digital Tutorial
(LT6)
Electronics Lab)

WK 1 ✓

WK 2 ✓ Tutorial – 1

Happy Lunar New Year and Online Make-up Lecture on

Tutorial – 2
WK 3 HAPPY HOLIDAYS! 25 Jan Sat (Recorded) Makeup Monday 27 Jan
5PM (Check w Tutor!)

WK 4 Lab 1 ✓ Tutorial – 3

WK 5 Lab 2 ✓ Tutorial – 4

Mid-Semester Quiz
WK 6 Lab 3 20 Feb 25 - 915AM to
1045AM

Recess Week
6
Digital Design
Course Organization (Refer Canvas)
Week Lab Lecture Tutorial

WK 7 Project 1 ✓ Tutorial – 5

WK 8 Project 2 ✓ Tutorial – 6

✓
WK 9 Project 3 Tutorial – 7
Guest Lecture
WK 10 Verilog Evaluation Tutorial – 8

WK 11 Final Quiz

WK 12

WK 13 Project Assessment and Demo

No final exam 
7
 Course Assessment
Component Assessment Weight
Quizzes Total 40%
o Mid-Term Quiz 17%
o Weekly Canvas Quizzes 6%
o Final Quiz 17%
Labs Total 30%
o Lab Assignment 1 3%
o Lab Assignment 2 5%
o Lab Assignment 3 10%
o Verilog Evaluation 12%
Design Project – Team Work Total 30%
o Project basic features (specified) 30%
o Enhanced features (open-ended)

No final exam 
9
Digital Design
Quizzes
o Mid-Semester Quiz 1 – 17%
o Week 6 Thursday 20 Feb 25 - 915AM to 1045AM @ Venue TBA
o Closed book test, single A4 (two sided) help/crib/cheat sheet allowed.
o Calculators are not allowed.
o Includes Part 1 lecture topics covered from Week 1 to Week 4.
oEnd-Semester Quiz 2 – 17%
o Week 11 Thursday 03 Apr 25 - 915AM to 1045AM @ Venue TBA
o Closed book test, single A4 sized (two sided) help/crib/cheat sheet is allowed.
o Calculators are allowed.
o Includes Part 2 lecture topics covered from Week 5 to Week 8.
oWeekly Canvas Quizzes – 6%
o Questions to identify misconceptions and reinforce of concepts
o MCQ, MRQ, FIB, etc
o 3 Attempts, Best Score Taken
10
Digital Design
LAB / PROJECT REMINDER
o EE2026 is a hands-on module 
significant lab and project time / components
o Software : Xilinx Vivado 2018.2
o Referring to installation instructions provided on Canvas,
please install the software by end of Week 3
o Unfortunately, this software is not supported on Mac
operating systems (only windows / linux)
o If you have difficulties accessing a windows-based system,
PC Cluster access is available. Details on Canvas Pages >>
EE2026 - PC Cluster Access for Mac Users
o Project will be done in groups of 4, students are to be from
same lab group.

11
Digital Design
 Course Information
Course materials
◦ Canvas (Everything about the course)

Need Help?
◦ Tutors (tutorial questions)
◦ TAs and GAs (labs and projects)
◦ During lab sessions
◦ Face-to-face consultation with lecturer:
◦ By appointment, email elechuad@nus.edu.sg

Reference book (download from NUS library)

◦ D. Harris, S. Harris, Digital Design and Computer Architecture
(1st ed.), Morgan Kaufmann, 2007

12
Digital Design
 Expected Learning Outcomes
Expected learning outcome (Part 1)
◦ Be able to perform conversion between binary, octal, hexadecimal
and decimal number systems, and solve simple problems;
◦ Understand Boolean Algebra, and manipulate and simplify Boolean
functions using theorems and postulates;
◦ Be able to design simple combinational logic circuits based on Truth
table and Karnaugh Map
◦ Be able to design complex combinational logic circuits using Hardware
Description Languages (Verilog) and/or combinational building blocks
◦ Be able to simulate complex combinational blocks and verify their
proper functionality through behavioural simulation
◦ Be able to design combinational logic circuits for practical problems /
applications

13
Digital Design
 Expected Learning Outcomes
Expected learning outcome (Part-2)
◦ Be able to describe simple sequential logic circuits based on functional
descriptions
◦ Be able to describe simple sequential logic circuits based on state
transition diagrams
◦ Be able to design complex logic circuits using Hardware Description
Languages (Verilog) and/or sequential/combinational building
blocks/IPs
◦ Be able to simulate complex blocks and verify their proper
functionality through behavioural simulation
◦ Be able to design complex logic circuits for practical problems /
applications

14
Digital Design
 Why Study this
Module?

Digital Design Page 15

 Why study this module?
The module is about the fundamentals of digital systems,
which is important if you are interested in the design of
digital circuits and systems, especially if you plan to
specialize in the following areas:
◦ Integrated circuit design (very important)
◦ Digital integrated circuits (very important)
◦ Embedded systems and Computer Architecture (very important)
It’s the first module about Hardware Description Language
(HDL), which is widely used for digital system design and
modeling
You will also learn analytical and problem solving skills
through the projects (practical design problems)
It also serves as prerequisite for other modules at senior
levels (EE4415). It is complementary to EE2028, CG3207,
EE4218.
16
Digital Design
 EE2026:
Not Just Another Module…
Think & do: strong foundations, real-world design
◦ Industry-relevant project

– This year: machine learning and human-machine interfaces

handwritten input

text output (classification)

your design on FPGA board

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Digital Design
EE2026: Quite Unique…
Design skills in high demand

◦ FPGA designer (startups, SMEs, MNCs)

◦ Semiconductor industry

AND SO ON AND SO FORTH…

◦ Not capital intensive: create YOUR OWN technology/company

19
Digital Design
INTRODUCTION
 Analog vs. Digital Circuit
•Analog circuit deals with continuous signals
•Digital circuit deals with signals having discrete levels

V Analog signal V Digital signals

t t

Analog circuit is more susceptible to noise

Digital circuit is a binary system which is much more robust

26
Digital Design
 Why Digital?
o Robustness (reliability)
o Programmability
o Scalability (in integrated circuit technology)
o Cost

27
Digital Design
Technology Scaling
Transistors got smaller over time (at a relentless pace)
µm
10

1 0.8 µm 0.5 µm
0.35 µm 0.25 µm
0.18 µm
0.1 0.13 µm 90 nm
65 nm
45 nm
32 nm 22 nm
0.01 10 nm
7 nm
5 nm
3 nm
0.001
1970 1980 1990 2000 2010 2020 2030
year
28
Digital Design
Technology Scaling (cont.)
1971:
• Intel 4-bit processor in 10 µm PMOS process
with 2300 transistors
• Initial clock speed of 108 kHz
• 10µm pMOS technology

2020:
• AMD Epyc Rome 7 nm processor (64 cores, 256MB
L3, Zen 2 arch.) 40B transistors
• IBM z15 5.2 GHz clock freq., 12 cores in 14 nm
FinFET, 9.2B transistors
• Intel Xeon Platinum 8180 in 14nm CMOS (28
cores), 3.6 GHz, 205 W, 8B transistors
• nVIDIA Ampere, 7nm FinFET, 5 PFLOPS, 54B
transistors
29
Digital Design
Technology Scaling (cont.)
10000
millions of transistors/die

1000
100
10 Moore’s
1 law
0.1
0.01
0.001
1970 1980 1990 2000 2010 2020
year
As more and more transistors can be integrated on a single chip,
- functionality is increased
- for the same functionality: lower chip area, lower cost per transistor
30
Digital Design
 Digital Revolution & Information Age
1947 – Invention of transistor
1971 – First microprocessor
*Rapid development of digital computing and communication technology
brought about the digital revolution and information age
1980s – Personal computers
1990s – World Wide Web, digital cameras
2000s – Mobile phones, digital TVs, ipod
2010 – Smart phones, xPad, cloud computing (accessible
everywhere), social networking (constantly connected)
2020 – Cloud computing, Internet of things, ultra-low
power high-performance mobile computing, ubiquitous
computing, immersive computing/augmented reality,
gesture recognition...

31
Digital Design
 Example in Your Pocket (Today)
Application Processor (AP) Image sensor + pre-processing
(microprocessor cores, GPU, LTE modem
memory, video processing…)

Touchscreen
controller

Image sensor +
pre-processing
smart battery
(charge, wearing, GPS, WiFi, DRAM, Flash, RF transceiver, Power
genuineness) Management, NFC, audio, display power management,
Digital Design FPGA, battery charger, compass, other sensors 32
 Example Available Everywhere
(Tomorrow) from GREEN IC Group

energy
1.2 V
http://www.green-ic.org
0.3 V
Ultra-low Energy-
CORE

tiny sensing platforms

voltage scalable
TECHNOLOGIES ckts/systems ckts/systems

CONNECTING data-driven HW-level

ckts/systems security
THE DOTS
emerging technologies
LEVERAGING NEW POSSIBILITIES
- MEMS, STT-MRAMs, TFETs, ...

computer vision in IoT most (cyber)secure AES in 100 nW 1st lunar-powered

for 1st time (55 µW) “silicon fingerprint” (0.1µmx0.1µm solar cell) chip (power
∼1nW)
3.08mm

IMEM

bank 0
bank 1
bank 2
bank 3
bank 4
bank 5
bank 6
bank 7
testing harness
clk. gen.
MCU core

3.08mm

bank 0
bank 1
bank 2
bank 3
bank 4
bank 5
bank 6
bank 7
DMEM
ripple self-startup & headers

solar cell

sub-µW machine 1st mm-scale CO2 sensor PRESS

1st book
learning (perpetual operation)
ADC
resolution
# of
features
on chip
MEMS MEMS
design
TinyCO2
E-Q SCALING heater Integrated System thermop
speech ile
analog FFT
feature
classifier
activity? speech ...
for IoT
+

extractor recognition
Voice Activity Detector (VAD)
33
Digital Design voice controlled device
Heaters array Thermopiles array
EE2026
Digital Design
NUMBER SYSTEMS & VERILOG INTRO
Chua Dingjuan elechuad@nus.edu.sg
NUMBER SYSTEMS
Positional Number Systems : Decimal, Binary, Hex
Binary Arithmetic
Introduction to Verilog
 Positional Number System (Decimal)
Decimal number: Digits (0 to 9) Radix (r=10)
Terminologies
◦ Radix (or base)
◦ Digits and a numeral (0 
radix-1) Number 1260.25
◦ Radix point
◦ Place value (or weight) is in
the power of the base 103 100 10-1
(positive on the left and
negative on the right side of 102
Radix point
the radix point integer part fractional part

N = 1×103 + 2 ×10 2 + 6 ×101 + 0 ×100 + 2 ×10 −1 + 5 ×10 −2 = 1260.25

*Weighted sum of each digit (each digit is weighted by its place value)

6
Digital Design
 Radix r and its Decimal Equivalent
General form of Number of radix r:
Radix point
Ar = ( an an −1... ao .a−1... a− m )r
where an , an −1,..., a0 ,..a− m ∈ {0,...( r − 1)} (Integer only)

Decimal equivalent:
Ar = (an an −1... ao .a−1... a−m )r Radix point is here

= an × r n + an −1 × r n −1 + ... ao × r 0 + a−1 × r −1 + ... a−m × r −m

n
= ∑a r
i =− m
i
i

*Weighted sum of all digits

7
Digital Design
 Binary Number
Digits (0 to 1) Radix (r=2)

Number 10110.01

20 2-1
Radix point
24
Decimal Equivalent: 23

N10 = 1 × 24 + 0 × 23 + 1 × 22 + 1 × 21 + 0 × 20 + 0 × 2 −1 + 1 × 2 −2
1
= 16 + 0 + 4 + 2 + 0 + 0 +
4
= 22.25
(10110.01)2 = (22.25)10
8
Digital Design
MSB and LSB of a Binary Number
MSB
◦Most significant bit
LSB
◦Least significant bit

1011001
(Left-most bit) MSB LSB (Right-most bit)

*For integer binary number only

Range
◦ 0 to 2n – 1, where n is the number of bits ( 2n values )
9
Digital Design
 ( 1 1 0 1 . 0 1 1 0 )2
Hexadecimal number ( D . 6 )16
Digits (0 to 15) Hex Dec Bin
Radix (r=16) 0 0 0000

1 1 0001

Number 18F4.2A 2 2 0010

3 3 0011

4 4 0100
16-2
163 2 160 16-1 5 5 0101
16
6 6 0110
Radix point
Decimal Equivalent: 7 7 0111

3 2 1 0 −1 −2 8 8 1000
N10 = 1 × 16 + 8 × 16 + F × 16 + 4 × 16 + 2 × 16 + 10 × 16
9 9 1001
2 10
= 4096 + 2048 + 240 + 4 + + A 10 1010
16 256 B 11 1011

21 C 12 1100
= 6388 +
128 (18F4.2A)16 ≅ (6388.16)10 D 13 1101

≈ 6388.16 E 14 1110

F 15 1111
10
Digital Design
 ( 1 0 1 . 0 1 1 )2
Octal number ( 5 . 3 )8
Radix (r=8) Digits (0 to 7) Oct Dec

0 0

1 1

Number 754.2 (754.2)8 = (520.25)10 2

3
2

4 4

80 8-1 5 5
82 6 6
Decimal Equivalent: Radix point
7 7

N10 = 7 × 82 + 5 × 81 + 4 × 80 + 2 × 8−1 ? 8

? 9
2
= 448 + 40 + 4 + ? 10
8
= 492.25

11
Digital Design
Numbers with Different Radixes:
Summary
Numbers with Different Radixes
Decimal Binary Octal Hexadecimal
(radix 10) (radix 2) (radix 8) (radix 16)

12
Digital Design
 Radix Conversion
Three types of conversions:
o Radix r (r≠10)  Decimal

o Decimal  Radix r (r≠10)

o Conversion among Binary, Octal and Hex numbers

13
Digital Design
 Radix r (r ≠ 10)  Decimal (r = 10)
Binary  Decimal (10110.01)2 = (??)10

(10110.01)2 → 1 × 24 + 0 × 23 + 1 × 22 + 1 × 21 + 0 × 20 + 0 × 2 −1 + 1 × 2 −2 = (22.25)10

Hex  Decimal (18F4.2A)16 = (??)10

(18𝐹𝐹𝐹.2𝐴𝐴)16 = 1 × 163 + 8 × 162 + 𝐹𝐹 × 161 + 4 × 160 + 2 × 16−1 + 10 × 16−2
≈ (6388.16)10

*Compute the weighted sum of all digits

Ar = (an an −1... ao .a−1... a−m )r
= an × r n + an −1 × r n −1 + ... ao × r 0 + a−1 × r −1 + ... a−m × r −m
n
= ∑a r
i =− m
i
i

14
Digital Design
 Decimal (r = 10)  Radix r (r ≠ 10)
Decimal  Binary (102)10 = (??)2
(102)10 = A2 = ( an an −1... ao .a−1... a− m )r
= an × 2 n + an −1 × 2 n −1 + ... + a1 × 21 + ao (Assume integer)
= ( an × 2 n + an −1 × 2 n −1 + ... + a1 × 21 ) + ao

Integer multiple of 2

(102)10 Continue dividing quotient by 2

→
2
quotient an × 2 n −1 + an −1 × 2 n − 2 + ... + a1 an × 2 n − 2 + an −1 × 2 n −3 + ... + a1
an × 2 n + an −1 × 2 n −1 + ... + a1 × 2 + ao an × 2 n −1 + an −1 × 2 n − 2 + ... + a1
2 2
n n −1
an × 2 + an −1 × 2 + ... + a1 × 2 an × 2 n −1 + an −1 × 2 n − 2 + ...
ao a1
Remainder is a0 Remainder is a1
15
Digital Design
Decimal  Radix r (r ≠ 10) – cont.

Decimal  Binary (102)10 = (??)2

Division Quotient Remainder (102)10 = (110 0110)2

102/2 51 0  a0
Check:
51/2 25 1  a1

25/2 12 1  a2 N10 = a6 × 26 + a5 × 25 + a4 × 2 4 + a3 × 23
12/2 6 0  a3 + a2 × 2 2 + a1 × 21 + a0 × 20
6/2 3 0  a4 = 1 × 2 6 + 1 × 25 + 0 × 2 4 + 0 × 23
3/2 1 1  a5 + 1 × 2 2 + 1 × 21 + 0 × 20
1/2 0 1  a6 = 64 + 32 + 0 + 0 + 4 + 2 + 0
= 102
Stop when the quotient = 0

16
Digital Design
 How about Fractional Numbers?
Decimal  Binary (0.58)10 = (??)2

(0.58)10 = A2 = (0.a−1a− 2 ... a− m +1a− m )r

= a−1 × 2 −1 + a− 2 × 2 − 2 + ... + a− m +1 × 2 − m +1 + a− m × 2 − m

Multiply by 2:

(0.58)10 × 2 = a−1 + a− 2 × 2 −1 + ... + a− m +1 × 2 − m + 2 + a− m × 2 − m +1

Integer part is a-1 fractional part

17
Digital Design
 How about Fractional Numbers? – cont.
Decimal  Binary (0.58)10 = (??)2

Multiply Product Integer

by 2 Part
0.58x2 1.16 1  a-1 (0.58)10 = (0.1001 01)2
0.16x2 0.32 0  a-2
Check:
0.32x2 0.64 0  a-3
0.64x2 1.28 1  a-4 N10 = 1 × 2 −1 + 1 × 2 −4 + 1 × 2 −6
0.28x2 0.56 0  a-5 1 1 1
= + +
0.56x2 1.12 1  a-6 2 16 64
= 0.578125
0.12x2 0.24 0  a-7
≈ 0.58
0.24x2 0.48 0  a-8

- The conversion process may never end.

- Where to stop depends on the required precision
- The process only ends when fractional part = 0
18
Digital Design
Binary Arithmetic
ADDITION, SUBTRACT, MULTIPLICATION, DIVISION

Page 19
Addition
Addition table:

0+0=0
0+1=1
1 + 1 = 10

“1” is the carry to the next higher bit

Example:
10111 + 110 = 11101

1 1
Carry
10111
+ 110
---------------
11101

20
Digital Design
 Multiplication
Multiplication table:

0x0=0
0x1=0
1x1=1 Example:
10111 x 110 = 10001010

10111 Multiplicand
x 110 Multiplier
---------------
Multiplication: 00000
 Shift then Add 10111 Partial products
 Only need “add” operation + 10111
----------------------
10001010 Product

21
Digital Design
 Subtraction
Subtraction table:

0-0=0
1-0=1
1-1=0
0–1=1 with a borrow from the next (higher) bit

Example:
11011 - 110 = 10101

11011
- 110
---------------
10101

22
Digital Design
 Division (shift and subtract)
 Shift then subtraction
Division  Only need “subtract” operation

• Set quotient to 0
100101/101 = ?
• Align leftmost digits in dividend and divisor
• Repeat
111 quotient • If that portion of the dividend above
the divisor is greater than or equal to
101 100101 the divisor
101 • Then subtract divisor from that
portion of the dividend and
1000 • Concatenate 1 to the right hand
101 end of the quotient
• Else concatenate 0 to the right
111 hand end of the quotient
101 • Shift the divisor one place right
• Until dividend is less than the divisor
10 remainder
• quotient is correct, dividend is remainder
• STOP
Check in decimal
23
Digital Design
Arithmetic
•Only addition, subtraction and shifting are needed
for 4 binary arithmetic operations
•Subtraction can be performed by adding a negative
number
•Thus, a computer may only use adders and shifters
to perform all binary arithmetic operations
•This requires an appropriate representation of the
negative binary numbers

 Signed Number Representation

24
Digital Design
Signed Binary numbers
Three ways to represent the signed binary
numbers

◦Signed Magnitude (Sign + magnitude)

◦1’s complement
◦2’s complement

25
Unsigned Binary number

Unsigned binary number (n bits) Example:

Decimal Unsigned
binary
1 1 0 1 … … 1 0
0 000
1 001
Magnitude 2 010
(No sign, always positive) 3 011
4 100
Range of unsigned binary number:
5 101
Max value of a 4-bit number: 6 110
24 23 22 21 20 7 111
1111 = 1 0 0 0 0 – 1  (24) 10 -1

Max value of n-bit unsigned number in decimal  2n – 1. Range: 0 ~ (2n-1)

26
Signed Binary – Signed Magnitude (S-M)
Example:
Signed binary number (n bits)
Decimal S-M
3 011
1 0 1 … … 1 0
2 010
1 001
Note:
Magnitude +0 000 Two zeros
-0 100
Sign bit 0 – represents a positive number
-1 101
1 – represents a negative number
-2 110 Negative
MSB is a sign bit numbers
-3 111

“1” in MSB position for all negative numbers

27
 Signed Magnitude – cont.
More examples: 00111010 = +0111010 = (58)10

11100101 = - 1100101 = (-101)10

10000001 = - 0000001 = (-1)10

01111111 = +1111111 = (+127)10

Range of binary number represented by S-M:

For a n-bit Signed binary (S-M), its magnitude is (n-1) bits

Max magnitude: (2n-1-1)10

Range: -(2n-1-1)10 ~ +(2n-1-1)10

28
 Arithmetic
using Binary Numbers (S-M) ?
Computer performs binary arithmetic operations using only
◦ Adders
◦ Multipliers
Subtraction is performed by adding a negative number

Examples of subtraction using S-M binary representation:

3 011 3 011 2 010

- 2 + 110 - 1 + 101 - 1 + 101
------- ------- ------- ------- ------- -------
1 1001 (1)10 2 1000 (0)10 1 111 (-3)10
  
Discarded Discarded
*S-M representation cannot be used for addition of two number with opposite signs
or subtraction when using a simple adder
(dedicated hardware is needed for all possible sign combinations)
29
Complement Representation
Complement representations of a number
◦Radix complements
◦Diminished complements
Definitions:
- Radix Complement
of a n-digit integer number A with radix (r):
A* = rn – A

- Diminished radix complement

of a n-digit integer number A with radix (r):
A* = rn – A - 1

30
 Diminished Radix Complement
A* = rn – A – 1 or A*= (rn – 1) - A
Examples:

Decimal Operation: 1 1 1
888 888 888
A = 237  A* = (100010 – 1) - 23710 - 237 ⟺ + (-237) ⟺ + 762
= 99910 – 23710 651 ______ 650
+1
= 76210 651

Binary number:
A = 0011  A* = (100002 – 1) – 00112 = 11112 – 00112 = 11002

A = 1100  A* = (100002 – 1) – 11002 = 11112 – 11002 = 00112

Shortcut! 
Diminished radix 2 complement
can be found by reversing the bits =)
This is also called 1’s Complement.
31
1’s Complement
“1’s Complement” is the diminished radix complement of
binary numbers
1’s complement of a n-bit number is A* = (2n – 1) - A
1’s complement of a binary number can be obtained by
reversing the bits, i.e. “1”  “0” and “0”  “1”, since
(2n – 1)10 = 1000…000 - 1 = 111…111
n+1 bits n bits

Binary number (n=8): 0101 1100

1’s Complement: 1111 1111 - 0101 1100 = 1010 0011
Reversing the bits

32
1’s Complement representation of
signed binary number
No change for positive numbers and use 1’s complement for negative numbers

1’s Magnitude range: -(2n-1-1) ~ (2n-1-1)

Decimal Complement 3 – 2 = 3 + (-2) = 1 - 3 + 1 = - 3+ 1 = -2
3 011
011 3 100 -3
2 010
+ 101 + (-2) + 001 + ( 1)
1 001 -------- ------- -------- -------
+0 000 (1)000 (0)101
+ 1 + 0
-0 111
-------- ------- -------- -------
-1 110 001 +1 101 - 2
-2 101  -------  -------
-3 100 * Subtraction can be performed by adding the carry!

Two Zeroes?

33
2’s Complement of a Binary Number
“2’s Complement” is the radix complement of binary
numbers
2’s complement of a n-bit number can be obtained by
adding “1” to its 1’s complement (reversing all the bits), i.e.,
A* = 2n – A
= (2n – A -1) + 1
Binary number (n=8): 01011100

2’s Complement: 10100011 + 1 = 10100100

1’s complement 2’s complement

34
 2’s Complement Arithmetic
No change for positive numbers and use 2’s complement for negative numbers

Decimal 2’s 3 – 2 = 3 + (-2) =1 -3 + 1 = - 3 + 1 = -2

Complement
011 3 101 -3
3 011
+ 110 + (-2) + 001 + ( 1)
2 010 -------- ------- -------- -------
1 001 (1)001 +1 (0)110 - 2
0 000 ------- -------
-1 111 Carry ignored Carry ignored
-2 110
-3 101 - Subtraction can be done!
-4 100 - Carry is discarded (there is NO NEED to shift
and add the carry, thus more hardware
Only one zero efficient)

Magnitude range: -(2n-1) ~ (2n-1-1)

35
Signed Binary Number (Recap)
Sign+Magnitude
◦ Two zero representations (+/- zeros)
◦ It cannot correctly perform subtraction
◦ Magnitude range: -(2n-1-1) ~ (2n-1-1)
1’s Complement (Diminished radix complement)
◦ Defined as: A* = (2n -1) – A
◦ 1’s complement can be obtained by reversing the bits
◦ Two zero representations (+/- zeros)
◦ It can correctly perform subtraction, but needs to shift and add the carry
◦ Magnitude range: -(2n-1-1) ~ (2n-1-1)
2’s Complement (Radix complement)
◦ Defined as: A* = 2n - A
◦ One zero representation
◦ It can correctly perform subtraction by just ignoring the carry
◦ 2’s complement can be obtained by adding “1” to its 1’s complement
◦ Magnitude range: -(2n-1) ~ (2n-1-1)
Positive numbers are same in all 3 signed binary number representations
36
Introduction to Verilog
Hdl, module, I/Os, wires, reg,
operators

©COPYRIGHT CHUA DINGJUAN. ALL RIGHTS RESERVED.

Background…
An IBM Standard Modular System (SMS)
printed-circuit card from the early-1960s.
This particular card implemented three
simple logic gates. 1980s
Hardware Description
1971 Languages :
VHDL & Verilog

1950s – 1960s
Rapid
1947 Development of
Technology Intel 4-bit
The First Processor
Transistor 2300 Transistors
~ 400 gates
Robert, G. (2013) IBM Standard Modular System [Photograph] Retrieved 1 Dec, 2014, from IEEE Global History Network, Early Popular Computers, 1950 - 1970 http://www.ieeeghn.org/wiki/index.php/File:EPC_-_fig_4.jpg

Digital Design Page 38

 What are HDLs?
Hardware Description Languages (HDLs) are programming
languages for describing digital circuits and systems.
CONCURRENCY STRUCTURE & TIME
time t
A Input / Output ports, multiple bits
B
Z MUX +
C
D ∆t1 ∆t2
time t + ∆

Today, Verilog and VHDL are the two leading HDLs.

Verilog code is used to describe RTL (Register Transfer Level) designs.
Virtually every chip (FPGA, ASIC, etc.) is designed in part using one of
these two languages.
Xilinx and Altera are the two largest FPGA manufacturers.
(AMD) (Intel)
Digital Design Page 39
Verilog…
Verilog is an IEEE 1364 Standard  link here
Used for Modeling, Simulation and Synthesis of digital circuits.
Focus on synthesizable logic in this module.
Advantages :
◦ Reduces Design Time  Cost
◦ Improves Design Quality
◦ Vendor and Technology Independence
◦ Easy Design Management
Disadvantages :
◦ Cost (Including training you and me!)
◦ Debugging

Digital Design Page 40

 The Module
A piece of hardware with inputs & outputs : module
Module a box
Name Port Declaration y
b
module box( input a, b
input [1:0] c, c
2
output [3:0] y );
// Here is where the magic
happens!
endmodule

o Verilog is CasE-SeNSitiVe….
o Module Name : No spaces, No starting with numbers (1box), use meaningful names (box)
o Port Direction : input, output, inout (bidirectional)
o Port Bitwidth : input a,b ; input [1:0] c ; output [3:0] y
By default, signals Input c is a 2-bit vector Output y is a 4-bit vector
are one bit! (little endian) y : y[3] y[2] y[1] y[0]
o Don’t forget the __;____!

Digital Design Page 41

 Data Types – Net / wire
module box( input a, b box
input [1:0] c,
output [3:0] y ); a 4
tmp
wire tmp; b y
2
assign tmp = a; c

assign y[3:0] = 4’hA;

//We can also write assign y = 4’hA;
//What is the driver? y = 4’hA
Value in hexa
4 binary bits radix (b,o,d,h)
endmodule
o Input and output ports default to the wire or net type.
o In Verilog, a 1-bit net can take 3 basic values – 0 , 1, Z (high impedance).
o Nets do not store a value, and its value is determined by its driver (just like a wire!)
o If no driver is connected to a net, the value shall be high-impedance Z.
o Nets are connected to drivers via assign statements.
Digital Design Page 42
 Data Types – Variables / reg
module box( input a, b box
input [1:0] c,
a one two
output [3:0] y ); 4
b 2’b11 X y
reg [1:0] one = 2’b1_1; 2
three
reg two; c
integer three = 7; 0000 0000
//7 interpreted as decimal 0000 0000
0000 0000
0000 0111
endmodule
o Variables is an abstraction of a data storage element and is of reg type.
o When uninitialized, the value will be X (unknown).
o reg variables can be used to model both combinatorial or sequential logic.
o Assignments to reg are made via procedural assignments (always @ )
o Registers cannot be connected to nets
o integer is a general purpose variable for manipulating quantities and not regarded as
hardware. When the size is undefined, it is by default 32-bit.
Digital Design Page 43
Numerical Values (IEEE Std 1364-2001 p9)
Example 1—Unsized constant numbers
◦ 659 // is a decimal number
◦ ’h 837FF // is a hexadecimal number
◦ ’o7460 // is an octal number
◦ 4af // is illegal (hexadecimal format requires ’h)
Example 2—Sized constant numbers
◦ 4’b1001 // is a 4-bit binary number
◦ 5 ’D 3 // is a 5-bit decimal number
◦ 3’b01x // is a 3-bit number with the least significant bit
unknown
◦ 12’hx // is a 12-bit unknown number
◦ 16’hz // is a 16-bit high-impedance number
Example 3—Using sign with constant numbers
◦ 8 ’d -6 // this is illegal syntax
◦ -8 ’d 6 // this defines the two’s complement of 6, held in 8
bits—equivalent to -(8’d 6)
◦ 4 ’shf // this denotes the 4-bit number ‘1111’, to be
interpreted as a 2’s complement number, or ‘-1’. This is
equivalent to -4’h 1
◦ -4Design
Digital ’sd15 // this is equivalent to -(-4’d 1), or ‘0001’ Page 44
Numerical Values (IEEE Std 1364-2001 p9)
Example 4—Automatic left padding
reg [11:0] a, b, c, d;
initial begin
a = ’h x; // yields xxx
b = ’h 3x; // yields 03x
c = ’h z3; // yields zz3
d = ’h 0z3; // yields 0z3
end
Example 5—Using underscore character in numbers
o 27_195_000
o 16’b0011_0101_0001_1111
o 32 ’h 12ab_f001

Digital Design Page 45

 Useful Operators
Operator Description Examples: a = 4’b1010, b=4’b0000

High !, ~ Logical negation, Bit-wise NOT !a = 0, !b =1, ~a=4’b0101, ~b=4’b1111

&, |, ^ Reduction (Outputs 1-bit) &a = 0, |a=1, ^a = 0
{__,__} Concatenation {b, a} = 8’b00001010
{n{___}} Replication {2 {a} } = 8’b10101010
*, /, %, Multiply, *Divide, *Modulus 3 % 2 = 1, 16 % 4 = 0
Precedence

+, - Binary addition, subtraction a + b = 4’b1010

<< , >> Shift Zeros in Left / Right a << 1 = 4’b0100, a >> 2 = 4’b0010
<, <=, >, >= Logical Relative (1-bit output) (a > b) = 1
==, != Logical Equality (1-bit output) (a == b)= 0 (a != b)= 1
&, ^, | Bit-wise AND, XOR, OR a&b = a|b =
&&, || Logical AND, OR (1-bit output) a&&b = a||b =
Low ?: Conditional Operator <out> = <condition> ? If_ONE : if_ZERO

Digital Design Page 46

 What is happening here?
o Let’s assume that a, b and c are being box
provided these values as shown  a=1
b=0 4
module box( input a, b 2
y
input [1:0] c, c = 2’b10
output [3:0] y );
wire tmp; Net / Variable Number Value in
reg [1:0] one = 3; Name of bits? dec / bin
reg two; a 1 1 / 1’b1
integer three = 1;
b 1 0 / 1’b0

assign y[3] = one[0]; c 2 2 / 2’b10

tmp 1 Z / 1’bZ
assign y[2:1] = a + c; one 2 3 / 2’b11
two 1 X / 1’bX
assign y[0] = ( a > b ) ;
three 32 1 / 32’h00000001
endmodule y 4 15 / 4’b1111

Digital Design Page 47

Summary
We have covered :
•Positional number system (radix 10, 2, 8 and 16)
•Conversion among decimal, binary, octal and hex
•Binary arithmetic

We have covered:
•Introduction to Verilog
•Module, input and output ports (Single Bit and Multi-Bit signals)
•Data Types (wire/net vs reg)
•Numerical values (Hexa/Decimal/Binary/Octal/Integer)
•Addition / Subtraction / Conditional Operators

Digital Design Page 48

EE2026
Digital Design
NUMBER SYSTEMS & VERILOG INTRO
Chua Dingjuan elechuad@nus.edu.sg
Ask Weekly Questions here…
You can ask questions during the week using
slido below! (Slido remains open for the week)

https://app.sli.do/event/vD2MFRBXFNYkBEtmu
dX7gV

Or at slido.com + #2026 001

Or the tiny little QR :

Digital Design Page 2

Digital Design Page 3
NUMBER SYSTEMS
Positional Number Systems : Decimal, Binary, Hex
Binary Arithmetic
Introduction to Verilog
 Positional Number System (Decimal)
Decimal number: Digits (0 to 9) Radix (r=10)
Terminologies
◦ Radix (or base)
◦ Digits and a numeral (0 
radix-1) Number 1260.25
◦ Radix point
◦ Place value (or weight) is in
the power of the base 103 100 10-1
(positive on the left and
negative on the right side of 102
Radix point
the radix point integer part fractional part

N = 1×103 + 2 ×10 2 + 6 ×101 + 0 ×100 + 2 ×10 −1 + 5 ×10 −2 = 1260.25

*Weighted sum of each digit (each digit is weighted by its place value)

5
Digital Design
 Radix r and its Decimal Equivalent
General form of Number of radix r:
Radix point
Ar = ( an an −1... ao .a−1... a− m )r
where an , an −1,..., a0 ,..a− m ∈ {0,...( r − 1)} (Integer only)

Decimal equivalent:
Ar = (an an −1... ao .a−1... a−m )r Radix point is here

= an × r n + an −1 × r n −1 + ... ao × r 0 + a−1 × r −1 + ... a−m × r −m

n
= ∑a r
i =− m
i
i

*Weighted sum of all digits

6
Digital Design
 Binary Number
Digits (0 to 1) Radix (r=2)

Number 10110.01

20 2-1
Radix point
24
Decimal Equivalent: 23

N10 = 1 × 24 + 0 × 23 + 1 × 22 + 1 × 21 + 0 × 20 + 0 × 2 −1 + 1 × 2 −2
1
= 16 + 0 + 4 + 2 + 0 + 0 +
4
= 22.25
(10110.01)2 = (22.25)10
7
Digital Design
MSB and LSB of a Binary Number
MSB
◦Most significant bit
LSB
◦Least significant bit

1011001
(Left-most bit) MSB LSB (Right-most bit)

*For integer binary number only

Range
◦ 0 to 2n – 1, where n is the number of bits ( 2n values )
8
Digital Design
 ( 1 1 0 1 . 0 1 1 0 )2
Hexadecimal number ( D . 6 )16
Digits (0 to 15) Hex Dec Bin
Radix (r=16) 0 0 0000

1 1 0001

Number 18F4.2A 2 2 0010

3 3 0011

4 4 0100
16-2
163 2 160 16-1 5 5 0101
16
6 6 0110
Radix point
Decimal Equivalent: 7 7 0111

3 2 1 0 −1 −2 8 8 1000
N10 = 1 × 16 + 8 × 16 + F × 16 + 4 × 16 + 2 × 16 + 10 × 16
9 9 1001
2 10
= 4096 + 2048 + 240 + 4 + + A 10 1010
16 256 B 11 1011

21 C 12 1100
= 6388 +
128 (18F4.2A)16 ≅ (6388.16)10 D 13 1101

≈ 6388.16 E 14 1110

F 15 1111
12
Digital Design
 ( 1 0 1 . 0 1 1 )2
Octal number ( 5 . 3 )8
Radix (r=8) Digits (0 to 7) Oct Dec

0 0

1 1

Number 754.2 (754.2)8 = (520.25)10 2

3
2

4 4

80 8-1 5 5
82 6 6
Decimal Equivalent: Radix point
7 7

N10 = 7 × 82 + 5 × 81 + 4 × 80 + 2 × 8−1 ? 8

? 9
2
= 448 + 40 + 4 + ? 10
8
= 492.25

13
Digital Design
Numbers with Different Radixes:
Summary
Numbers with Different Radixes
Decimal Binary Octal Hexadecimal
(radix 10) (radix 2) (radix 8) (radix 16)

14
Digital Design
 Radix Conversion
Three types of conversions:
o Radix r (r≠10)  Decimal

o Decimal  Radix r (r≠10)

o Conversion among Binary, Octal and Hex numbers

16
Digital Design
 Radix r (r ≠ 10)  Decimal (r = 10)
Binary  Decimal (10110.01)2 = (??)10

(10110.01)2 → 1 × 24 + 0 × 23 + 1 × 22 + 1 × 21 + 0 × 20 + 0 × 2 −1 + 1 × 2 −2 = (22.25)10

Hex  Decimal (18F4.2A)16 = (??)10

(18F 4.2 A)16 = 1 × 163 + 8 × 16 2 + F × 161 + 4 × 160 + 2 × 16 −1 + 10 × 16 −2

≈ (6388.16)10

*Compute the weighted sum of all digits

Ar = (an an −1... ao .a−1... a−m )r
= an × r n + an −1 × r n −1 + ... ao × r 0 + a−1 × r −1 + ... a−m × r −m
n
= ∑a r
i =− m
i
i

17
Digital Design
 Decimal (r = 10)  Radix r (r ≠ 10)
Decimal  Binary (102)10 = (??)2
(102)10 = A2 = ( an an −1... ao .a−1... a− m )r
= an × 2 n + an −1 × 2 n −1 + ... + a1 × 21 + ao (Assume integer)
= ( an × 2 n + an −1 × 2 n −1 + ... + a1 × 21 ) + ao

Integer multiple of 2

(102)10 Continue dividing quotient by 2

→
2
quotient an × 2 n −1 + an −1 × 2 n − 2 + ... + a1 an × 2 n − 2 + an −1 × 2 n −3 + ... + a1
an × 2 n + an −1 × 2 n −1 + ... + a1 × 2 + ao an × 2 n −1 + an −1 × 2 n − 2 + ... + a1
2 2
n n −1
an × 2 + an −1 × 2 + ... + a1 × 2 an × 2 n −1 + an −1 × 2 n − 2 + ...
ao a1
Remainder is a0 Remainder is a1
18
Digital Design
Decimal  Radix r (r ≠ 10) – cont.

Decimal  Binary (102)10 = (??)2

Division Quotient Remainder (102)10 = ( )2

102/2 51  a0
Check:
51/2 25  a1

25/2 12  a2 N10 = a6 × 26 + a5 × 25 + a4 × 2 4 + a3 × 23
12/2 6  a3 + a2 × 2 2 + a1 × 21 + a0 × 20
6/2 3  a4 = 1 × 2 6 + 1 × 25 + 0 × 2 4 + 0 × 23
3/2 1  a5 + 1 × 2 2 + 1 × 21 + 0 × 20
1/2 0  a6 = 64 + 32 + 0 + 0 + 4 + 2 + 0
= 102
Stop when the quotient = 0

19
Digital Design
 How about Fractional Numbers?
Decimal  Binary (0.58)10 = (??)2

(0.58)10 = A2 = (0.a−1a− 2 ... a− m +1a− m )r

= a−1 × 2 −1 + a− 2 × 2 − 2 + ... + a− m +1 × 2 − m +1 + a− m × 2 − m

Multiply by 2:

(0.58)10 × 2 = a−1 + a− 2 × 2 −1 + ... + a− m +1 × 2 − m + 2 + a− m × 2 − m +1

Integer part is a-1 fractional part

21
Digital Design
 How about Fractional Numbers? – cont.
Decimal  Binary (0.58)10 = (??)2

Multiply Product Integer

by 2 Part
0.58x2 1.16  a-1 (0.58)10 = ( )2
0.16x2 0.32  a-2
Check:
0.32x2 0.64  a-3
0.64x2 1.28  a-4 N10 = 1 × 2 −1 + 1 × 2 −4 + 1 × 2 −6
0.28x2 0.56  a-5 1 1 1
= + +
0.56x2 1.12  a-6 2 16 64
= 0.578125
0.12x2 0.24  a-7
≈ 0.58
0.24x2 0.48  a-8

- The conversion process may never end.

- Where to stop depends on the required precision
- The process only ends when fractional part = 0
22
Digital Design
Binary Arithmetic
ADDITION, SUBTRACT, MULTIPLICATION, DIVISION

Page 24
Addition
Addition table:

0+0=0
0+1=1
1 + 1 = 10

“1” is the carry to the next higher bit

Example: Carry
10111 + 110 = 11101
10111
+ 110
---------------
25
Digital Design
 Multiplication
Multiplication table:

0x0=0
0x1=0
1x1=1 Example:
10111 x 110 = 10001010

10111 Multiplicand
x 110 Multiplier
---------------
Multiplication: 00000
 Shift then Add Partial products
10111
 Only need “add” operation
+ 10111
----------------------
10001010 Product

27
Digital Design
 Subtraction
Subtraction table:

0-0=0
1-0=1
1-1=0
0–1=1 with a borrow from the next (higher) bit

Example:
11011 - 110 = 10101 11011
- 110
---------------

28
Digital Design
 Division (shift and subtract)
 Shift then subtraction
Division  Only need “subtract” operation

• Set quotient to 0
100101/101 = ?
• Align leftmost digits in dividend and divisor
• Repeat
111 quotient • If that portion of the dividend above
the divisor is greater than or equal to
101 100101 the divisor
101 • Then subtract divisor from that
portion of the dividend and
1000 • Concatenate 1 to the right hand
101 end of the quotient
• Else concatenate 0 to the right
111 hand end of the quotient
101 • Shift the divisor one place right
• Until dividend is less than the divisor
10 remainder
• quotient is correct, dividend is remainder
• STOP
Check in decimal
30
Digital Design
Arithmetic
•Only addition, subtraction and shifting are needed
for 4 binary arithmetic operations
•Subtraction can be performed by adding a negative
number
•Thus, a computer may only use adders and shifters
to perform all binary arithmetic operations
•This requires an appropriate representation of the
negative binary numbers

 Signed Number Representation

31
Digital Design
Signed Binary numbers
Three ways to represent the signed binary
numbers

◦Signed Magnitude (Sign + magnitude)

◦1’s complement
◦2’s complement

32
Unsigned Binary number

Unsigned binary number (n bits) Example:

Decimal Unsigned
binary
1 1 0 1 … … 1 0
0 000
1 001
Magnitude 2 010
(No sign, always positive) 3 011
4 100
Range of unsigned binary number:
5 101
Max value of a 4-bit number: 6 110
24 23 22 21 20 7 111
1111 = 1 0 0 0 0 – 1  (24)10 -1

Max value of n-bit unsigned number in decimal  2n – 1. Range: 0 ~ (2n-1)

33
Signed Binary – Signed Magnitude (S-M)
Example:
Signed binary number (n bits)
Decimal S-M
3 011
1 0 1 … … 1 0
2 010
1 001
Note:
Magnitude +0 000 Two zeros
-0 100
Sign bit 0 – represents a positive number
-1 101
1 – represents a negative number
-2 110 Negative
MSB is a sign bit numbers
-3 111

“1” in MSB position for all negative numbers

34
 Signed Magnitude – cont.
More examples: 00111010 = +0111010 = (58)10

11100101 = - 1100101 = (-101)10

10000001 = - 0000001 = (-1)10

01111111 = +1111111 = (+127)10

Range of binary number represented by S-M:

For a n-bit Signed binary (S-M), its magnitude is (n-1) bits

Max magnitude: (2n-1-1)10

Range: -(2n-1-1)10 ~ +(2n-1-1)10

35
 Arithmetic
using Binary Numbers (S-M) ?
Computer performs binary arithmetic operations using only
◦ Adders
◦ Multipliers
Subtraction is performed by adding a negative number

Examples of subtraction using S-M binary representation:

3 011 3 011 2 010

- 2 + 110 - 1 + 101 - 1 + 101
------- ------- ------- ------- ------- -------
1 1001 (1)10 2 1000 (0)10 1 111 (-3)10
  
Discarded Discarded
*S-M representation cannot be used for addition of two number with opposite signs
or subtraction when using a simple adder
(dedicated hardware is needed for all possible sign combinations)
36
Complement Representation
Complement representations of a number
◦Radix complements
◦Diminished complements
Definitions:
- Radix Complement
of a n-digit integer number A with radix (r):
A* = rn – A

- Diminished radix complement

of a n-digit integer number A with radix (r):
A* = rn – A - 1

37
 Diminished Radix Complement
A* = rn – A – 1 or A*= (rn – 1) - A
Examples:

Decimal Operation: 1 1 1
888 888 888
A = 237  A* = (100010 – 1) - 23710 - 237 ⟺ + (-237) ⟺ + 762
= 99910 – 23710 651 ______ 650
+1
= 76210 651

Binary number:
A = 0011  A* = (100002 – 1) – 00112 = 11112 – 00112 = 11002

A = 1100  A* = (100002 – 1) – 11002 = 11112 – 11002 = 00112

Shortcut! 
Diminished radix 2 complement
can be found by reversing the bits =)
This is also called 1’s Complement.
38
1’s Complement
“1’s Complement” is the diminished radix complement of
binary numbers
1’s complement of a n-bit number is A* = (2n – 1) - A
1’s complement of a binary number can be obtained by
reversing the bits, i.e. “1”  “0” and “0”  “1”, since
(2n – 1)10 = 1000…000 - 1 = 111…111
n+1 bits n bits

Binary number (n=8): 0101 1100

1’s Complement: 1111 1111 - 0101 1100 = 1010 0011
Reversing the bits

39
1’s Complement representation of
signed binary number
No change for positive numbers and use 1’s complement for negative numbers

1’s Magnitude range: -(2n-1-1) ~ (2n-1-1)

Decimal Complement 3 – 2 = 3 + (-2) = 1 - 3 + 1 = - 3+ 1 = -2
3 011
011 3 100 -3
2 010
+ 101 + (-2) + 001 + ( 1)
1 001 -------- ------- -------- -------
+0 000 (1)000 (0)101
+ 1 + 0
-0
-------- ------- -------- -------
-1 001 +1 101 - 2
-2  -------  -------
-3 * Subtraction can be performed by adding the carry!

Two Zeroes?

40
2’s Complement of a Binary Number
“2’s Complement” is the radix complement of binary
numbers
2’s complement of a n-bit number can be obtained by
adding “1” to its 1’s complement (reversing all the bits), i.e.,
A* = 2n – A
= (2n – A -1) + 1
Binary number (n=8): 01011100

2’s Complement: 10100011 + 1 = 10100100

1’s complement 2’s complement

42
 2’s Complement Arithmetic
No change for positive numbers and use 2’s complement for negative numbers

Decimal 2’s 3 – 2 = 3 + (-2) =1 -3 + 1 = - 3 + 1 = -2

Complement
011 3 101 -3
3 011
+ 110 + (-2) + 001 + ( 1)
2 010 -------- ------- -------- -------
1 001 (1)001 +1 (0)110 - 2
0 000 ------- -------
-1 Carry ignored Carry ignored
-2
-3 - Subtraction can be done!
-4 - Carry is discarded (there is NO NEED to shift
and add the carry, thus more hardware
Only one zero efficient)

Magnitude range: -(2n-1) ~ (2n-1-1)

43
Signed Binary Number (Recap)
Sign+Magnitude
◦ Two zero representations (+/- zeros)
◦ It cannot correctly perform subtraction
◦ Magnitude range: -(2n-1-1) ~ (2n-1-1)
1’s Complement (Diminished radix complement)
◦ Defined as: A* = (2n -1) – A
◦ 1’s complement can be obtained by reversing the bits
◦ Two zero representations (+/- zeros)
◦ It can correctly perform subtraction, but needs to shift and add the carry
◦ Magnitude range: -(2n-1-1) ~ (2n-1-1)
2’s Complement (Radix complement)
◦ Defined as: A* = 2n - A
◦ One zero representation
◦ It can correctly perform subtraction by just ignoring the carry
◦ 2’s complement can be obtained by adding “1” to its 1’s complement
◦ Magnitude range: -(2n-1) ~ (2n-1-1)
Positive numbers are same in all 3 signed binary number representations
45
Introduction to Verilog
Hdl, module, I/Os, wires, reg,
operators

©COPYRIGHT CHUA DINGJUAN. ALL RIGHTS RESERVED.

Background…
An IBM Standard Modular System (SMS)
printed-circuit card from the early-1960s.
This particular card implemented three
simple logic gates. 1980s
Hardware Description
1971 Languages :
VHDL & Verilog

1950s – 1960s
Rapid
1947 Development of
Technology Intel 4-bit
The First Processor
Transistor 2300 Transistors
~ 400 gates
Robert, G. (2013) IBM Standard Modular System [Photograph] Retrieved 1 Dec, 2014, from IEEE Global History Network, Early Popular Computers, 1950 - 1970 http://www.ieeeghn.org/wiki/index.php/File:EPC_-_fig_4.jpg

Digital Design Page 48

 What are HDLs?
Hardware Description Languages (HDLs) are programming
languages for describing digital circuits and systems.
CONCURRENCY STRUCTURE & TIME
time t
A Input / Output ports, multiple bits
B
Z MUX
+
C
D ∆t1 ∆t2
time t + ∆

Today, Verilog and VHDL are the two leading HDLs.

Verilog code is used to describe RTL (Register Transfer Level) designs.
Virtually every chip (FPGA, ASIC, etc.) is designed in part using one of
these two languages.
Xilinx and Altera are the two largest FPGA manufacturers.
(AMD) (Intel)
Digital Design Page 49
Verilog…
Verilog is an IEEE 1364 Standard  link here
Used for Modeling, Simulation and Synthesis of digital circuits.
Focus on synthesizable logic in this module.
Advantages :
◦ Reduces Design Time  Cost
◦ Improves Design Quality
◦ Vendor and Technology Independence
◦ Easy Design Management
Disadvantages :
◦ Cost (Including training you and me!)
◦ Debugging

Digital Design Page 50

 The Module
A piece of hardware with inputs & outputs : module
Module box
Name Port Declaration
module box( input a, b
input [1:0] c,
output [3:0] y );
// Here is where the magic
happens!
endmodule

o Verilog is CasE-SeNSitiVe….
o Module Name : No spaces, No starting with numbers (1box), use meaningful names (box)
o Port Direction : input, output, inout (bidirectional)
o Port Bitwidth : input a,b ; input [1:0] c ; output [3:0] y
By default, signals Input c is a 2-bit vector Output y is a 4-bit vector
are one bit! (little endian) y : y[3] y[2] y[1] y[0]
o

Digital Design Page 51

 Data Types – Net / wire
module box( input a, b box
input [1:0] c,
output [3:0] y ); a 4
tmp
wire tmp; b y
2
assign tmp = a; c

assign y[3:0] = 4’hA;

//We can also write assign y = 4’hA;
//What is the driver? y = 4’hA
___________
_________________ ____________
endmodule
o Input and output ports default to the wire or net type.
o In Verilog, a 1-bit net can take 3 basic values – 0 , 1, Z (high impedance).
o Nets do not store a value, and its value is determined by its driver (just like a wire!)
o If no driver is connected to a net, the value shall be high-impedance Z.
o Nets are connected to drivers via assign statements.
Digital Design Page 52
 Data Types – Variables / reg
module box( input a, b box
input [1:0] c,
a one two
output [3:0] y ); 4
b y
reg [1:0] one = 2’b1_1; 2
three
reg two; c
integer three = 7; 0000 0000
//7 interpreted as decimal 0000 0000
0000 0000
0000 0111
endmodule
o Variables is an abstraction of a data storage element and is of reg type.
o When uninitialized, the value will be X (unknown).
o reg variables can be used to model both combinatorial or sequential logic.
o Assignments to reg are made via procedural assignments (always @ )
o Registers cannot be connected to nets
o integer is a general purpose variable for manipulating quantities and not regarded as
hardware. When the size is undefined, it is by default 32-bit.
Digital Design Page 53
Numerical Values (IEEE Std 1364-2001 p9)
Example 1—Unsized constant numbers
◦ 659 // is a decimal number
◦ ’h 837FF // is a hexadecimal number
◦ ’o7460 // is an octal number
◦ 4af // is illegal (hexadecimal format requires ’h)
Example 2—Sized constant numbers
◦ 4’b1001 // is a 4-bit binary number
◦ 5 ’D 3 // is a 5-bit decimal number
◦ 3’b01x // is a 3-bit number with the least significant bit
unknown
◦ 12’hx // is a 12-bit unknown number
◦ 16’hz // is a 16-bit high-impedance number
Example 3—Using sign with constant numbers
◦ 8 ’d -6 // this is illegal syntax
◦ -8 ’d 6 // this defines the two’s complement of 6, held in 8
bits—equivalent to -(8’d 6)
◦ 4 ’shf // this denotes the 4-bit number ‘1111’, to be
interpreted as a 2’s complement number, or ‘-1’. This is
equivalent to -4’h 1
◦ -4Design
Digital ’sd15 // this is equivalent to -(-4’d 1), or ‘0001’ Page 54
Numerical Values (IEEE Std 1364-2001 p9)
Example 4—Automatic left padding
reg [11:0] a, b, c, d;
initial begin
a = ’h x; // yields xxx
b = ’h 3x; // yields 03x
c = ’h z3; // yields zz3
d = ’h 0z3; // yields 0z3
end
Example 5—Using underscore character in numbers
o 27_195_000
o 16’b0011_0101_0001_1111
o 32 ’h 12ab_f001

Digital Design Page 55

 Useful Operators
Operator Description Examples: a = 4’b1010, b=4’b0000

High !, ~ Logical negation, Bit-wise NOT !a = 0, !b =1, ~a=4’b0101, ~b=4’b1111

&, |, ^ Reduction (Outputs 1-bit) &a = 0, |a=1, ^a = 0
{__,__} Concatenation {b, a} = 8’b00001010
{n{___}} Replication {2 {a} } = 8’b10101010
*, /, %, Multiply, *Divide, *Modulus 3 % 2 = 1, 16 % 4 = 0
Precedence

+, - Binary addition, subtraction a + b = 4’b1010

<< , >> Shift Zeros in Left / Right a << 1 = 4’b0100, a >> 2 = 4’b0010
<, <=, >, >= Logical Relative (1-bit output) (a > b) = 1
==, != Logical Equality (1-bit output) (a == b)= 0 (a != b)= 1
&, ^, | Bit-wise AND, XOR, OR a&b = a|b =
&&, || Logical AND, OR (1-bit output) a&&b = a||b =
Low ?: Conditional Operator <out> = <condition> ? If_ONE : if_ZERO

Digital Design Page 56

 What is happening here?
o Let’s assume that a, b and c are being box
provided these values as shown  a=1
b=0 4
module box( input a, b 2
y
input [1:0] c, c = 2’b10
output [3:0] y );
wire tmp; Net / Variable Number Value in
reg [1:0] one = 3; Name of bits? dec / bin
reg two; a
integer three = 1;
b

assign y[3] = one[0]; c

tmp
assign y[2:1] = a + c; one
two
assign y[0] = ( a > b ) ;
three
endmodule y

Digital Design Page 57

Summary
We have covered :
•Positional number system (radix 10, 2, 8 and 16)
•Conversion among decimal, binary, octal and hex
•Binary arithmetic
•Signed Number Systems
We have covered:
•Introduction to Verilog
•Module, input and output ports (Single Bit and Multi-Bit signals)
•Data Types (wire/net vs reg)
•Numerical values (Hexa/Decimal/Binary/Octal/Integer)
•Addition / Subtraction / Conditional Operators

Digital Design Page 60

EE2026
Digital Design
BOOLEAN ALGEBRA, LOGIC GATES
Chua Dingjuan elechuad@nus.edu.sg
BOOLEAN ALGEBRA
Postulates, Theorems, Laws, AND, OR, NOT, XOR, Minterm,
Maxterm, SOP/POS, CSOP/CPOS
Outline
o What is Boolean Algebra?
o Theorems and Postulates
o Boolean functions and truth table
o Boolean function simplification using algebra manipulation

3
Digital Design
What is Boolean Algebra?
Brief History:
o Boolean was developed in 1854 by George Boole
(An English mathematician, philosopher, and
logician)
o Huntington formulated the postulates in 1904 as
the formal definition
o Boolean Algebra is the mathematical foundation
for digital system design, including computers
o It was first applied to the practical problem
(Analysis of networks of relays) in late 1930s by C.E
Shannon (MIT) who later introduced “Switching
algebra” in 1938
o Switching algebra is a Boolean algebra in which the
number of elements is precisely two

4
Digital Design
 Boolean Algebra
o Boolean algebra is a two-valued type of switching algebra
o Switching algebra represents bistable electrical switching
circuits (On or Off)
o Boolean algebra is defined by a set of elements, B, and there
are two main operators (AND, OR)
o Binary operators (two arguments involved)
o AND  “.”
o OR  “+”
o Plus, one unary operator (only one argument involved)
o NOT  “ � ” (Complement operator represented by an overbar)

o Boolean algebra satisfies six Huntington postulates

5
Digital Design
 Ref - Postulates of Boolean Algebra
There are Six Huntington Postulates that define the Boolean Algebra:
1. Closure - For all elements 𝑥𝑥 and 𝑦𝑦 in the set B
i. 𝑥𝑥 + 𝑦𝑦 𝑖𝑖𝑖𝑖 𝑎𝑎𝑎𝑎 𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒 𝑜𝑜𝑜𝑜 𝑩𝑩 𝑎𝑎𝑎𝑎𝑎𝑎
ii. 𝑥𝑥 � 𝑦𝑦 𝑖𝑖𝑖𝑖 𝑎𝑎𝑎𝑎 𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒 𝑜𝑜𝑜𝑜 𝑩𝑩

2. There exists a 0 and 1 element in B, such that

i. 𝑥𝑥 + 0 = 𝑥𝑥
ii. x� 1 = 𝑥𝑥

3. Commutative Law
i. x+𝑦𝑦 = 𝑦𝑦 + 𝑥𝑥
ii. x� 𝑦𝑦 = 𝑦𝑦 � 𝑥𝑥

4. Distributive Law
i. 𝑥𝑥 � 𝑦𝑦 + 𝑧𝑧 = 𝑥𝑥 � 𝑦𝑦 + 𝑥𝑥 � 𝑧𝑧 (� 𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜 +)
ii. 𝑥𝑥 + 𝑦𝑦 � 𝑧𝑧 = (𝑥𝑥 + 𝑦𝑦) � (𝑥𝑥 + 𝑧𝑧) (+ 𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜 �)

5. For every element 𝑥𝑥 in the set B, there exists an element 𝑥𝑥̅ in the set B, such that
i. 𝑥𝑥 + 𝑥𝑥̅ = 1
ii. 𝑥𝑥 � 𝑥𝑥̅ = 0
(𝑥𝑥 is called the complement of 𝑥𝑥)

6. There exist at least two distinct elements in the set B

6
Digital Design
 Ref - Boolean vs. Ordinary Algebra

Boolean algebra Ordinary algebra

No associative law. But it can be derived from Associative law is included:
the other postulates 𝑎𝑎 + 𝑏𝑏 + 𝑐𝑐 = 𝑎𝑎 + 𝑏𝑏 + 𝑐𝑐
Distributive law:
x + 𝑦𝑦 � 𝑧𝑧 = (𝑥𝑥 + 𝑦𝑦) � (𝑥𝑥 + 𝑧𝑧) valid Not valid
No additive or multiplicative inverses,
therefore there are no subtraction and
division operation Subtraction and division operations exist

Complement operation available No complement operation

Boolean algebra: Undefined set of elements;
Switching algebra: a two-valued Boolean
algebra, whose element set only has two Dealing with real numbers and constituting an
elements, 0 and 1. infinite set of elements

7
Digital Design
 The Three Operators in Two-
Valued Boolean Algebra (B={0,1})
OR: 𝑨𝑨 + 𝑩𝑩 AND: 𝑨𝑨 � 𝑩𝑩 NOT: 𝑨𝑨
𝑨𝑨 𝑩𝑩 𝑨𝑨 + 𝑩𝑩 𝑨𝑨 𝑩𝑩 𝑨𝑨 � 𝑩𝑩 𝑨𝑨 𝑨𝑨

0 0 0 0 0 0 0 1

0 1 1 0 1 0 1 0

1 0 1 1 0 0

1 1 1 1 1 1 A = 0 → 𝐴𝐴 = 1
A = 1 → 𝐴𝐴 = 0
0 + 0 = 0 0 � 0 = 0
0 + 1 = 1 0 � 1 = 0
1 + 0 = 1 1 � 0 = 0
1 + 1 = 1 1 � 1 = 1

Priority: NOT has highest precedence, followed by AND and OR

NOT(A ⋅ B + C) = NOT((A ⋅ B) + C)
8
Digital Design
 Theorems of Boolean Algebra
# Theorem

1 𝐴𝐴 + 𝐴𝐴 = 𝐴𝐴 𝐴𝐴 � 𝐴𝐴 = 𝐴𝐴 Tautology Law

2 𝐴𝐴 + 1 = 1 𝐴𝐴 � 0 = 0 Union Law

3 𝐴𝐴� = 𝐴𝐴 Involution Law

4 𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶 𝐴𝐴 � 𝐵𝐵 � 𝐶𝐶 = 𝐴𝐴 � 𝐵𝐵 � 𝐶𝐶 Associative Law
= 𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶
5 𝐴𝐴 + 𝐵𝐵 = 𝐴𝐴̅ � 𝐵𝐵� 𝐴𝐴 � 𝐵𝐵 = 𝐴𝐴̅ + 𝐵𝐵� De Morgan’s Law

6 𝐴𝐴 + 𝐴𝐴 � 𝐵𝐵 = 𝐴𝐴 𝐴𝐴 � 𝐴𝐴 + 𝐵𝐵 = 𝐴𝐴 Absorption Law

7 𝐴𝐴 + 𝐴𝐴̅ � 𝐵𝐵 = 𝐴𝐴 + 𝐵𝐵 𝐴𝐴 � 𝐴𝐴̅ + 𝐵𝐵 = 𝐴𝐴 � 𝐵𝐵

8 𝐴𝐴𝐴𝐴 + 𝐴𝐴𝐵𝐵� = 𝐴𝐴 � = 𝐴𝐴
(𝐴𝐴 + 𝐵𝐵)(𝐴𝐴 + 𝐵𝐵) Logical adjacency

9 ̅ + 𝐵𝐵𝐵𝐵
𝐴𝐴𝐴𝐴 + 𝐴𝐴𝐶𝐶 𝐴𝐴 + 𝐵𝐵 𝐴𝐴̅ + 𝐶𝐶 𝐵𝐵 + 𝐶𝐶 Consensus Law
̅
= 𝐴𝐴𝐴𝐴 + 𝐴𝐴𝐶𝐶 = (𝐴𝐴 + 𝐵𝐵)(𝐴𝐴̅ + 𝐶𝐶)

Duality (OR and AND, 0 and 1 can be interchanged)

9
Digital Design
 Boolean Functions and Truth Table
•A Boolean function expresses the logical relationship between binary variables.
•It can be evaluated by determining the binary value of the expression for all
possible values of the variables
Truth table is a tabular technique for listing all 𝑭𝑭𝟑𝟑 = 𝑨𝑨 + 𝑩𝑩𝑩𝑩
possible combinations of input variables and A B C F3
the values of function for each combination
0 0 0 0
𝑭𝑭𝟏𝟏 = 𝑨𝑨 + 𝑩𝑩
0 0 1 0
A B F1 0 1 0 0
0 0 0 0 1 1 1
0 1 1 1 0 0 1
1 0 1 1 0 1 1
1 1 1 1 1 0 1

1 1 1 1

10
Digital Design
 Examples - Truth Table
# Theorem

5 𝐴𝐴 + 𝐵𝐵 = 𝐴𝐴̅ � 𝐵𝐵� 𝐴𝐴 � 𝐵𝐵 = 𝐴𝐴̅ + 𝐵𝐵� De Morgan’s Law

Prove the De Morgan’s Law:

𝐴𝐴 + 𝐵𝐵 = 𝐴𝐴̅ � 𝐵𝐵� 𝐴𝐴 � 𝐵𝐵 = 𝐴𝐴̅ + 𝐵𝐵�
A B 𝑨𝑨 + 𝑩𝑩 � � 𝑩𝑩
𝑨𝑨 � A B 𝑨𝑨 � 𝑩𝑩 � + 𝑩𝑩
𝑨𝑨 �
0 0 1 1 0 0 1 1
0 1 0 0 0 1 1 1
1 0 0 0 1 0 1 1
1 1 0 0 1 1 0 0

Try this yourself!

11
Digital Design
 Examples - Truth Table vs Algebra
# Theorem

6 𝐴𝐴 + 𝐴𝐴 � 𝐵𝐵 = 𝐴𝐴 𝐴𝐴 � 𝐴𝐴 + 𝐵𝐵 = 𝐴𝐴 Absorption Law

𝐴𝐴 � 𝐴𝐴 + 𝐵𝐵 = 𝐴𝐴
𝐴𝐴. 𝐴𝐴 + 𝐴𝐴. 𝐵𝐵 = 𝐴𝐴 + 𝐴𝐴. 𝐵𝐵 = 𝐴𝐴 𝐵𝐵 + 1 = 𝐴𝐴

𝐴𝐴 � 𝐴𝐴 + 𝐵𝐵 = 𝐴𝐴
A B 𝑨𝑨 � 𝑨𝑨 + 𝑩𝑩 𝑨𝑨
0 0 0 0
0 1 0 0
1 0 1 1
1 1 1 1

12
Digital Design
 Examples - Truth Table
Prove the De Morgan’s Law:
𝐴𝐴 + 𝐵𝐵 = 𝐴𝐴̅ � 𝐵𝐵� 𝐴𝐴 � 𝐵𝐵 = 𝐴𝐴̅ + 𝐵𝐵�
A B 𝑨𝑨 + 𝑩𝑩 � � 𝑩𝑩
𝑨𝑨 � A B 𝑨𝑨 � 𝑩𝑩 � + 𝑩𝑩
𝑨𝑨 �
0 0 1 1 0 0 1 1
0 1 0 0 0 1 1 1
1 0 0 0 1 0 1 1
1 1 0 0 1 1 0 0

Prove : 𝐴𝐴 + 𝐴𝐴̅ � 𝐵𝐵 = 𝐴𝐴 + 𝐵𝐵 𝐴𝐴 � 𝐴𝐴 + 𝐵𝐵 = 𝐴𝐴
A B � � 𝑩𝑩
𝑨𝑨 + 𝑨𝑨 𝑨𝑨 + 𝑩𝑩 A B 𝑨𝑨 � 𝑨𝑨 + 𝑩𝑩 𝑨𝑨
0 0 0 0 0 0 0 0
0 1 1 1 0 1 0 0
1 0 1 1 1 0 1 1

1 1 1 1 1 1 1 1

13
Digital Design
 Truth Table – examples (cont.)
Prove : 𝐴𝐴 + 𝐵𝐵 � 𝐶𝐶 = (𝐴𝐴 + 𝐵𝐵) � (𝐴𝐴 + 𝐶𝐶)

𝑨𝑨 𝑩𝑩 𝑪𝑪 𝑨𝑨 + 𝑩𝑩 � 𝑪𝑪 (𝑨𝑨 + 𝑩𝑩) � (𝑨𝑨 + 𝑪𝑪)

0 0 0 0 0
0 0 1 0 0
0 1 0 0 0
0 1 1 1 1
1 0 0 1 1
1 0 1 1 1
1 1 0 1 1
1 1 1 1 1

14
Digital Design
But how do we
use these ideas?

Page 15
Design Example
Ben Bitdiddle is having a picnic. He won’t enjoy it if it
rains or if there are ants. Design a circuit that will output
TRUE only if Ben enjoys the picnic.

Solution
Inputs : A (Ants), B (Rain)
Output : E (Ben’s Enjoyment)

Boolean Algebra Version Truth Table Version

E=? A B 𝑬𝑬
Ben enjoys his picnic if there 0 0 1
is no rain and no ants : 0 1 0
1 0 0
E = 1 if A = 0 and B = 0
1 1 0

E = 𝐴𝐴̅ � 𝐵𝐵� E=?

Digital Design Page 16
 Minterm and Maxterm
A B E Minterm Maxterm
0 0 1 𝐴𝐴̅ � 𝐵𝐵� 𝐴𝐴 + 𝐵𝐵
0 1 0 𝐴𝐴̅ � 𝐵𝐵 𝐴𝐴 + 𝐵𝐵�
1 0 0 𝐴𝐴 � 𝐵𝐵� 𝐴𝐴̅ + 𝐵𝐵
1 1 0 𝐴𝐴 � 𝐵𝐵 𝐴𝐴̅ + 𝐵𝐵�

minterm A. B = 1 for maxterm 𝐴𝐴̅ + 𝐵𝐵� = 0

A = 1 and B = 1 for A = 1 and B = 1

Minterm Maxterm
◦ Minterm is a product term that contains all – Maxterm is a sum term that contains all
variables in the function variables in the function
◦ AND all the variables – OR all the variables
◦ If the variable in truth table is “0”, take its
complement in the minterm – If the variable in truth table is “1”, take its
◦ Minterm is equal to 1 for that set of given complement in the maxterm
input – Maxterm is equal to 0 for that set of given
input
17
Digital Design
 Truth Table  CSOP or CPOS
A Boolean function is in canonical form if it is expressed as
◦ a sum of minterms (Canonical Sum Of Products - CSOP) or
◦ a product of maxterms (Canonical Product Of Sums - CPOS)

Using Ben’s Bitdiddle’s truth table :

• CSOP  sum the minterms that make
A B E minterm maxterm output = 1
0 0 1 𝐴𝐴̅ � 𝐵𝐵� 𝐴𝐴 + 𝐵𝐵
𝑬𝑬𝟏𝟏 𝑨𝑨, 𝑩𝑩 = 𝐴𝐴̅ � 𝐵𝐵�
0 1 0 𝐴𝐴̅ � 𝐵𝐵 𝐴𝐴 + 𝐵𝐵�
1 0 0 𝐴𝐴 � 𝐵𝐵� 𝐴𝐴̅ + 𝐵𝐵 • CPOS  product the maxterms that make
output = 0
1 1 0 𝐴𝐴 � 𝐵𝐵 𝐴𝐴̅ + 𝐵𝐵�
𝑬𝑬𝟐𝟐 𝑨𝑨, 𝑩𝑩 = 𝐴𝐴 + 𝐵𝐵� . 𝐴𝐴̅ + 𝐵𝐵 . 𝐴𝐴̅ + 𝐵𝐵�
A truth table expressed in either CSOP
or CPOS. (How should we choose?)
Are the above two functions equivalent?
How do we check?

18
Digital Design
 SOP and POS  Truth Table
Are the following two Boolean functions same?
𝑬𝑬𝟏𝟏 𝑨𝑨, 𝑩𝑩 = 𝐴𝐴̅ � 𝐵𝐵�
𝑬𝑬𝟐𝟐 𝑨𝑨, 𝑩𝑩 = 𝐴𝐴 + 𝐵𝐵� . 𝐴𝐴̅ + 𝐵𝐵 . 𝐴𝐴̅ + 𝐵𝐵�
Let’s use truth tables to check:

𝑬𝑬𝟏𝟏 𝑨𝑨, 𝑩𝑩 = 𝐴𝐴̅ � 𝐵𝐵� 𝑬𝑬𝟐𝟐 𝑨𝑨, 𝑩𝑩 = 𝐴𝐴 + 𝐵𝐵� . 𝐴𝐴̅ + 𝐵𝐵 . 𝐴𝐴̅ + 𝐵𝐵�
A B E1 A B E2
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 0 1 1 0

SOP: If any PRODUCT in SOP is “1”, the function is “1”. Otherwise, the function is “0”
POS: If any SUM in POS is “0”, the function is “0”. Otherwise, the function is “1”
SOP and POS are different ways to present the same Boolean function
19
Digital Design
 SOP and POS  Truth Table
Are the following two Boolean functions same?
𝑬𝑬𝟏𝟏 𝑨𝑨, 𝑩𝑩 = 𝐴𝐴̅ � 𝐵𝐵�
𝑬𝑬𝟐𝟐 𝑨𝑨, 𝑩𝑩 = 𝐴𝐴 + 𝐵𝐵� . 𝐴𝐴̅ + 𝐵𝐵 . 𝐴𝐴̅ + 𝐵𝐵�
Can we also prove this via Boolean algebra?

𝑬𝑬𝟏𝟏 𝑨𝑨, 𝑩𝑩 = 𝐴𝐴̅ � 𝐵𝐵� 𝑬𝑬𝟐𝟐 𝑨𝑨, 𝑩𝑩 = 𝐴𝐴 + 𝐵𝐵� . 𝐴𝐴̅ + 𝐵𝐵 . 𝐴𝐴̅ + 𝐵𝐵�

= 𝐴𝐴𝐴𝐴̅ + 𝐴𝐴𝐴𝐴 + 𝐴𝐴̅𝐵𝐵� + 𝐵𝐵𝐵𝐵� . 𝐴𝐴̅ + 𝐵𝐵�

= 𝐴𝐴𝐴𝐴 + 𝐴𝐴̅𝐵𝐵� . 𝐴𝐴̅ + 𝐵𝐵�

̅ + 𝐴𝐴𝐴𝐴 𝐵𝐵� + 𝐴𝐴̅𝐵𝐵� 𝐴𝐴̅ + 𝐴𝐴̅𝐵𝐵� 𝐵𝐵�

= 𝐴𝐴𝐴𝐴𝐵𝐵

= 𝐴𝐴̅𝐵𝐵� + 𝐴𝐴̅𝐵𝐵� = 𝐴𝐴̅𝐵𝐵�

20
Digital Design
 Example-2: Non-Canonical  Canonical
Form via Truth Table
Example: For the given Boolean function below, find a canonical minterm and
maxterm expression.
1) obtain the truth table from the given function
2) find minterm or maxterm expression from truth table (CSOP or CPOS)
𝐹𝐹 𝑥𝑥, 𝑦𝑦, 𝑧𝑧 = 𝑥𝑥̅ + 𝑦𝑦𝑧𝑧̅ Non Canonical form

Truth table:
x y z F Canonical minterm expression:
0 0 0 1
𝐹𝐹 𝑥𝑥, 𝑦𝑦, 𝑧𝑧 = 𝑥𝑥̅ 𝑦𝑦� 𝑧𝑧̅ + 𝑥𝑥̅ 𝑦𝑦𝑧𝑧
� + 𝑥𝑥𝑦𝑦
̅ 𝑧𝑧̅ + 𝑥𝑥𝑦𝑦𝑧𝑧
̅ + 𝑥𝑥𝑥𝑥𝑧𝑧̅
0 0 1 1
0 1 0 1 (only contains the minterms that make the function = 1)
0 1 1 1
Canonical maxterm expression:
1 0 0 0
1 0 1 0 𝐹𝐹 𝑥𝑥, 𝑦𝑦, 𝑧𝑧 = 𝑥𝑥̅ + 𝑦𝑦 + 𝑧𝑧 𝑥𝑥̅ + 𝑦𝑦 + 𝑧𝑧̅ (𝑥𝑥̅ + 𝑦𝑦� + 𝑧𝑧)̅
1 1 0 1 (only contains the maxterms that make the function = 0)
1 1 1 0
21
Digital Design
 Example-3: Non-Canonical  Canonical
Form via Postulates and Theorems
Example: For the given Boolean functions below, convert it to canonical minterm or
maxterm expression.
(*Using postulates/theorem to expand the given function to canonical form)

SOP  CSOP: 𝐹𝐹 𝑥𝑥, 𝑦𝑦, 𝑧𝑧 = 𝑥𝑥𝑦𝑦 ̅ + 𝑥𝑥𝑥𝑥 For missing literals, complete
(CSOP – Canonical SOP) minterms through postulates:
= 𝑥𝑥𝑦𝑦
̅ � 1 + 𝑥𝑥 � 1 � 𝑧𝑧
= 𝑥𝑥𝑦𝑦̅ z + 𝑧𝑧̅ + 𝑥𝑥 𝑦𝑦 + 𝑦𝑦� 𝑧𝑧 A � 1 = 𝐴𝐴 𝑎𝑎𝑎𝑎𝑎𝑎 𝐴𝐴 + 𝐴𝐴̅ =
= 𝑥𝑥𝑦𝑦𝑧𝑧
̅ + 𝑥𝑥𝑦𝑦 ̅ 𝑧𝑧̅ + 𝑥𝑥𝑥𝑥𝑥𝑥 + 𝑥𝑥 𝑦𝑦𝑧𝑧
� 1
1) express SOP as POS
1) a) complement twice
SOP  CPOS: 𝐹𝐹 𝑥𝑥, 𝑦𝑦, 𝑧𝑧 = 𝑥𝑥𝑦𝑦
̅ + 𝑥𝑥𝑥𝑥 b) apply De Morgan’s law
(CSOP – Canonical POS)
̅ + 𝑥𝑥𝑥𝑥 a
= 𝑥𝑥𝑦𝑦 c) expand
d) re-apply De Morgan’s law
Use distribution postulate: = 𝑥𝑥 + 𝑦𝑦� 𝑥𝑥̅ + 𝑧𝑧̅ b 2) for missing literals, complete
𝐴𝐴 + 𝑩𝑩𝑪𝑪 = 𝐴𝐴 + 𝑩𝑩 𝐴𝐴 + 𝑪𝑪 maxterms through distribution
(A = incomplete sum,
= 𝑥𝑥 𝑥𝑥̅ + 𝑥𝑥 𝑧𝑧̅ + 𝑥𝑥̅ 𝑦𝑦� + 𝑦𝑦� 𝑧𝑧̅ c
postulate
C=NOT(B)=missing literal) = 𝑥𝑥 + 𝑦𝑦 𝑥𝑥̅ + 𝑧𝑧 𝑦𝑦 + 𝑧𝑧 d
x+𝑦𝑦 = (𝑥𝑥 + 𝑦𝑦) + 𝒛𝒛�𝒛𝒛 2) = 𝑥𝑥 + 𝑦𝑦 + 𝑧𝑧 ⋅ 𝑥𝑥 + 𝑦𝑦 + 𝑧𝑧̅ ⋅ 𝑥𝑥̅ + 𝑦𝑦 + 𝑧𝑧 ⋅ 𝑥𝑥̅ + 𝑦𝑦� + 𝑧𝑧
= (𝑥𝑥 + 𝑦𝑦 + 𝒛𝒛)(𝑥𝑥 + 𝑦𝑦 + 𝒛𝒛� ) ⋅ 𝑥𝑥 + 𝑦𝑦 + 𝑧𝑧 ⋅ 𝑥𝑥̅ + 𝑦𝑦 + 𝑧𝑧

22
Digital Design
 Example-3 : SOP ⇔ POS (De Morgan’s)
Truth table: Applying De Morgan’s Law to CSOP of 𝑭𝑭𝟏𝟏 :
𝐴𝐴 𝐵𝐵 𝐶𝐶 𝐹𝐹1 𝐹𝐹𝟏𝟏
𝑭𝑭𝟏𝟏 = 𝑭𝑭𝟏𝟏 = 𝑭𝑭𝟏𝟏,𝑪𝑪𝑪𝑪𝑪𝑪𝑪𝑪
0 0 0 0 1
= 𝑨𝑨� 𝑩𝑩 � + 𝑨𝑨
� 𝑪𝑪 � 𝑩𝑩
� 𝑪𝑪 + 𝑨𝑨� 𝑩𝑩𝑩𝑩 + 𝑨𝑨𝑨𝑨𝑨𝑨
0 0 1 0 1 � 𝑩𝑩 � � 𝑨𝑨
� 𝑪𝑪 � 𝑩𝑩
� 𝑪𝑪 � 𝑨𝑨
� 𝑩𝑩𝑩𝑩 � 𝑨𝑨𝑨𝑨𝑨𝑨
= 𝑨𝑨
0 1 0 1 0 = 𝑨𝑨 + 𝑩𝑩 + 𝑪𝑪 𝑨𝑨 + 𝑩𝑩 + 𝑪𝑪 � 𝑨𝑨 + 𝑩𝑩 � (𝑨𝑨
� + 𝑪𝑪 � + 𝑩𝑩 �
� + 𝑪𝑪)
0 1 1 0 1

1 0 0 1 0
Now, find CPOS of F1 directly from truth table:
1 0 1 1 0 clearly the
1 1 0 1 0 𝑭𝑭𝟏𝟏 𝑨𝑨, 𝑩𝑩, 𝑪𝑪 CPOS of F1 same
� 𝑨𝑨 + 𝑩𝑩
= 𝑨𝑨 + 𝑩𝑩 + 𝑪𝑪 𝑨𝑨 + 𝑩𝑩 + 𝑪𝑪 � (𝑨𝑨
� + 𝑪𝑪 � + 𝑩𝑩 �
� + 𝑪𝑪)
1 1 1 0 1
CPOS can be obtained from CSOP (and vice versa) by
applying De Morgan’s Law!

31
Digital Design
Pre-Lab Exercise
The following task is required to be implemented :
oWhen switch A turns on, only LED1 lights up.
oWhen switch B turns on, only LED2 lights up.
oWhen both switches A and B turn on, LED1, LED2, and LED3 light up.

0 0 0
0 1 0
1 0 0
1 1 1

LED1 = 𝐴𝐴𝐵𝐵� + 𝐴𝐴𝐴𝐴

̅ + 𝐴𝐴𝐴𝐴
LED2 = 𝐴𝐴𝐵𝐵
LED3 = 𝐴𝐴𝐴𝐴

Digital Design Page 24

Pre-Lab Exercise
Modify your boolean expressions for LED1, LED2 and LED3 to incorporate an
additional switch C. (“PRACTICE TASK FOR LAB 1”)
o If switch C is in the OFF state, it forces all the three LEDs to be in the OFF
state.
o If the switch C is in the ON state, the design behaves exactly as described
previously.

LED1 = (𝐴𝐴𝐵𝐵� + 𝐴𝐴𝐴𝐴)

̅ + 𝐴𝐴𝐴𝐴)
LED2 = (𝐴𝐴𝐵𝐵

LED3 = (𝐴𝐴𝐴𝐴)

Digital Design Page 25

 Summary
oPostulates and theorems of Boolean algebra
oThree binary operators: AND, OR and NOT
oBoolean Functions
oTruth table and Boolean function evaluation using truth table
oBoolean function in SOP or POS form
oObtain SOP or POS from truth table
oMinterm and maxterm
oCanonical form of Boolean function
oConvert non-canonical form to canonical SOP or POS expressions.

26
Digital Design
Guidelines for Simplification of
Boolean Function (in SOP)
Three most used theorems:
(1) 𝐴𝐴𝐴𝐴 + 𝐴𝐴𝐵𝐵� = 𝐴𝐴 (Logical adjacency)
(2) 𝐴𝐴 + 𝐴𝐴̅ � 𝐵𝐵 = 𝐴𝐴 + 𝐵𝐵
(3) 𝐴𝐴𝐴𝐴 + 𝐴𝐴𝐶𝐶̅ + 𝐵𝐵𝐵𝐵 = 𝐴𝐴𝐴𝐴 + 𝐴𝐴𝐶𝐶
̅ (Consensus)

Apply (1) until it cannot be applied further

Apply (2) until it cannot be applied further
Go back to (1) and then (2) until they can no longer be applied
Apply (3) until it cannot be applied further
Go back to (1), (2) and then (3) until none of them can be applied
It can then be assumed that the function is simplified
Empirical: the result is usually close to minimal, but may not be the minimal
Cumbersome: other methods are much easier and quicker

27
Digital Design
LOGIC GATES
AND, OR, NOT, XOR gates

©COPYRIGHT CHUA DINGJUAN. ALL RIGHTS RESERVED.

Outline
Logic gate introduction
◦AND/NAND, OR/NOR, NOT/Buffer, XOR/NXOR
◦different levels of description (Boolean, truth table,
graphical, Verilog)
Implementation of Boolean function using gates
◦different levels of description (Boolean, graphical, Verilog)
Design simplification by algebra manipulation
Commercial logic gates

29
Digital Design
 Logic Gate Introduction
Logic gates are digital circuits that implement the Boolean
operations.
Basic Logic Gates:
Gate Symbol Function Verilog Gate Symbol Function Verilog
(F) Operator (F) Operator
A
AND A F 𝐴𝐴 � 𝐵𝐵 F=A&B NAND F 𝐴𝐴 � 𝐵𝐵 F = ~(A & B)
B B

OR A 𝐴𝐴 + 𝐵𝐵 F=A|B NOR A 𝐴𝐴 + 𝐵𝐵 F = ~(A | B)

F F
B B

NOT 𝐴𝐴̅ F = ~A Buffer 𝐴𝐴 F=A

XOR 𝐴𝐴 ⊕ 𝐵𝐵 F=A^B XNOR A 𝐴𝐴 ⊕ 𝐵𝐵 F = ~(A ^ B)

F
B

Verilog Bit-wise Operator Precedence : ~, &, ^, |

30
Digital Design
 AND and NAND Gates
A Truth Table (AND, NAND):
F 𝑭𝑭 = 𝑨𝑨 � 𝑩𝑩
B AND NAND
A B 𝑨𝑨 � 𝑩𝑩 𝑨𝑨 � 𝑩𝑩
A
F 𝑭𝑭 = 𝑨𝑨 � 𝑩𝑩 0 0 0 1
B
1 0 0 1
A
F 0 1 0 1
B
1 1 1 0
bubble = complement
AND NAND
F is TRUE only when both A and B are • F is FALSE only if both A and
TRUE B are TRUE

module andgate(A, B, F); module nandgate(A, B, F);

input A, B; input A, B;
output F; output F;
assign F = A & B; assign F = ~( A & B );
endmodule endmodule
31
Digital Design
 OR and NOR Gates
A Truth Table (OR, NOR):
F 𝑭𝑭 = 𝑨𝑨 + 𝑩𝑩
B OR NOR
A B 𝑨𝑨 + 𝑩𝑩 𝑨𝑨 + 𝑩𝑩
A
F 𝑭𝑭 = 𝑨𝑨 + 𝑩𝑩 0 0 0 1
B
1 0 1 0
A 0 1 1 0
F
B
1 1 1 0

OR NOR
• F is FALSE only when both A and B • F is TRUE only if both A and
are FALSE B are FALSE

module orgate(A, B, F); module norgate(A, B, F);

input A, B; input A, B;
output F; output F;
assign F = A | B; assign F = ~( A | B);
endmodule endmodule
32
Digital Design
 XOR and XNOR Gates
Truth Table (XOR, XNOR):
𝑭𝑭 = 𝑨𝑨𝑩𝑩 + 𝑨𝑨𝑩𝑩 = 𝑨𝑨 ⊕ 𝑩𝑩
XOR XNOR
A B 𝑨𝑨 ⊕ 𝑩𝑩 𝑨𝑨 ⊕ 𝑩𝑩
A
F 𝑭𝑭 = 𝑨𝑨 ⊕ 𝑩𝑩 0 0 0 1
B
1 0 1 0
0 1 1 0
A
F
B 1 1 0 1

XOR XNOR
• F is TRUE if A ≠ B • F is TRUE if A = B

module xorgate(A, B, F); module xnorgate(A, B, F);

input A, B; input A, B;
output F; output F;
assign F = A ^ B; assign F = ~(A ^ B);
endmodule endmodule
33
Digital Design
 Cont’d Ben Bitdiddle’s Example
We developed the following two Boolean expressions for Ben :
𝑬𝑬 𝑨𝑨, 𝑩𝑩 = 𝐴𝐴̅ � 𝐵𝐵�
𝑬𝑬 𝑨𝑨, 𝑩𝑩 = 𝐴𝐴 + 𝐵𝐵� . 𝐴𝐴̅ + 𝐵𝐵 . 𝐴𝐴̅ + 𝐵𝐵�
How do we implement them?

𝑬𝑬𝟏𝟏 𝑨𝑨, 𝑩𝑩 = 𝐴𝐴̅ � 𝐵𝐵� 𝑬𝑬𝟐𝟐 𝑨𝑨, 𝑩𝑩 = 𝐴𝐴 + 𝐵𝐵� . 𝐴𝐴̅ + 𝐵𝐵 . 𝐴𝐴̅ + 𝐵𝐵�
# of Gates needed = 3 # of Gates needed = 6
𝐴𝐴
𝐴𝐴 𝐵𝐵
𝐸𝐸1
𝐵𝐵
𝐸𝐸2

34
Digital Design
 Implementation using Logic Gates –
Sketch Method
- Implement the following Boolean functions to logic gates, assume that
the maximum number of inputs of a gate is 4.
𝐹𝐹 𝑤𝑤, 𝑥𝑥, 𝑦𝑦, 𝑧𝑧 = 𝑤𝑤
� 𝑥𝑥𝑧𝑧
̅ + 𝑤𝑤𝑥𝑥𝑥𝑥
� + 𝑤𝑤𝑤𝑤𝑤𝑤 + 𝑥𝑥𝑥𝑥𝑥𝑥
𝑤𝑤 𝑥𝑥 𝑦𝑦 𝑧𝑧
𝑤𝑤
� 𝑥𝑥̅
Input signals needed?
𝑤𝑤, 𝑤𝑤,
� 𝑥𝑥, 𝑥𝑥,̅ 𝑦𝑦, 𝑧𝑧

Types / # of Gates
needed?
AND – 3 inputs
OR – 4 inputs

Schematic drawn in
PLA configuration
# of gates = 7

assign F = ~w & ~x & z | ~w & x & z | w & y & z | x & y & z;

Digital Design
35
 Implementation of Boolean
Function using Logic Gates
- Implement the following Boolean functions to logic gates, assume that
the maximum number of inputs of a gate is 4.
𝐹𝐹 𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑 = 𝑎𝑎𝑎𝑎𝑐𝑐̅ + 𝑎𝑎𝑎𝑎𝑎𝑎 + 𝑏𝑏𝑏𝑏𝑏𝑏 + 𝑎𝑎𝑐𝑐𝑐𝑐 �
� + 𝑎𝑎𝑏𝑏𝑐𝑐𝑑𝑑

10
gate count = ____

module func(a,b,c,d,F);
input a, b, c, d;
output F;
assign F = a & b & ~c | a & b & c | b & c & d | ~a & c & d | a & ~b & ~c & d;
endmodule
51
Digital Design
Boolean Function Simplification using
Algebra Manipulation

•To reduce the hardware cost, the Boolean function

can be simplified before implemented using logic
gates
•A simplified Boolean Function contains a minimal
number of terms such that no other expression with
fewer literals and terms will represent the original
function
•Simplification can be done by
•Algebraic manipulation using postulates and theorem
•Karnaugh Map  Next Topic!

37
Digital Design
 Ex - Boolean Function Simplification
(Relook at the second example):

𝐹𝐹 𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑 = 𝑎𝑎𝑎𝑎𝑐𝑐̅ + 𝑎𝑎𝑎𝑎𝑎𝑎 + 𝑏𝑏𝑏𝑏𝑏𝑏 + 𝑎𝑎𝑐𝑐𝑐𝑐 �

� + 𝑎𝑎𝑏𝑏𝑐𝑐𝑑𝑑
= 𝑎𝑎𝑎𝑎 𝑐𝑐̅ + 𝑐𝑐 + 𝑏𝑏𝑏𝑏𝑏𝑏 + 𝑎𝑎𝑐𝑐𝑐𝑐
� + 𝑎𝑎𝑏𝑏𝑐𝑐𝑑𝑑 � (𝐴𝐴 + 𝐴𝐴̅ = 1)
= 𝑎𝑎 𝑏𝑏 + 𝑏𝑏� 𝑐𝑐𝑑𝑑 ̅ + 𝑏𝑏𝑏𝑏𝑏𝑏 + 𝑎𝑎𝑐𝑐𝑐𝑐
� (𝐴𝐴 + 𝐴𝐴̅ � 𝐵𝐵 = 𝐴𝐴 + 𝐵𝐵)
= 𝑎𝑎 𝑏𝑏 + 𝑐𝑐𝑑𝑑 ̅ + 𝑏𝑏𝑏𝑏𝑏𝑏 + 𝑎𝑎𝑐𝑐𝑐𝑐
�
= 𝑎𝑎𝑏𝑏 + 𝑎𝑎� 𝑐𝑐𝑐𝑐 + 𝑏𝑏 𝑐𝑐𝑐𝑐 + 𝑎𝑎𝑐𝑐𝑑𝑑 ̅ (𝐴𝐴𝐵𝐵 + 𝐴𝐴𝐶𝐶̅ + 𝐵𝐵𝐶𝐶 = 𝐴𝐴𝐴𝐴 + 𝐴𝐴𝐶𝐶)
̅ - consensus
= 𝑎𝑎𝑎𝑎 + 𝑎𝑎𝑐𝑐𝑐𝑐
� + 𝑎𝑎𝑐𝑐𝑑𝑑 ̅

Before simplification: After simplification:

gate count = 6
gate count = 11 (45.5% reduction!)
38
Digital Design
Ex - Boolean Function Simplification

𝐹𝐹 𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑 = 𝑎𝑎� 𝑏𝑏� 𝑐𝑐̅ + 𝑎𝑎𝑏𝑏

� 𝑐𝑐̅𝑑𝑑̅ + 𝑎𝑎𝑏𝑏
� 𝑐𝑐𝑑𝑑
̅
� 𝑐𝑐̅ 𝑑𝑑̅ + 𝑑𝑑
= 𝑎𝑎� 𝑏𝑏� 𝑐𝑐̅ + 𝑎𝑎𝑏𝑏 (𝐴𝐴 + 𝐴𝐴̅ = 1)
= 𝑎𝑎� 𝑐𝑐̅ 𝑏𝑏� + 𝑏𝑏 (𝐴𝐴 + 𝐴𝐴̅ = 1)
= 𝑎𝑎� 𝑐𝑐̅

Before simplification: After simplification:

gate count = 3
gate count = 8
(62.5% reduction!)

39
Digital Design
 Timing

Digital Design Page 40

Propagation Delays
o Apart from the # gates ($), we are also concerned with speed!
o Logic gates take time to change its output  Propagation Delay, tpd
o tpd = from 50% of change in i/p to 50% of induced change in o/p
o Usually in range of sub-ns! (Artix-7 FPGAs Link)
A B The green arrow
indicates that the falling
tpd edge of B is caused by
VDD
the rising edge of A.
A VDD/2
Gnd

VDD
B VDD/2
Gnd

We often think of digital signals If we zoom in, things are quite different!
changing instantaneously…
 Critical Path
o Assuming the below tpds, which path below is the slowest?
Critical path delay = 2.7ns
Gate tpd
NOT 0.3ns
2-input OR 0.6ns
3-input OR 0.8ns
3-input AND 0.7ns
4-input AND 0.9ns

o The Critical Path limits the speed at which the entire circuit operates
eg. the slowest path in circuit!
o Total tpd of a combinational circuit is sum of tpd through each element
on the critical path.
Which is the critical path here?
 Positive &
Negative Logic

Digital Design Page 43

 Positive and Negative Logic
Positive and negative logic map the physical voltage (H, L) in a gate
correspondence to a logic value
Positive logic (Active high)
◦ Voltage “H” (i.e. VDD)  interpreted as logic “1” or “True”
◦ Voltage “L” (i.e. Gnd or 0V)  interpreted as logic “0” or “False”
Negative Logic (Active low)
◦ Voltage “L” (i.e. Gnd or 0V)  interpreted as logic “1” or “True”
◦ Voltage “H” (i.e. VDD)  interpreted as logic “0” or “False”

Example: Conversion of a signal:

VDD
Positive logic T F T 𝑿𝑿. 𝑯𝑯 � . 𝑳𝑳
𝑿𝑿. 𝑯𝑯 = 𝑿𝑿
Gnd

VDD 𝑿𝑿. 𝑳𝑳 = 𝑿𝑿. 𝑯𝑯

Negative logic F T F 𝑿𝑿. 𝑳𝑳
Gnd

44
Digital Design
Example – Implementation in Positive
Logic
Implement the following Boolean function in positive logic.
A.H
𝐹𝐹 = 𝐴𝐴 � 𝐵𝐵 + 𝐴𝐴 � 𝐶𝐶 B.H
F.H
A.H
C.H

45
Digital Design
Example – Implementation in Positive
Logic
Implement the following Boolean function in positive logic.
A.H
𝐹𝐹 = 𝐴𝐴 � 𝐵𝐵 + 𝐴𝐴 � 𝐶𝐶 B.H
F.H
A.H
C.H

Implement the following Boolean function in mixed logic, where A , B are

active low signals and C, F are active high.

𝐹𝐹 = 𝐴𝐴 � 𝐵𝐵 + 𝐴𝐴 � 𝐶𝐶

Step 1: A.L  𝐴𝐴.H Step 2: 𝐴𝐴.H

(convert active B.L  𝐵𝐵.H (implement in 𝐵𝐵.H
F.H
low notation active high logic) 𝐴𝐴.H
A.L𝐴𝐴.H
to active high) C.H
C.H

46
Digital Design
 If you could only
choose one gate…
SELF-READING

Digital Design Page 47

Bubble Pushing Rule to Rearrange
Logic and Transform (N)AND/(N)OR
- NAND and NOR are universal gates – They can be used to implement any function!
- Graphic manipulations helps us to do NAND/NOR only implementations :
- Bubbles at the input of an AND gate can be “pushed” at its output, and the
gate is transformed into a NOR gate (similarly, NAND becomes OR)

𝐴𝐴 ⋅ 𝐵𝐵 = 𝐴𝐴 + 𝐵𝐵
De Morgan’s law
- bubbles at the input of an OR gate can be “pushed” at its output, and the
gate is transformed into a NAND gate (similarly, NOR becomes AND)
A.L
𝐴𝐴 + 𝐵𝐵 = 𝐴𝐴 ⋅ 𝐵𝐵 F.L
B.L
De Morgan’s law
- and vice versa, of course:
alternate gate
A.L representations
F.L
B.L

- two adjacent bubbles gets simplified 𝐹𝐹 = 𝐴𝐴 = 𝐴𝐴

48
Digital Design
 Example – Bubble Pushing
Implement the following Boolean function using only NOR gates and inverters.

𝐹𝐹 = 𝐴𝐴 � 𝐵𝐵 + 𝐴𝐴 � 𝐶𝐶
AND
Step 1: 𝐴𝐴 � 𝐵𝐵 NOR
Step 2: A
A (add the negation B F
B where needed for
the correct function) A
A C
C 𝐴𝐴 � 𝐶𝐶

redundant... NOR
A
Step 3:
(i) Replace AND gate with NOR gate B F
(ii) balance the bubbles using inverters
to maintain the correct functionality A

C gate count = 7
NOR

49
Digital Design
 Summary
Logic gate is a circuit that implement Boolean operations
AND, NAND, OR, NOR, XOR, XNOR gates
Boolean function implementation using logic gates
Boolean function simplification using algebra postulates and theorems
Timing
Positive and negative logic
◦ Definition
◦ Conversion between positive and negative logic
◦ Gates with mixed logic

Universal Gates

50
Digital Design
EE2026
Digital Design
BOOLEAN ALGEBRA, LOGIC GATES
Chua Dingjuan elechuad@nus.edu.sg
BOOLEAN ALGEBRA
Postulates, Theorems, Laws, AND, OR, NOT, XOR, Minterm,
Maxterm, SOP/POS, CSOP/CPOS
Outline
o What is Boolean Algebra?
o Theorems and Postulates
o Boolean functions and truth table
o Boolean function simplification using algebra manipulation

3
Digital Design
Ask Week 2 Questions here…
You can ask questions during the week using
slido here :

https://app.sli.do/event/aNGM7YZg9Q4J8pw
sh5pQne

Or at slido.com + #2026 002

Or the tiny little QR :

Digital Design Page 4

What is Boolean Algebra?
Brief History:
o Boolean was developed in 1854 by George Boole
(An English mathematician, philosopher, and
logician)
o Huntington formulated the postulates in 1904 as
the formal definition
o Boolean Algebra is the mathematical foundation
for digital system design, including computers
o It was first applied to the practical problem
(Analysis of networks of relays) in late 1930s by C.E
Shannon (MIT) who later introduced “Switching
algebra” in 1938
o Switching algebra is a Boolean algebra in which the
number of elements is precisely two

5
Digital Design
 Boolean Algebra
o Boolean algebra is a two-valued type of switching algebra
o Switching algebra represents bistable electrical switching
circuits (On or Off)
o Boolean algebra is defined by a set of elements, B, and there
are two main operators (AND, OR)
o Binary operators (two arguments involved)
o AND  “.”
o OR  “+”
o Plus, one unary operator (only one argument involved)
o NOT  “ � ” (Complement operator represented by an overbar)

o Boolean algebra satisfies six Huntington postulates

6
Digital Design
 Ref - Postulates of Boolean Algebra
There are Six Huntington Postulates that define the Boolean Algebra:
1. Closure - For all elements 𝑥𝑥 and 𝑦𝑦 in the set B
i. 𝑥𝑥 + 𝑦𝑦 𝑖𝑖𝑖𝑖 𝑎𝑎𝑎𝑎 𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒 𝑜𝑜𝑜𝑜 𝑩𝑩 𝑎𝑎𝑎𝑎𝑎𝑎
ii. 𝑥𝑥 � 𝑦𝑦 𝑖𝑖𝑖𝑖 𝑎𝑎𝑎𝑎 𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒 𝑜𝑜𝑜𝑜 𝑩𝑩

2. There exists a 0 and 1 element in B, such that

i. 𝑥𝑥 + 0 = 𝑥𝑥
ii. x� 1 = 𝑥𝑥

3. Commutative Law
i. x+𝑦𝑦 = 𝑦𝑦 + 𝑥𝑥
ii. x� 𝑦𝑦 = 𝑦𝑦 � 𝑥𝑥

4. Distributive Law
i. 𝑥𝑥 � 𝑦𝑦 + 𝑧𝑧 = 𝑥𝑥 � 𝑦𝑦 + 𝑥𝑥 � 𝑧𝑧 (� 𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜 +)
ii. 𝑥𝑥 + 𝑦𝑦 � 𝑧𝑧 = (𝑥𝑥 + 𝑦𝑦) � (𝑥𝑥 + 𝑧𝑧) (+ 𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜 �)

5. For every element 𝑥𝑥 in the set B, there exists an element 𝑥𝑥̅ in the set B, such that
i. 𝑥𝑥 + 𝑥𝑥̅ = 1
ii. 𝑥𝑥 � 𝑥𝑥̅ = 0
(𝑥𝑥 is called the complement of 𝑥𝑥)

6. There exist at least two distinct elements in the set B

7
Digital Design
 Ref - Boolean vs. Ordinary Algebra

Boolean algebra Ordinary algebra

No associative law. But it can be derived from Associative law is included:
the other postulates 𝑎𝑎 + 𝑏𝑏 + 𝑐𝑐 = 𝑎𝑎 + 𝑏𝑏 + 𝑐𝑐
Distributive law:
x + 𝑦𝑦 � 𝑧𝑧 = (𝑥𝑥 + 𝑦𝑦) � (𝑥𝑥 + 𝑧𝑧) valid Not valid
No additive or multiplicative inverses,
therefore there are no subtraction and
division operation Subtraction and division operations exist

Complement operation available No complement operation

Boolean algebra: Undefined set of elements;
Switching algebra: a two-valued Boolean
algebra, whose element set only has two Dealing with real numbers and constituting an
elements, 0 and 1. infinite set of elements

8
Digital Design
 The Three Operators in Two-
Valued Boolean Algebra (B={0,1})
OR: 𝑨𝑨 + 𝑩𝑩 AND: 𝑨𝑨 � 𝑩𝑩 NOT: 𝑨𝑨
𝑨𝑨 𝑩𝑩 𝑨𝑨 + 𝑩𝑩 𝑨𝑨 𝑩𝑩 𝑨𝑨 � 𝑩𝑩 𝑨𝑨 𝑨𝑨

0 0 0 0 0 0 0 1

0 1 1 0 1 0 1 0

1 0 1 1 0 0

1 1 1 1 1 1 A = 0 → 𝐴𝐴 = 1
A = 1 → 𝐴𝐴 = 0
0 + 0 = 0 0 � 0 = 0
0 + 1 = 1 0 � 1 = 0
1 + 0 = 1 1 � 0 = 0
1 + 1 = 1 1 � 1 = 1

Priority: NOT has highest precedence, followed by AND and OR

NOT(A ⋅ B + C) = NOT((A ⋅ B) + C)
9
Digital Design
 Theorems of Boolean Algebra
# Theorem

1 𝐴𝐴 + 𝐴𝐴 = 𝐴𝐴 𝐴𝐴 � 𝐴𝐴 = 𝐴𝐴 Tautology Law

2 𝐴𝐴 + 1 = 1 𝐴𝐴 � 0 = 0 Union Law

3 𝐴𝐴� = 𝐴𝐴 Involution Law

4 𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶 𝐴𝐴 � 𝐵𝐵 � 𝐶𝐶 = 𝐴𝐴 � 𝐵𝐵 � 𝐶𝐶 Associative Law
= 𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶
5 𝐴𝐴 + 𝐵𝐵 = 𝐴𝐴̅ � 𝐵𝐵� 𝐴𝐴 � 𝐵𝐵 = 𝐴𝐴̅ + 𝐵𝐵� De Morgan’s Law

6 𝐴𝐴 + 𝐴𝐴 � 𝐵𝐵 = 𝐴𝐴 𝐴𝐴 � 𝐴𝐴 + 𝐵𝐵 = 𝐴𝐴 Absorption Law

7 𝐴𝐴 + 𝐴𝐴̅ � 𝐵𝐵 = 𝐴𝐴 + 𝐵𝐵 𝐴𝐴 � 𝐴𝐴̅ + 𝐵𝐵 = 𝐴𝐴 � 𝐵𝐵

8 𝐴𝐴𝐴𝐴 + 𝐴𝐴𝐵𝐵� = 𝐴𝐴 � = 𝐴𝐴
(𝐴𝐴 + 𝐵𝐵)(𝐴𝐴 + 𝐵𝐵) Logical adjacency

9 ̅ + 𝐵𝐵𝐵𝐵
𝐴𝐴𝐴𝐴 + 𝐴𝐴𝐶𝐶 𝐴𝐴 + 𝐵𝐵 𝐴𝐴̅ + 𝐶𝐶 𝐵𝐵 + 𝐶𝐶 Consensus Law
̅
= 𝐴𝐴𝐴𝐴 + 𝐴𝐴𝐶𝐶 = (𝐴𝐴 + 𝐵𝐵)(𝐴𝐴̅ + 𝐶𝐶)

Duality (OR and AND, 0 and 1 can be interchanged)

10
Digital Design
 Boolean Functions and Truth Table
•A Boolean function expresses the logical relationship between binary variables.
•It can be evaluated by determining the binary value of the expression for all
possible values of the variables
Truth table is a tabular technique for listing all 𝑭𝑭𝟑𝟑 = 𝑨𝑨 + 𝑩𝑩𝑩𝑩
possible combinations of input variables and A B C F3
the values of function for each combination
0 0 0 0
𝑭𝑭𝟏𝟏 = 𝑨𝑨 + 𝑩𝑩
0 0 1 0
A B F1 0 1 0 0
0 0 0 0 1 1 1
0 1 1 1 0 0 1
1 0 1 1 0 1 1
1 1 1 1 1 0 1

1 1 1 1

11
Digital Design
 Examples - Truth Table
Prove the De Morgan’s Law:
𝐴𝐴 + 𝐵𝐵 = 𝐴𝐴̅ � 𝐵𝐵� 𝐴𝐴 � 𝐵𝐵 = 𝐴𝐴̅ + 𝐵𝐵�
A B 𝑨𝑨 + 𝑩𝑩 � � 𝑩𝑩
𝑨𝑨 � A B 𝑨𝑨 � 𝑩𝑩 � + 𝑩𝑩
𝑨𝑨 �

0 0 1 1 0 0 1 1
0 1 0 0 0 1 1 1
1 0 0 0 1 0 1 1
1 1 0 0 1 1 0 0

Prove : 𝐴𝐴 + 𝐴𝐴̅ � 𝐵𝐵 = 𝐴𝐴 + 𝐵𝐵 𝐴𝐴 � 𝐴𝐴 + 𝐵𝐵 = 𝐴𝐴
A B � � 𝑩𝑩
𝑨𝑨 + 𝑨𝑨 𝑨𝑨 + 𝑩𝑩 A B 𝑨𝑨 � 𝑨𝑨 + 𝑩𝑩 𝑨𝑨
0 0 0 0 0 0 0 0
0 1 1 1 0 1 0 0
1 0 1 1 1 0 1 1

1 1 1 1 1 1 1 1

14
Digital Design
 Truth Table – examples (cont.)
Prove : 𝐴𝐴 + 𝐵𝐵 � 𝐶𝐶 = (𝐴𝐴 + 𝐵𝐵) � (𝐴𝐴 + 𝐶𝐶)

𝑨𝑨 𝑩𝑩 𝑪𝑪 𝑨𝑨 + 𝑩𝑩 � 𝑪𝑪 (𝑨𝑨 + 𝑩𝑩) � (𝑨𝑨 + 𝑪𝑪)

0 0 0 0 0
0 0 1 0 0
0 1 0 0 0
0 1 1 1 1
1 0 0 1 1
1 0 1 1 1
1 1 0 1 1
1 1 1 1 1

15
Digital Design
But how do we
use these ideas?

Page 16
Design Example
Ben Bitdiddle is having a picnic. He won’t enjoy it if it
rains or if there are ants. Design a circuit that will output
TRUE only if Ben enjoys the picnic.

Solution
Inputs : A (Ants), B (Rain)
Output : E (Ben’s Enjoyment)

Boolean Algebra Version Truth Table Version

E=? A B 𝑬𝑬
Ben enjoys his picnic if there 0 0
is no rain and no ants : 0 1
1 0
E = 1 if A = 0 and B = 0
1 1

Digital Design Page 18

 Minterm and Maxterm
A B E Minterm Maxterm
0 0 1 𝐴𝐴̅ � 𝐵𝐵� 𝐴𝐴 + 𝐵𝐵
0 1 0 𝐴𝐴̅ � 𝐵𝐵 𝐴𝐴 + 𝐵𝐵�
1 0 0 𝐴𝐴 � 𝐵𝐵� 𝐴𝐴̅ + 𝐵𝐵
1 1 0 𝐴𝐴 � 𝐵𝐵 𝐴𝐴̅ + 𝐵𝐵�

minterm A. B = 1 for maxterm 𝐴𝐴̅ + 𝐵𝐵� = 0

A = 1 and B = 1 for A = 1 and B = 1

Minterm Maxterm
◦ Minterm is a product term that contains all – Maxterm is a sum term that contains all
variables in the function variables in the function
◦ AND all the variables – OR all the variables
◦ If the variable in truth table is “0”, take its
complement in the minterm – If the variable in truth table is “1”, take its
◦ Minterm is equal to 1 for that set of given complement in the maxterm
input – Maxterm is equal to 0 for that set of given
input
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Digital Design
 Truth Table  CSOP or CPOS
A Boolean function is in canonical form if it is expressed as
◦ a sum of minterms (Canonical Sum Of Products - CSOP) or
◦ a product of maxterms (Canonical Product Of Sums - CPOS)

Using Ben’s Bitdiddle’s truth table :

• CSOP  sum the minterms that make
A B E minterm maxterm output = 1
0 0 1 𝐴𝐴̅ � 𝐵𝐵� 𝐴𝐴 + 𝐵𝐵
0 1 0 𝐴𝐴̅ � 𝐵𝐵 𝐴𝐴 + 𝐵𝐵�
1 0 0 𝐴𝐴 � 𝐵𝐵� 𝐴𝐴̅ + 𝐵𝐵 • CPOS  product the maxterms that make
output = 0
1 1 0 𝐴𝐴 � 𝐵𝐵 𝐴𝐴̅ + 𝐵𝐵�
A truth table expressed in either CSOP
or CPOS. (How should we choose?)
Are the above two functions equivalent?
How do we check?

23
Digital Design
 SOP and POS  Truth Table
Are the following two Boolean functions same?
𝑬𝑬𝟏𝟏 𝑨𝑨, 𝑩𝑩 = 𝐴𝐴̅ � 𝐵𝐵�
𝑬𝑬𝟐𝟐 𝑨𝑨, 𝑩𝑩 = 𝐴𝐴 + 𝐵𝐵� . 𝐴𝐴̅ + 𝐵𝐵 . 𝐴𝐴̅ + 𝐵𝐵�
Let’s use truth tables to check:

𝑬𝑬𝟏𝟏 𝑨𝑨, 𝑩𝑩 = 𝐴𝐴̅ � 𝐵𝐵� 𝑬𝑬𝟐𝟐 𝑨𝑨, 𝑩𝑩 = 𝐴𝐴 + 𝐵𝐵� . 𝐴𝐴̅ + 𝐵𝐵 . 𝐴𝐴̅ + 𝐵𝐵�
A B E1 A B E2
0 0 0 0
0 1 0 1
1 0 1 0
1 1 1 1

SOP: If any PRODUCT in SOP is “1”, the function is “1”. Otherwise, the function is “0”
POS: If any SUM in POS is “0”, the function is “0”. Otherwise, the function is “1”
SOP and POS are different ways to present the same Boolean function
25
Digital Design
 SOP and POS  Truth Table
Are the following two Boolean functions same?
𝑬𝑬𝟏𝟏 𝑨𝑨, 𝑩𝑩 = 𝐴𝐴̅ � 𝐵𝐵�
𝑬𝑬𝟐𝟐 𝑨𝑨, 𝑩𝑩 = 𝐴𝐴 + 𝐵𝐵� . 𝐴𝐴̅ + 𝐵𝐵 . 𝐴𝐴̅ + 𝐵𝐵�
Can we also prove this via Boolean algebra?

𝑬𝑬𝟏𝟏 𝑨𝑨, 𝑩𝑩 = 𝐴𝐴̅ � 𝐵𝐵� 𝑬𝑬𝟐𝟐 𝑨𝑨, 𝑩𝑩 = 𝐴𝐴 + 𝐵𝐵� . 𝐴𝐴̅ + 𝐵𝐵 . 𝐴𝐴̅ + 𝐵𝐵�

27
Digital Design
 Example-2: Non-Canonical  Canonical
Form via Truth Table
Example: For the given Boolean function below, find a canonical minterm and
maxterm expression.
1) obtain the truth table from the given function
2) find minterm or maxterm expression from truth table (CSOP or CPOS)
𝐹𝐹 𝑥𝑥, 𝑦𝑦, 𝑧𝑧 = 𝑥𝑥̅ + 𝑦𝑦𝑧𝑧̅ Non Canonical form

Truth table:
x y z F Canonical minterm expression:
0 0 0 1
𝐹𝐹 𝑥𝑥, 𝑦𝑦, 𝑧𝑧 = 𝑥𝑥̅ 𝑦𝑦�𝑧𝑧̅ + 𝑥𝑥̅ 𝑦𝑦𝑧𝑧
� + 𝑥𝑥𝑦𝑦
̅ 𝑧𝑧̅ + 𝑥𝑥𝑦𝑦𝑧𝑧
̅ + 𝑥𝑥𝑥𝑥𝑧𝑧̅
0 0 1 1
0 1 0 1 (only contains the minterms that make the function = 1)
0 1 1 1
Canonical maxterm expression:
1 0 0 0
1 0 1 0 𝐹𝐹 𝑥𝑥, 𝑦𝑦, 𝑧𝑧 = 𝑥𝑥̅ + 𝑦𝑦 + 𝑧𝑧 𝑥𝑥̅ + 𝑦𝑦 + 𝑧𝑧̅ (𝑥𝑥̅ + 𝑦𝑦� + 𝑧𝑧)̅
1 1 0 1 (only contains the maxterms that make the function = 0)
1 1 1 0
29
Digital Design
 Example-3: Non-Canonical  Canonical
Form via Postulates and Theorems
Example: For the given Boolean functions below, convert it to canonical minterm or
maxterm expression.
(*Using postulates/theorem to expand the given function to canonical form)

SOP  CSOP: 𝐹𝐹 𝑥𝑥, 𝑦𝑦, 𝑧𝑧 = 𝑥𝑥𝑦𝑦 ̅ + 𝑥𝑥𝑥𝑥 For missing literals, complete
(CSOP – Canonical SOP) minterms through postulates:
= 𝑥𝑥𝑦𝑦
̅ � 1 + 𝑥𝑥 � 1 � 𝑧𝑧
= 𝑥𝑥𝑦𝑦̅ z + 𝑧𝑧̅ + 𝑥𝑥 𝑦𝑦 + 𝑦𝑦� 𝑧𝑧 A � 1 = 𝐴𝐴 𝑎𝑎𝑎𝑎𝑎𝑎 𝐴𝐴 + 𝐴𝐴̅ =
= 𝑥𝑥𝑦𝑦𝑧𝑧
̅ + 𝑥𝑥𝑦𝑦 ̅ 𝑧𝑧̅ + 𝑥𝑥𝑥𝑥𝑥𝑥 + 𝑥𝑥𝑦𝑦𝑧𝑧
� 1
1) express SOP as POS
1) a) complement twice
SOP  CPOS: 𝐹𝐹 𝑥𝑥, 𝑦𝑦, 𝑧𝑧 = 𝑥𝑥𝑦𝑦
̅ + 𝑥𝑥𝑥𝑥 b) apply De Morgan’s law
(CSOP – Canonical POS)
̅ + 𝑥𝑥𝑥𝑥 a
= 𝑥𝑥𝑦𝑦 c) expand
d) re-apply De Morgan’s law
Use distribution postulate: = 𝑥𝑥 + 𝑦𝑦� 𝑥𝑥̅ + 𝑧𝑧̅ b 2) for missing literals, complete
𝐴𝐴 + 𝑩𝑩𝑪𝑪 = 𝐴𝐴 + 𝑩𝑩 𝐴𝐴 + 𝑪𝑪 maxterms through distribution
(A = incomplete sum,
= 𝑥𝑥 𝑥𝑥̅ + 𝑥𝑥 𝑧𝑧̅ + 𝑥𝑥̅ 𝑦𝑦� + 𝑦𝑦� 𝑧𝑧̅ c
postulate
C=NOT(B)=missing literal) = 𝑥𝑥 + 𝑦𝑦 𝑥𝑥̅ + 𝑧𝑧 𝑦𝑦 + 𝑧𝑧 d
x+𝑦𝑦 = (𝑥𝑥 + 𝑦𝑦) + 𝒛𝒛�𝒛𝒛 2) = 𝑥𝑥 + 𝑦𝑦 + 𝑧𝑧 ⋅ 𝑥𝑥 + 𝑦𝑦 + 𝑧𝑧̅ ⋅ 𝑥𝑥̅ + 𝑦𝑦 + 𝑧𝑧 ⋅ 𝑥𝑥̅ + 𝑦𝑦� + 𝑧𝑧
= (𝑥𝑥 + 𝑦𝑦 + 𝒛𝒛)(𝑥𝑥 + 𝑦𝑦 + 𝒛𝒛� ) ⋅ 𝑥𝑥 + 𝑦𝑦 + 𝑧𝑧 ⋅ 𝑥𝑥̅ + 𝑦𝑦 + 𝑧𝑧

30
Digital Design
 Example-3 : SOP ⇔ POS (De Morgan’s)
Truth table: Applying De Morgan’s Law to CSOP of 𝑭𝑭𝟏𝟏 :
𝐴𝐴 𝐵𝐵 𝐶𝐶 𝐹𝐹1 𝐹𝐹𝟏𝟏
𝑭𝑭𝟏𝟏 = 𝑭𝑭𝟏𝟏 = 𝑭𝑭𝟏𝟏,𝑪𝑪𝑪𝑪𝑪𝑪𝑪𝑪
0 0 0 0 1
= 𝑨𝑨� 𝑩𝑩 � + 𝑨𝑨
� 𝑪𝑪 � 𝑩𝑩
� 𝑪𝑪 + 𝑨𝑨� 𝑩𝑩𝑩𝑩 + 𝑨𝑨𝑨𝑨𝑨𝑨
0 0 1 0 1 � 𝑩𝑩 � � 𝑨𝑨
� 𝑪𝑪 � 𝑩𝑩
� 𝑪𝑪 � 𝑨𝑨
� 𝑩𝑩𝑩𝑩 � 𝑨𝑨𝑨𝑨𝑨𝑨
= 𝑨𝑨
0 1 0 1 0 = 𝑨𝑨 + 𝑩𝑩 + 𝑪𝑪 𝑨𝑨 + 𝑩𝑩 + 𝑪𝑪 � 𝑨𝑨 + 𝑩𝑩 � (𝑨𝑨
� + 𝑪𝑪 � + 𝑩𝑩 �
� + 𝑪𝑪)
0 1 1 0 1

1 0 0 1 0
Now, find CPOS of F1 directly from truth table:
1 0 1 1 0 clearly the
1 1 0 1 0 𝑭𝑭𝟏𝟏 𝑨𝑨, 𝑩𝑩, 𝑪𝑪 CPOS of F1 same
� 𝑨𝑨 + 𝑩𝑩
= 𝑨𝑨 + 𝑩𝑩 + 𝑪𝑪 𝑨𝑨 + 𝑩𝑩 + 𝑪𝑪 � (𝑨𝑨
� + 𝑪𝑪 � + 𝑩𝑩 �
� + 𝑪𝑪)
1 1 1 0 1
CPOS can be obtained from CSOP (and vice versa) by
applying De Morgan’s Law!

31
Digital Design
Pre-Lab Exercise
The following task is required to be implemented :
oWhen switch A turns on, only LED1 lights up.
oWhen switch B turns on, only LED2 lights up.
oWhen both switches A and B turn on, LED1, LED2, and LED3 light up.

LED1 =
LED2 =
LED3 =

Digital Design Page 33

Pre-Lab Exercise
Modify your boolean expressions for LED1, LED2 and LED3 to incorporate an
additional switch C. (“PRACTICE TASK FOR LAB 1”)
o If switch C is in the OFF state, it forces all the three LEDs to be in the OFF
state.
o If the switch C is in the ON state, the design behaves exactly as described
previously.

LED1 =

LED2 =

LED3 =

Digital Design Page 35

 Summary
oPostulates and theorems of Boolean algebra
oThree binary operators: AND, OR and NOT
oBoolean Functions
oTruth table and Boolean function evaluation using truth table
oBoolean function in SOP or POS form
oObtain SOP or POS from truth table
oMinterm and maxterm
oCanonical form of Boolean function
oConvert non-canonical form to canonical SOP or POS expressions.

37
Digital Design
Guidelines for Simplification of
Boolean Function (in SOP)
Three most used theorems:
(1) 𝐴𝐴𝐴𝐴 + 𝐴𝐴𝐵𝐵� = 𝐴𝐴 (Logical adjacency)
(2) 𝐴𝐴 + 𝐴𝐴̅ � 𝐵𝐵 = 𝐴𝐴 + 𝐵𝐵
(3) 𝐴𝐴𝐴𝐴 + 𝐴𝐴𝐶𝐶̅ + 𝐵𝐵𝐵𝐵 = 𝐴𝐴𝐴𝐴 + 𝐴𝐴𝐶𝐶
̅ (Consensus)

Apply (1) until it cannot be applied further

Apply (2) until it cannot be applied further
Go back to (1) and then (2) until they can no longer be applied
Apply (3) until it cannot be applied further
Go back to (1), (2) and then (3) until none of them can be applied
It can then be assumed that the function is simplified
Empirical: the result is usually close to minimal, but may not be the minimal
Cumbersome: other methods are much easier and quicker

38
Digital Design
LOGIC GATES
AND, OR, NOT, XOR gates

©COPYRIGHT CHUA DINGJUAN. ALL RIGHTS RESERVED.

Outline
Logic gate introduction
◦AND/NAND, OR/NOR, NOT/Buffer, XOR/NXOR
◦different levels of description (Boolean, truth table,
graphical, Verilog)
Implementation of Boolean function using gates
◦different levels of description (Boolean, graphical, Verilog)
Design simplification by algebra manipulation
Commercial logic gates

40
Digital Design
 Logic Gate Introduction
Logic gates are digital circuits that implement the Boolean
operations.
Basic Logic Gates:
Gate Symbol Function Verilog Gate Symbol Function Verilog
(F) Operator (F) Operator
A
AND A F 𝐴𝐴 � 𝐵𝐵 F=A&B NAND F 𝐴𝐴 � 𝐵𝐵 F = ~(A & B)
B B

OR A 𝐴𝐴 + 𝐵𝐵 F=A|B NOR A 𝐴𝐴 + 𝐵𝐵 F = ~(A | B)

F F
B B

NOT 𝐴𝐴̅ F = ~A Buffer 𝐴𝐴 F=A

XOR 𝐴𝐴 ⊕ 𝐵𝐵 F=A^B XNOR A 𝐴𝐴 ⊕ 𝐵𝐵 F = ~(A ^ B)

F
B

Verilog Bit-wise Operator Precedence : ~, &, ^, |

41
Digital Design
 AND and NAND Gates
A Truth Table (AND, NAND):
F 𝑭𝑭 = 𝑨𝑨 � 𝑩𝑩
B AND NAND
A B 𝑨𝑨 � 𝑩𝑩 𝑨𝑨 � 𝑩𝑩
A
F 𝑭𝑭 = 𝑨𝑨 � 𝑩𝑩 0 0 0 1
B
1 0 0 1
A
F 0 1 0 1
B
1 1 1 0
bubble = complement
AND NAND
F is TRUE only when both A and B are • F is FALSE only if both A and
TRUE B are TRUE

module andgate(A, B, F); module nandgate(A, B, F);

input A, B; input A, B;
output F; output F;
assign F = A & B; assign F = _______
endmodule endmodule
42
Digital Design
 OR and NOR Gates
A Truth Table (OR, NOR):
F 𝑭𝑭 = 𝑨𝑨 + 𝑩𝑩
B OR NOR
A B 𝑨𝑨 + 𝑩𝑩 𝑨𝑨 + 𝑩𝑩
A
F 𝑭𝑭 = 𝑨𝑨 + 𝑩𝑩 0 0 0 1
B
1 0 1 0
A 0 1 1 0
F
B
1 1 1 0

OR NOR
• F is FALSE only when both A and B • F is TRUE only if both A and
are FALSE B are FALSE

module orgate(A, B, F); module norgate(A, B, F);

input A, B; input A, B;
output F; output F;
assign F = A | B; assign F = ~( A | B);
endmodule endmodule
44
Digital Design
 XOR and XNOR Gates
Truth Table (XOR, XNOR):
𝑭𝑭 = 𝑨𝑨𝑩𝑩 + 𝑨𝑨𝑩𝑩 = 𝑨𝑨 ⊕ 𝑩𝑩
XOR XNOR
A B 𝑨𝑨 ⊕ 𝑩𝑩 𝑨𝑨 ⊕ 𝑩𝑩
A
F 𝑭𝑭 = 𝑨𝑨 ⊕ 𝑩𝑩 0 0 0 1
B
1 0 1 0
0 1 1 0
A
F
B 1 1 0 1

XOR XNOR
• F is TRUE if A ≠ B • F is TRUE if A = B

module xorgate(A, B, F); module xnorgate(A, B, F);

input A, B; input A, B;
output F; output F;
assign F = A ^ B; assign F = ~(A ^ B);
endmodule endmodule
45
Digital Design
Cont’d Ben Bitdiddle’s Example
We developed the following two Boolean expressions for Ben :
𝑬𝑬 𝑨𝑨, 𝑩𝑩 = 𝐴𝐴̅ � 𝐵𝐵�
𝑬𝑬 𝑨𝑨, 𝑩𝑩 = 𝐴𝐴 + 𝐵𝐵� . 𝐴𝐴̅ + 𝐵𝐵 . 𝐴𝐴̅ + 𝐵𝐵�
How do we implement them?

𝑬𝑬𝟏𝟏 𝑨𝑨, 𝑩𝑩 = 𝐴𝐴̅ � 𝐵𝐵� 𝑬𝑬𝟐𝟐 𝑨𝑨, 𝑩𝑩 = 𝐴𝐴 + 𝐵𝐵� . 𝐴𝐴̅ + 𝐵𝐵 . 𝐴𝐴̅ + 𝐵𝐵�
# of Gates needed = # of Gates needed =

46
Digital Design
 Cont’d Ben Bitdiddle’s Example
We developed the following two Boolean expressions for Ben :
𝑬𝑬 𝑨𝑨, 𝑩𝑩 = 𝐴𝐴̅ � 𝐵𝐵�
𝑬𝑬 𝑨𝑨, 𝑩𝑩 = 𝐴𝐴 + 𝐵𝐵� . 𝐴𝐴̅ + 𝐵𝐵 . 𝐴𝐴̅ + 𝐵𝐵�
How do we implement them?

𝑬𝑬𝟏𝟏 𝑨𝑨, 𝑩𝑩 = 𝐴𝐴̅ � 𝐵𝐵� 𝑬𝑬𝟐𝟐 𝑨𝑨, 𝑩𝑩 = 𝐴𝐴 + 𝐵𝐵� . 𝐴𝐴̅ + 𝐵𝐵 . 𝐴𝐴̅ + 𝐵𝐵�
# of Gates needed = # of Gates needed =
𝐴𝐴
𝐴𝐴 𝐵𝐵
𝐸𝐸1
𝐵𝐵
𝐸𝐸2

47
Digital Design
 Implementation using Logic Gates –
Sketch Method
- Implement the following Boolean functions to logic gates, assume that
the maximum number of inputs of a gate is 4.
𝐹𝐹 𝑤𝑤, 𝑥𝑥, 𝑦𝑦, 𝑧𝑧 = 𝑤𝑤
� 𝑥𝑥𝑧𝑧
̅ + 𝑤𝑤𝑥𝑥𝑥𝑥
� + 𝑤𝑤𝑤𝑤𝑤𝑤 + 𝑥𝑥𝑥𝑥𝑥𝑥
𝑤𝑤 𝑥𝑥 𝑦𝑦 𝑧𝑧
𝑤𝑤
� �
𝒙𝒙
Input signals needed?
𝑤𝑤, 𝑤𝑤,
� 𝑥𝑥, 𝑥𝑥,̅ 𝑦𝑦, 𝑧𝑧

Types / # of Gates
needed?
AND – 3 inputs
OR – 4 inputs

Schematic drawn in
PLA configuration
# of gates = 7

assign F = ~w & ~x & z | ~w & x & z | w & y & z | x & y & z;

Digital Design
49
 Implementation of Boolean
Function using Logic Gates
- Implement the following Boolean functions to logic gates, assume that
the maximum number of inputs of a gate is 4.
𝐹𝐹 𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑 = 𝑎𝑎𝑎𝑎𝑐𝑐̅ + 𝑎𝑎𝑎𝑎𝑎𝑎 + 𝑏𝑏𝑏𝑏𝑏𝑏 + 𝑎𝑎𝑐𝑐𝑐𝑐 �
� + 𝑎𝑎𝑏𝑏𝑐𝑐𝑑𝑑

gate count = ____

module func(a,b,c,d,F);
input a, b, c, d;
output F;
assign F = a & b & ~c | a & b & c | b & c & d | ~a & c & d | a & ~b & ~c & d;
endmodule
51
Digital Design
Boolean Function Simplification using
Algebra Manipulation

•To reduce the hardware cost, the Boolean function

can be simplified before implemented using logic
gates
•A simplified Boolean Function contains a minimal
number of terms such that no other expression with
fewer literals and terms will represent the original
function
•Simplification can be done by
•Algebraic manipulation using postulates and theorem
•Karnaugh Map  Next Topic!

52
Digital Design
 Ex - Boolean Function Simplification
(Relook at the second example):

𝐹𝐹 𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑 = 𝑎𝑎𝑎𝑎𝑐𝑐̅ + 𝑎𝑎𝑎𝑎𝑎𝑎 + 𝑏𝑏𝑏𝑏𝑏𝑏 + 𝑎𝑎𝑐𝑐𝑐𝑐 �

� + 𝑎𝑎𝑏𝑏𝑐𝑐𝑑𝑑
= 𝑎𝑎𝑎𝑎 𝑐𝑐̅ + 𝑐𝑐 + 𝑏𝑏𝑏𝑏𝑏𝑏 + 𝑎𝑎𝑐𝑐𝑐𝑐
� + 𝑎𝑎𝑏𝑏𝑐𝑐𝑑𝑑 � (𝐴𝐴 + 𝐴𝐴̅ = 1)
= 𝑎𝑎 𝑏𝑏 + 𝑏𝑏� 𝑐𝑐𝑑𝑑 ̅ + 𝑏𝑏𝑏𝑏𝑏𝑏 + 𝑎𝑎𝑐𝑐𝑐𝑐
� (𝐴𝐴 + 𝐴𝐴̅ � 𝐵𝐵 = 𝐴𝐴 + 𝐵𝐵)
= 𝑎𝑎 𝑏𝑏 + 𝑐𝑐𝑑𝑑 ̅ + 𝑏𝑏𝑏𝑏𝑏𝑏 + 𝑎𝑎𝑐𝑐𝑐𝑐
�
= 𝑎𝑎𝑏𝑏 + 𝑎𝑎� 𝑐𝑐𝑐𝑐 + 𝑏𝑏 𝑐𝑐𝑐𝑐 + 𝑎𝑎𝑐𝑐𝑑𝑑 ̅ (𝐴𝐴𝐵𝐵 + 𝐴𝐴𝐶𝐶̅ + 𝐵𝐵𝐶𝐶 = 𝐴𝐴𝐴𝐴 + 𝐴𝐴𝐶𝐶)
̅ - consensus
= 𝑎𝑎𝑎𝑎 + 𝑎𝑎𝑐𝑐𝑐𝑐
� + 𝑎𝑎𝑐𝑐𝑑𝑑 ̅

Before simplification: After simplification:

gate count = 6
gate count = 11 (45.5% reduction!)
53
Digital Design
 Ex - Boolean Function Simplification

𝐹𝐹 𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑 = 𝑎𝑎� 𝑏𝑏� 𝑐𝑐̅ + 𝑎𝑎𝑏𝑏

� 𝑐𝑐̅𝑑𝑑̅ + 𝑎𝑎𝑏𝑏
� 𝑐𝑐𝑑𝑑
̅
� 𝑐𝑐̅ 𝑑𝑑̅ + 𝑑𝑑
= 𝑎𝑎� 𝑏𝑏� 𝑐𝑐̅ + 𝑎𝑎𝑏𝑏 (𝐴𝐴 + 𝐴𝐴̅ = 1)
= 𝑎𝑎� 𝑐𝑐̅ 𝑏𝑏� + 𝑏𝑏 (𝐴𝐴 + 𝐴𝐴̅ = 1)
= 𝑎𝑎� 𝑐𝑐̅

Before simplification: After simplification:

gate count = 3
gate count = 8
(62.5% reduction!)

54
Digital Design
 Timing

Digital Design Page 55

Propagation Delays
o Apart from the # gates ($), we are also concerned with speed!
o Logic gates take time to change its output  Propagation Delay, tpd
o tpd = from 50% of change in i/p to 50% of induced change in o/p
o Usually in range of sub-ns! (Artix-7 FPGAs Link)
A B The green arrow
indicates that the falling
tpd edge of B is caused by
VDD
the rising edge of A.
A VDD/2
Gnd

VDD
B VDD/2
Gnd

We often think of digital signals If we zoom in, things are quite different!
changing instantaneously…
 Critical Path
o Assuming the below tpds, which path below is the slowest?

Gate tpd
NOT 0.3ns
2-input OR 0.6ns
3-input OR 0.8ns
3-input AND 0.7ns
4-input AND 0.9ns

o The Critical Path limits the speed at which the entire circuit operates
eg. the slowest path in circuit!
o Total tpd of a combinational circuit is sum of tpd through each element
on the critical path.
Which is the critical path here?
 Positive &
Negative Logic

Digital Design Page 58

 Positive and Negative Logic
Positive and negative logic map the physical voltage (H, L) in a gate
correspondence to a logic value
Positive logic (Active high)
◦ Voltage “H” (i.e. VDD)  interpreted as logic “1” or “True”
◦ Voltage “L” (i.e. Gnd or 0V)  interpreted as logic “0” or “False”
Negative Logic (Active low)
◦ Voltage “L” (i.e. Gnd or 0V)  interpreted as logic “1” or “True”
◦ Voltage “H” (i.e. VDD)  interpreted as logic “0” or “False”

Example: Conversion of a signal:

VDD
Positive logic T F T 𝑿𝑿. 𝑯𝑯 � . 𝑳𝑳
𝑿𝑿. 𝑯𝑯 = 𝑿𝑿
Gnd

VDD 𝑿𝑿. 𝑳𝑳 = 𝑿𝑿. 𝑯𝑯

Negative logic F T F 𝑿𝑿. 𝑳𝑳
Gnd

59
Digital Design
Example – Implementation in Positive
Logic
Implement the following Boolean function in positive logic.
A.H
𝐹𝐹 = 𝐴𝐴 � 𝐵𝐵 + 𝐴𝐴 � 𝐶𝐶 B.H
F.H
A.H
C.H

Implement the following Boolean function in mixed logic, where A , B are

active low signals and C, F are active high.

𝐹𝐹 = 𝐴𝐴 � 𝐵𝐵 + 𝐴𝐴 � 𝐶𝐶

Step 1: A.L  𝐴𝐴.H Step 2: 𝐴𝐴.H

(convert active B.L  𝐵𝐵.H (implement in 𝐵𝐵.H
F.H
low notation active high logic) 𝐴𝐴.H
A.L𝐴𝐴.H
to active high) C.H
C.H

61
Digital Design
 If you could only
choose one gate…
SELF-READING

Digital Design Page 62

Bubble Pushing Rule to Rearrange
Logic and Transform (N)AND/(N)OR
- NAND and NOR are universal gates – They can be used to implement any function!
- Graphic manipulations helps us to do NAND/NOR only implementations :
- Bubbles at the input of an AND gate can be “pushed” at its output, and the
gate is transformed into a NOR gate (similarly, NAND becomes OR)

𝐴𝐴 ⋅ 𝐵𝐵 = 𝐴𝐴 + 𝐵𝐵
De Morgan’s law
- bubbles at the input of an OR gate can be “pushed” at its output, and the
gate is transformed into a NAND gate (similarly, NOR becomes AND)
A.L
𝐴𝐴 + 𝐵𝐵 = 𝐴𝐴 ⋅ 𝐵𝐵 F.L
B.L
De Morgan’s law
- and vice versa, of course:
alternate gate
A.L representations
F.L
B.L

- two adjacent bubbles gets simplified 𝐹𝐹 = 𝐴𝐴 = 𝐴𝐴

𝐴𝐴 63
Digital Design
𝐴𝐴 𝐴𝐴 ≡ 𝐴𝐴 𝐴𝐴
 Example – Bubble Pushing
Implement the following Boolean function using only NOR gates and inverters.

𝐹𝐹 = 𝐴𝐴 � 𝐵𝐵 + 𝐴𝐴 � 𝐶𝐶
AND
Step 1: 𝐴𝐴 � 𝐵𝐵 NOR
Step 2: A
A (add the negation B F
B where needed for
the correct function) A
A C
C 𝐴𝐴 � 𝐶𝐶

redundant... NOR
A
Step 3:
(i) Replace AND gate with NOR gate B F
(ii) balance the bubbles using inverters
to maintain the correct functionality A

C gate count = 7
NOR

64
Digital Design
 Summary
Logic gate is a circuit that implement Boolean operations
AND, NAND, OR, NOR, XOR, XNOR gates
Boolean function implementation using logic gates
Boolean function simplification using algebra postulates and theorems
Timing
Positive and negative logic
◦ Definition
◦ Conversion between positive and negative logic
◦ Gates with mixed logic

Universal Gates

65
Digital Design
EE2026
Digital Design
MODELING STYLES IN VERILOG
Chua Dingjuan elechuad@nus.edu.sg
 Pictorial Summary of Module Structure

Module Covers different

levels of abstraction
Dataflow vs
Behavioral vs
I/O Ports Structural description
interfaces

Continuous assignment always @ (posedge clk)....

Concurrent blocks assign out=(sel)?in0:in1;
Design partitioning
Instances manages hierarchy (sub-
modules), enables modularity
functionality
(reusable) and regularity
(many times)

2
 Recall where we last left off….
module box( input a, b,
input [1:0] c, Net / Variable Number Value in
output [3:0] y ); Name of bits? dec / bin
wire tmp; a 1 1 / 1’b1
reg [1:0] one = 3; b 1 0 / 1’b0
reg two;
c 2 2 / 2’b10
integer three = 1;
tmp 1 Z / 1’bZ
assign y[3] = one[0]; one 2 3 / 2’b11
assign y[2:1] = a + c; two 1 X / 1’bX
assign y[0] = ( a > b ); three 32 1 / 32’h00000001
y 4 15 / 4’b1111
endmodule

Gate Symbol Function Verilog Gate Symbol Function Verilog

(F) Operator (F) Operator
A
AND B
F 𝐴𝐴 � 𝐵𝐵 F=A&B NOT 𝐴𝐴̅ F = ~A
A
OR F 𝐴𝐴 + 𝐵𝐵 F=A|B XOR 𝐴𝐴 ⊕ 𝐵𝐵 F=A^B
B

assign F = ~w & ~x & z | ~w & x & z | w & y & z | x & y & z;

Page 3
 Bad Example 1 – Multi-Driven Net
module notgood Assign statements are used for wire or
(input a,b); net types.

Thus error states that <z> signal should

reg z; be a net type!
assign z = a | b;
endmodule

Page 4
 Continuous Assignment (Dataflow)
assign statements are often used to model combinational logic
A P module bigbox (input a, b, c, d,
B output z);
Q wire p, q, r; internal connections
C Z
assign z = p ^ q ^ r; 1 ∆ ∆
Order? assign q = ~c; 2
D not
not B 1 0
R important assign p = a & b; 3
important
assign r = ~(c | d); 4 P 1 0

endmodule Z 1 0

o Whenever there’s an event on the RHS signal, expression is evaluated and

assigned (∆)  continuously monitored
o Multiple statements can be executed in parallel (concurrently)
o wire is used to represent an internal connection
Page 5
Bad Example 2 – Multi-Driven Net
module notgood(….); There are two conflicting instructions
presented!

assign x = a | b; Signal x is connected to TWO drivers.

Thus, the Multiple Driver Nets error
assign x = a + b; would occur.

endmodule

Page 6
 Useful Operators
o Boolean (bit-wise), logical, arithmetic, concatenation.
o Use brackets for readability, take note if *synthesizable.
Operator Description Examples: a = 4’b1010, b=4’b0000

High !, ~ Logical negation, Bit-wise NOT !a = 0, !b = 1, ~a = 4’b0101, ~b = 4’b1111

&, |, ^ Reduction (Outputs 1-bit) &a = 0, |a=1, ^a = 0
{__,__} Concatenation {b, a} = 8’b00001010
{n{___}} Replication {2 {a} } = 8’b10101010
*, /, %, Multiply, *Divide, *Modulus 3 % 2 = 1, 16 % 4 = 0
Precedence

+, - Binary addition, subtraction a + b = 4’b1010

<< , >> Shift Zeros in Left / Right a << 1 = 4’b0100, a >> 2 = 4’b0010
<, <=, >, >= Logical Relative (1-bit output) (a > b) = 1
==, != Logical Equality (1-bit output) (a == b)= 0 (a != b)= 1
&, ^, | Bit-wise AND, XOR, OR a&b = 4’b0000 a|b = 4’b1010
&&, || Logical AND, OR (1-bit output) a&&b = 0 a||b = 1
Low ?: Conditional Operator <out> = <condition> ? If_ONE : if_ZERO
Page 7
 Conditional Operator…
The ?: conditional operator allows us to select the output
from a set of inputs based on a condition.
module mystery ( input s, input [1:0] d,
output y);
d[0]
y assign y = s ? d[1] : d[0];
d[1]
<output> = <condition> ? If_ONE : If_ZERO
s= 1  y = d[1], s= 0  y= d[0]
s
endmodule

o This expression is evaluated whenever there is an event on any input.

o What is this block? o – 2-1 Multiplexer / MUX!
o Multiplexer also come in 4-1, 8-1, 16-1 configurations!

Page 8
 2

Procedural Assignment : always

Behavioral, higher-level description of logic. d[0]
MUX y
d[1]
2 assignment types : Blocking & Non-Blocking
module mux21( input s, input d[1:0],
output reg y); s
Anything assigned in an always block
must be declared as type reg
always @ (s, d) Conceptually, the always block runs once when
any signal in sensitivity list (s,d) changes value.
begin
if (sel == 1’b0) Statements executed sequentially & evaluated
y= d[0]; instantaneously.  Order matters!
else
y= d[1];

end begin and end behave like

parentheses/brackets for conditional statements.
endmodule
Page 9
Procedural Assignment : always
Behavioral, higher-level description of logic. d[0]
MUX y
d[1]

module mux21( input s, input [1:0] d, s

output reg y);

always @ (s, d)

begin
if (s == 1’b0)
y = d[0];
else
y = d[1];
end

endmodule

Page 10
Some notes on: always
o always@(*) includes all input signals that are read in current block.

o Statements within always block are executed sequentially.

o Variables within sensitivity list are very important!
o if--else if--else, case, for, while can only be used in
procedural assignments (always blocks)
o Multiple always blocks run in parallel, concurrently, watch out for
multi-driven nets and race conditions. (next slide)
o No assign in always blocks!

Registers
o Anything assigned in an always block must be declared as type reg
o In Verilog, the term register (reg) simply means a variable that can
hold a value. (cf. wire)

Page 11
Bad Example 3 – Multi-Driven Net
module notgood(….); There are two conflicting instructions
always @ (*) presented.

y = y + 1; The first instruction would be to

increment y by 1, while the second
instruction would be to increment y by 3.
The compiler would not be able to know
always @ (*) which instruction should be executed.
y = y + 3;
Thus, the Multiple Driver Nets error
would occur.
endmodule

Page 12
Ref – Conditional Statements
If - else if - else case
if ( expr ) case ( expr )
statement;
value1 : statement;
value2 : statement;
if ( expr ) value3 : statement;
statement; ...
else default : statement;
statement;
endcase

if ( expr )
statement;
else if ( expr )
statement;
else if ( expr )
statement;
else
statement;

Page 13
Equivalence
module mux21( input s, input [1:0] d, output reg y);

always @ (s, d)
begin
if (s == 1’b0) d[0]
y= d[0]; MUX y
else d[1]
y= d[1];
end s
endmodule

module mux ( input s, input [1:0] d, output y);

assign y = s ? d[1] : d[0];

endmodule

Page 14
 Equivalence…
A
B

C Z

D
module bigbox module bigbox
(input a,b,c,d, output z); (input a,b,c,d, output ___
reg z);
reg p,q,r;
wire p, q, r; always @ ( a,b,c,d )
begin
assign q = ~c; q = ~c;
assign z = p ^ q ^ r; p = a & b;
assign p = a & b; r = ~(c | d);
assign r = ~(c | d); z = p ^ q ^ r;
end
endmodule endmodule

Page 15
 Structural Modeling – Primitives
Structural modeling can be used to connect multiple modules and gates.
Verilog provides a standard set of primitive such as basic logic gates.
Dataflow
module bigbox (input a,b,c,d, output z);

A assign z = (a & b) ^ ~c ^ ~(c | d) ;

B
endmodule
C Z Structural (using primitives)
module bigbox (input a,b,c,d, output z);
wire p, q, r;
D
and u1 (p, a, b); //output, then inputs
not u2 (q, c);
nor u3 (r, c, d);
xor u4 (z, p, q, r);

endmodule

Page 16
 Structural Modeling
Structural modeling can be used to connect multiple modules via port
connection by name and position.
module mux21( input s, module mux41( input [1:0] s,
input [1:0] d, input [3:0] d,
output y); output y);
… … … ?
assign y = s ? d[1] : d[0];
endmodule
endmodule

mux41
d[3]
mux21
d[1] d[2] y
d[0] y d[1]
d[0]
s
s[1] s[0]
Page 17
 Structural Modeling
For example, a 4-to-1 multiplexer can also be implemented by combining
several 2-to-1 multiplexers. How can we write this in Verilog?

mux21

mux41
d[3] d[1] y
d[3] d[2] d[0] mux21
s
d[2] y d[1]
y y
d[1] s[0]
d[0]
d[0] mux21 s

d[1] d[1] y
d[0] d[0]
s[1] s[0] s

s[0] s[1]

Page 18
 Structural Modeling
For example, a 4-to-1 multiplexer can also be implemented by combining
several 2-to-1 multiplexers.
module mux21( input s, input [1:0] d,
output y);
assign y = s ? d[1] : d[0];
mux21 endmodule
d[3] d[1] out1
y
Port Connection by Position
d[2] d[0] mux21 module mux41( input [1:0] s,
s
d[1] input [3:0] d,
y y output y);
d[0]
s wire out1, out2;
mux21

d[1] d[1] y
//check for port order!
out2 mux21 u1 (s[0], d[3:2], out1);
d[0] d[0]
s mux21 u2 (s[0], d[1:0], out2);

mux21 u3 (s[1], {out1, out2}, y);

s[0] s[1]
endmodule

Page 19
 Structural Modeling
For example, a 4-to-1 multiplexer can also be implemented by combining
several 2-to-1 multiplexers. Port Connection by Name
module mux41( input [1:0] s,
input [3:0] d,
output y);

wire out1, out2;

mux21 u1 (.s ( s[0]),

.d ( d[3:2] ),
.y ( out1 ) );

mux21 u2 (.s ( s[0]),

.d ( d[1:0] ),
.y ( out2) );

mux21 u3 (.s ( s[1]),

.d ( {out1, out2} ),
.y ( y ) );

endmodule

Page 20
 Example - Structural Modeling
o For modular designs, the top design is often specified as interconnected
blocks.
o Two examples below demonstrate port connection by position / name.
module mymodule (input a, b, output x); module yourmodule (input c, d, output z);
... …
endmodule endmodule

ourmodule Port Connection by Name

sw1 a
b
mymodule x led1
module ourmodule (input sw1, sw2,
output led1, led2);
sw2 led2
c
yourmodule z
d
mymodule M1 ( .a (sw1),
.b (sw2),
.x (led1) );
Port Connection by Position
yourmodule M2( .z(led2),
module ourmodule (input sw1, sw2, .c (sw1),
output led1, led2); .d(sw2) );

mymodule M1 (sw1, sw2, led1); endmodule

yourmodule M2 (sw1, sw2, led2);

endmodule

Page 21
Recall Simulation?
module savetheworld (input a1, … z1,
a1 a2
output a2, …,z2); save
the
………. ………. ………. ………. ……….
z1 world z2
………. ………. ………. ………. ………. .v
………. ………. ………. ………. ……….
endmodule

How do we know our design actually works?

o Functional Simulation Verilog Code Test Bench
call module
b1
a1=9;
(Verification) module
………. ………. b1=1; b2
………. ………. //wait for 10u
#10
endmodule b1=0; z2
Method 0 10 20 30
t/µs

o Designer applies input values to the code

o Simulator produces corresponding outputs in truth tables /
timing diagrams
o Simulators usually assume negligible propagation gate delays.
Page 22
 Simulation Testbench Example
mux21
module mux21( input s,
input [1:0] d, d[1]
output y); y
assign y = s ? d[1] : d[0]; d[0]
endmodule

module mux_test(); s
reg [1:0] ip = 0;
mux_test
reg sel = 0;
wire op; mux21

ip
d[1]
mux21 dut (sel, ip, op); y op
2’b10 d[0]
initial begin
ip = 2’b10;
sel = 1’b0; s
#10; //wait 10 time units sel

end 1’b0

endmodule

Page 23
EE2026
Digital Design
MODELING STYLES IN VERILOG
Chua Dingjuan elechuad@nus.edu.sg
Ask Week 3 Questions here…
You can ask questions during the week using
slido here :

https://app.sli.do/event/7Y43tp4vqnHWjDqX
S7FXiA

Or at slido.com + #2026 003

Or the tiny little QR :

Digital Design Page 2

 Pictorial Summary of Module Structure

Module Covers different

levels of abstraction
Dataflow vs
Behavioral vs
I/O Ports Structural description
interfaces

Continuous assignment always @ (posedge clk)....

Concurrent blocks assign out=(sel)?in0:in1;
Design partitioning
Instances manages hierarchy (sub-
modules), enables modularity
functionality
(reusable) and regularity
(many times)

3
Digital Design
 Recall where we last left off….
module box( input a, b,
input [1:0] c, Net / Variable Number Value in
output [3:0] y ); Name of bits? dec / bin
wire tmp; a 1 1 / 1’b1
reg [1:0] one = 3; b 1 0 / 1’b0
reg two;
c 2 2 / 2’b10
integer three = 1;
tmp 1 Z / 1’bZ

assign y[3] = one[0]; one 2 3 / 2’b11

assign y[2:1] = a + c; two 1 X / 1’bX
assign y[0] = ( a > b ); three 32 1 / 32’h00000001
y 4 15 / 4’b1111
endmodule

Gate Symbol Function Verilog Gate Symbol Function Verilog

(F) Operator (F) Operator
A
AND B
F 𝐴𝐴 � 𝐵𝐵 F=A&B NOT 𝐴𝐴̅ F = ~A
A
OR F 𝐴𝐴 + 𝐵𝐵 F=A|B XOR 𝐴𝐴 ⊕ 𝐵𝐵 F=A^B
B

assign F = ~w & ~x & z | ~w & x & z | w & y & z | x & y & z;

Digital Design Page 4
 Bad Example 1 – Wrong Type
module notgood Assign statements are used for wire or
(input a,b); net types.

Thus error states that <z> signal should

reg z; be a net type!
assign z = a | b;
endmodule

Digital Design Page 5

 Continuous Assignment (Dataflow)
assign statements are often used to model combinational logic
A P module bigbox (input a, b, c, d,
B output z);
Q wire p, q, r; internal connections
C Z
assign z = p ^ q ^ r; 1 ∆ ∆
Order? assign q = ~c; 2
D B 1 0
R assign p = a & b; 3
assign r = ~(c | d); 4 P 1 0

endmodule Z 1 0

o Whenever there’s an event on the RHS signal, expression is evaluated and

assigned (∆)  continuously monitored
o Multiple statements can be executed in parallel (concurrently)
o wire is used to represent an internal connection
Digital Design Page 6
Bad Example 2 – Multi-Driven Net
module notgood(….); There are two conflicting instructions
presented!

assign x = a | b; Signal x is connected to TWO drivers.

Thus, the Multiple Driver Nets error
assign x = a + b; would occur.

endmodule

Digital Design Page 9

 Useful Operators
o Boolean (bit-wise), logical, arithmetic, concatenation.
o Use brackets for readability, take note if *synthesizable.
Operator Description Examples: a = 4’b1010, b=4’b0000

High !, ~ Logical negation, Bit-wise NOT !a = , !b = , ~a=4’b , ~b=4’b

&, |, ^ Reduction (Outputs 1-bit) &a = 0, |a=1, ^a = 0
{__,__} Concatenation {b, a} = 8’b
{n{___}} Replication {2 {a} } = 8’b
*, /, %, Multiply, *Divide, *Modulus 3 % 2 = 1, 16 % 4 = 0
Precedence

+, - Binary addition, subtraction a + b = 4’b1010

<< , >> Shift Zeros in Left / Right a << 1 = , a >> 2 = 4’b
<, <=, >, >= Logical Relative (1-bit output) (a > b) =
==, != Logical Equality (1-bit output) (a == b)= (a != b)=
&, ^, | Bit-wise AND, XOR, OR a&b = a|b =
&&, || Logical AND, OR (1-bit output) a&&b = a||b =
Low ?: Conditional Operator <out> = <condition> ? If_ONE : if_ZERO
Digital Design Page 10
 Conditional Operator…
The ?: conditional operator allows us to select the output
from a set of inputs based on a condition.
module mystery ( input s, input [1:0] d,
output y);
d[0]
y assign y = s ? d[1] : d[0];
d[1]
<output> = <condition> ? If_ONE : If_ZERO
s= 1  y = , s= 0  y=
s
endmodule

o This expression is evaluated whenever there is an event on any input.

o What is this block?

Digital Design Page 14

 2

Procedural Assignment : always

Behavioral, higher-level description of logic. d[0]
MUX y
d[1]
2 assignment types : Blocking & Non-Blocking
module mux21( input s, input d[1:0],
output reg y); s
Anything assigned in an always block
must be declared as type reg
always @ (s, d) Conceptually, the always block runs once when
any signal in sensitivity list (s,d) changes value.
begin
if (sel == 1’b0) Statements executed sequentially & evaluated
y= d[0]; instantaneously.  Order matters!
else
y= d[1];

end begin and end behave like

parentheses/brackets for conditional statements.
endmodule
Digital Design Page 16
Some notes on: always
o always@(*) includes all input signals that are read in current block.

o Statements within always block are executed sequentially.

o Variables within sensitivity list are very important!
o if--else if--else, case, for, while can only be used in
procedural assignments (always blocks)
o Multiple always blocks run in parallel, concurrently, watch out for
multi-driven nets and race conditions. (next slide)
o No assign in always blocks!

Registers
o Anything assigned in an always block must be declared as type reg
o In Verilog, the term register (reg) simply means a variable that can
hold a value. (cf. wire)

Digital Design Page 18

Bad Example 3 – Multi-Driven Net
module notgood(….); There are two conflicting instructions
always @ (*) presented.

y = y + 1; The first instruction would be to

increment y by 1, while the second
instruction would be to increment y by 3.
The compiler would not be able to know
always @ (*) which instruction should be executed.
y = y + 3;
Thus, the Multiple Driver Nets error
would occur.
endmodule

Digital Design Page 19

Ref – Conditional Statements
If - else if - else case
if ( expr ) case ( expr )
statement;
value1 : statement;
value2 : statement;
if ( expr ) value3 : statement;
statement; ...
else default : statement;
statement;
endcase

if ( expr )
statement;
else if ( expr )
statement;
else if ( expr )
statement;
else
statement;

Digital Design Page 20

Equivalence
module mux21( input s, input [1:0] d, output reg y);

always @ (s, d)
begin
if (s == 1’b0) d[0]
y= d[0]; MUX y
else d[1]
y= d[1];
end s
endmodule

module mux ( input s, input [1:0] d, output y);

assign y = s ? d[1] : d[0];

endmodule

Digital Design Page 21

 Equivalence…
A P
B
Q
C Z

D R
module bigbox module bigbox
(input a,b,c,d, output z); (input a,b,c,d, output ___ z);

wire p, q, r; always @ ( )
begin
assign q = ~c;
assign z = p ^ q ^ r;
assign p = a & b;
assign r = ~(c | d);
end
endmodule endmodule
Digital Design Page 22
 Structural Modeling – Primitives
Structural modeling can be used to connect multiple modules and gates.
Verilog provides a standard set of primitive such as basic logic gates.
Dataflow
module bigbox (input a,b,c,d, output z);

A assign z = (a & b) ^ ~c ^ ~(c | d) ;

B
endmodule
C Z Structural (using primitives)
module bigbox (input a,b,c,d, output z);
wire p, q, r;
D
and u1 (p, a, b); //output, then inputs
not u2 ( );
Fill in this! nor u3 ( );
 xor u4 ( );

endmodule

Digital Design Page 24

 Structural Modeling
Structural modeling can be used to connect multiple modules via port
connection by name and position.
module mux21( input s, module mux41( input [1:0] s,
input [1:0] d, input [3:0] d,
output y); output y);
… … … ?
assign y = s ? d[1] : d[0];
endmodule
endmodule

mux41
d[3]
mux21
d[1] d[2] y
d[0] y d[1]
d[0]
s
s[1] s[0]
Digital Design Page 26
 Structural Modeling
For example, a 4-to-1 multiplexer can also be implemented by combining
several 2-to-1 multiplexers. How can we write this in Verilog?

mux21

mux41
d[3] d[1] y
d[3] d[2] d[0] mux21
s
d[2] y d[1]
y y
d[1] s[0]
d[0]
d[0] mux21 s

d[1] d[1] y
d[0] d[0]
s[1] s[0] s

s[0] s[1]

Digital Design Page 27

 Structural Modeling
For example, a 4-to-1 multiplexer can also be implemented by combining
several 2-to-1 multiplexers.
module mux21( input s, input [1:0] d,
output y);
assign y = s ? d[1] : d[0];
mux21 endmodule
d[3] d[1] out1
y
Port Connection by Position
d[2] d[0] mux21 module mux41( input [1:0] s,
s
d[1] input [3:0] d,
y y output y);
d[0]
s wire out1, out2;
mux21

d[1] d[1] y
//check for port order!
out2 mux21 u1 (s[0], d[3:2], out1);
d[0] d[0]
s mux21 u2 ( );

mux21 u3 ( );
s[0] s[1]
endmodule

Digital Design Page 28

 Structural Modeling
For example, a 4-to-1 multiplexer can also be implemented by combining
several 2-to-1 multiplexers. Port Connection by Name
module mux41( input [1:0] s,
input [3:0] d,
output y);

wire out1, out2;

mux21 u1 (.s ( s[0]),

.d ( d[3:2] ),
.y ( out1 ) );

mux21 u2 (.s ( s[0]),

.d ( d[1:0] ),
.y ( out2) );

mux21 u3 (.s ( s[1]),

.d ( {out1, out2} ),
.y ( y ) );

endmodule

Digital Design Page 31

 Example - Structural Modeling
o For modular designs, the top design is often specified as interconnected
blocks.
o Two examples below demonstrate port connection by position / name.
module mymodule (input a, b, output x); module yourmodule (input c, d, output z);
... …
endmodule endmodule

ourmodule Port Connection by Name

sw1 a
b
mymodule x led1
module ourmodule (input sw1, sw2,
output led1, led2);
sw2 led2
c
yourmodule z
d
mymodule M1 ( .a (sw1),
.b (sw2),
.x (led1) );
Port Connection by Position
yourmodule M2( .z(led2),
module ourmodule (input sw1, sw2, .c (sw1),
output led1, led2); .d(sw2) );

mymodule M1 (sw1, sw2, led1); endmodule

yourmodule M2 (sw1, sw2, led2);

endmodule

Digital Design Page 32

Recall Simulation?
module savetheworld (input a1, … z1,
a1 a2
output a2, …,z2); save
the
………. ………. ………. ………. ……….
z1 world z2
………. ………. ………. ………. ………. .v
………. ………. ………. ………. ……….
endmodule

How do we know our design actually works?

o Functional Simulation Verilog Code Test Bench
call module
b1
a1=9;
(Verification) module
………. ………. b1=1; b2
………. ………. //wait for 10u
#10
endmodule b1=0; z2
Method 0 10 20 30
t/µs

o Designer applies input values to the code

o Simulator produces corresponding outputs in truth tables /
timing diagrams
o Simulators usually assume negligible propagation gate delays.
Digital Design Page 33
 Simulation Testbench Example
mux21
module mux21( input s,
input [1:0] d, d[1]
output y); y
assign y = s ? d[1] : d[0]; d[0]
endmodule

module mux_test(); s
reg [1:0] ip = 0;
mux_test
reg sel = 0;
wire op; mux21

ip
d[1]
mux21 dut (sel, ip, op); y op
2’b10 d[0]
initial begin
ip = 2’b10;
sel = 1’b0; s
#10; //wait 10 time units sel

end 1’b0

endmodule

Digital Design Page 34

EE2026
Digital Design
LOGIC MINIMIZATION, KARNAUGH MAPS
Chua Dingjuan elechuad@nus.edu.sg
Ask Week 4 Questions here…
You can ask questions during the week using
slido here :

https://app.sli.do/event/ePPnicViz9oMHb8N
AWu4WX

Or at slido.com + #2026 004

Or the tiny little QR :

Digital Design Page 2

 In Lab 1… Design Workflow!
idea! .v (verilog)
assign LED1 = (A & ~B) | (A & B);

Synthesized Schematic
RTL Schematic

Simulation Results .xdc (Constraints Mapping) .bit (Bitstream)

Digital Design Page 3

LOGIC MINIMIZATION
Karnaugh Maps
Gate-Level Logic Design
Step 1 (simplify the Boolean function)
◦ Simplify the Boolean function to be implemented
◦ Methods of simplification
◦ Postulates and theorem
◦ Karnaugh Map

Step 2
◦ Implement the simplified Boolean function using logic gates
◦ Minimize the gate counts

Why minimization?
◦ Cost, power, performance, size, reliability, …

5
Digital Design
 Karnaugh Map (K-Map)
K-map is a diagram that consists of a number of squares
Each square represent one minterm (or maxterm) of a Boolean function
The Boolean function (SOP) can be expressed as a sum of minterms in the map
n-variables Boolean function has maximum 2n minterms

Two-variable K-map: m0 → 00 → 𝐴 𝐵
(maximum 4 minterms) m1 → 01 → 𝐴 𝐵
m2 → 10 → 𝐴 𝐵
B squares B B m3 → 11 → 𝐴𝐵
A 𝐵ത B A 0 1 0 1
A
𝐴ҧ 𝐴ҧ𝐵ത ҧ
𝐴𝐵 0 00 01 0 m0 m1

A 𝐴𝐵ത 𝐴𝐵 1 10 11 1 m2 m3

“0” → Literal with overbar

“1” → Literal without overbar

6
Digital Design
Truth table → K-map

A B F B
0 0 0 A 0 1
0 1 0 0 0 0
1 0 1
1 1 1
1 1 1

oK – map is a two-dimensional truth table

oEach row of truth table corresponds to one square in the k-map
oIf the term in a row is a minterm of the function (F=1), place a “1” in the
corresponding square of the K-map, otherwise (maxterm), place a “0”.

7
Digital Design
 Three- and four-Variable K-Maps
*Note that any two adjacent squares differ by only one literal

Three-variable K-map Four-variable K-map

BC
𝐵ത 𝐶ҧ ത
𝐵𝐶 𝐵𝐶 𝐵 𝐶ҧ CD
A 00 01 11 10
AB
𝐴ҧ 𝐴ҧ 𝐵ത 𝐶ҧ 𝐴ҧ𝐵𝐶
ത ҧ
𝐴𝐵𝐶 ҧ 𝐶ҧ
𝐴𝐵 00 0000 0001 0011 0010
𝐴 𝐴𝐵ത 𝐶ҧ ത
𝐴𝐵𝐶 𝐴𝐵𝐶 𝐴𝐵 𝐶ҧ 01 0100 0101 0111 0110

BC 11 1100 1101 1111 1110

00 01 11 10
A 10 1000 1001 1011 1010
0 000 001 011 010

1 100 101 111 110

CD
00 01 11 10
AB
BC 00 m0 m1 m3 m2
A 00 01 11 10 01 m4 m5 m7 m6
0 m0 m1 m3 m2 11 m12 m13 m15 m14
1 m4 m5 m7 m6 10 m8 m9 m11 m10
8
Digital Design
 Boolean function in K-map
Represent the following functions on K-map:

𝐹 = 𝐴𝐵 + 𝐴𝐵 + 𝐴𝐵ത

B Write the Boolean expression

0 1
A for the function in K-map:
0
B
1 0 1
A
0 0 1
Place a “1” in the square that represents
a minterm in the given function 1 1 0

𝑭 =?
in SOP: write F as sum of the minterms
(squares with “1”)

9
Digital Design
 Ex - Boolean function in K-map (cont.)
Represent the following function on K-map: Write the Boolean expression
𝐹 = 𝐴𝐵𝐶 + 𝐴𝐵 𝐶ҧ + 𝐴ҧ𝐵𝐶
ത + 𝐴ҧ𝐵ത 𝐶ҧ for the function in K-map:
BC
BC A 00 01 11 10
A 00 01 11 10
0 1 0 0 0
0 1 1 1 0
1 0 1 0 0
1 0 0 0 1

ҧ 𝐶𝐷
ҧ + 𝐴ҧ𝐵𝐶𝐷
𝑭 =? 𝑭 = 𝐴 ⋅ 𝐵 ⋅ 𝐶 + 𝐴 ⋅ 𝐵ത ⋅ 𝐶
𝐹 = 𝐴𝐵 ത + 𝐴𝐵 𝐶ҧ 𝐷
ഥ + 𝐴ҧ𝐵𝐶
ത 𝐷ഥ
ത 𝐷
+𝐴𝐵𝐶 ഥ + 𝐴𝐵𝐶𝐷
ത + 𝐴𝐵ത 𝐶𝐷ҧ + 𝐴ҧ𝐵ത 𝐶ҧ 𝐷
ഥ
CD 00 01 11 10
CD 00 01 11 10 AB
AB 00 0 1 0 0
00 1 0 1 1 01 0 0 0 1
01 0 1 0 0 11 0 1 0 0
11 1 0 0 0 10 0 0 0 0
10 0 1 1 1
𝑭 =? 𝑭 = 𝐴. 𝐵. 𝐶. 𝐷 + 𝐴𝐵𝐶𝐷 + 𝐴𝐵𝐶𝐷

10
Digital Design
 Boolean function in K-map (cont.)
What about Boolean function in non-canonical form?

Example-1: Example-2:

𝐹 = 𝐴𝐵 + 𝐴𝐵 𝐶ҧ + 𝐴ҧ𝐵𝐶
ത 𝐹 = A + 𝐴ҧ𝐵𝐶𝐷
ത + 𝐵 𝐶ҧ 𝐷
ഥ
CD 00 01 11 10
𝐴𝐵 = 𝐴𝐵 𝐶 + 𝐶 = 𝐴𝐵𝐶 + 𝐴𝐵𝐶 AB
00
BC 01
A 00 01 11 10
0 11

1 10

Or 𝐴𝐵 → 1 for 𝐶 = 0 𝑜𝑟 1
or just fill the truth table and derive the K-map

11
Digital Design
 Boolean function simplification
using K-map
Boolean function (SOP) simplification using K-map

Simplify: 𝐹 = 𝐴ҧ𝐵ത + 𝐴𝐵 + 𝐴𝐵
Minimum Sum of
𝐴𝐵 + 𝐴ҧ𝐵ത = 𝐴 𝐵 + 𝐵ത = 𝐴 Products
B
A 0 1 eliminated MSOP:
𝐹 =𝐴+𝐵
0 1 1

1 0 1
𝐴𝐵 + 𝐴𝐵 = 𝐵 𝐴ҧ + 𝐴 = 𝐵
2-cell group
eliminated
Alternatively,
𝐹 = 𝐴𝐵 + 𝐴𝐵 + 𝐴ҧ𝐵ത *The variable that changes value in the
= 𝐴ҧ + 𝐴𝐵 group is eliminated, or the variable that
= 𝐴ҧ + 𝐵 doesn’t change value in the group remains

12
Digital Design
 How do we find
MSOP using
Kmaps?

Digital Design Page 13

 Minimization (MSOP) using K-Map
(cont.)
*** K-Map Grouping Rules *** :
• Group all squares that contains “1”.
• Groups must be either horizontal or vertical (diagonal is invalid), but can wrap
around edges of the map.
• Group size is always 2n , that is, 2, 4, 8, …
• Group should be as large as possible (contains as many as squares with “1” as
possible)
• Simplified term retains variables that don’t change value.
• A 1 in may be circled multiple times if doing so allows fewer circles to be used.
• Minimum essential number of groupings to cover all the “1”s.
Four-variables: ഥ
𝐷 𝐵
CD 00 01 11 10
𝐹 = 𝐴ҧ𝐵ത 𝐶ҧ 𝐷
ഥ + 𝐴ҧ𝐵𝐶
ത 𝐷 ҧ 𝐶ҧ 𝐷
ഥ + 𝐴𝐵 ഥ + 𝐴𝐵ҧ 𝐶𝐷
ҧ AB
ҧ ҧ 𝐷ഥ + 𝐴𝐵 𝐶ҧ 𝐷ഥ + 𝐴𝐵 𝐶𝐷ҧ 00 1 0 0 1
+𝐴𝐵𝐶𝐷 + 𝐴𝐵𝐶
+𝐴𝐵𝐶𝐷 + 𝐴𝐵𝐶 𝐷 ഥ + 𝐴𝐵ത 𝐶ҧ 𝐷
ഥ + 𝐴𝐵𝐶
ത 𝐷 ഥ 01 1 1 1 1
11 1 1 1 1
𝐹𝑀𝑆𝑂𝑃 = 𝐵 + 𝐷 10 1 0 0 1

14
Digital Design
 Three-variables: Application Time!
𝐹 = 𝐴ҧ𝐵ത 𝐶ҧ + 𝐴ҧ𝐵𝐶 ҧ 𝐶ҧ + 𝐴𝐵 𝐶ҧ
ത + 𝐴𝐵𝐶 + 𝐴𝐵 𝐹 = 𝐴ҧ𝐵𝐶
ത + 𝐴𝐵ത 𝐶ҧ + 𝐴𝐵𝐶
ത + 𝐴ҧ𝐵ത 𝐶ҧ + 𝐴𝐵
ҧ 𝐶ҧ
BC BC
A
00 01 11 10 00 01 11 10
A
0 1 1 1 1 0 1 1 0 1

1 0 0 0 1 1 1 1 0 0

𝐹𝑀𝑆𝑂𝑃 = 𝐹𝑀𝑆𝑂𝑃 =
Four-variables:
𝐹 = 𝐴ҧ𝐵ത 𝐶ҧ 𝐷
ഥ + 𝐴ҧ𝐵𝐶𝐷
ത ҧ 𝐶𝐷
+ 𝐴𝐵 ҧ + 𝐴𝐵𝐶𝐷
ҧ 𝐹 = 𝐴ҧ𝐵ത 𝐶ҧ 𝐷
ഥ + 𝐴ҧ𝐵𝐶
ത 𝐷 ҧ 𝐶𝐷
ഥ + 𝐴𝐵 ҧ + 𝐴𝐵𝐶𝐷
ҧ
+𝐴𝐵 𝐶𝐷 ҧ + 𝐴𝐵𝐶𝐷 + 𝐴𝐵ത 𝐶ҧ 𝐷
ഥ + 𝐴𝐵𝐶𝐷
ത +𝐴𝐵 𝐶𝐷 ҧ + 𝐴𝐵𝐶𝐷 + 𝐴𝐵ത 𝐶ҧ 𝐷
ഥ + 𝐴𝐵𝐶
ത 𝐷
ഥ

CD 00 CD 00 01 11 10
01 11 10 AB
AB 00 1 0 0 1
00 1 0 1 0
01 0 1 1 0 01 0 1 1 0

11 0 1 1 0 11 0 1 1 0

10 1 0 1 0 10 1 0 0 1

𝐹𝑀𝑆𝑂𝑃 = 𝐹𝑀𝑆𝑂𝑃 =
Digital Design 15
 Boolean function (SOP) simplification
using K-Map (cont.)
Three-variables: 𝐴ҧ (B and C eliminated)
BC
A
00 01 11 10
𝐹 = 𝐴ҧ𝐵ത 𝐶ҧ + 𝐴ҧ𝐵𝐶 ҧ 𝐶ҧ + 𝐴𝐵 𝐶ҧ
ത + 𝐴𝐵𝐶 + 𝐴𝐵
0 1 1 1 1

𝐹 = 𝐴ҧ + 𝐵 𝐶ҧ 1 0 0 0 1

𝐴ҧ𝐵ത 𝐶ҧ + 𝐴ҧ𝐵𝐶 ҧ 𝐶ҧ → 𝐴ҧ𝐵ത 𝐶ҧ + 𝐶 + 𝐴𝐵 𝐶 + 𝐶ҧ

ത + 𝐴𝐵𝐶 + 𝐴𝐵
→ 𝐴ҧ𝐵ത + 𝐴𝐵 → 𝐴ҧ 𝐵ത + 𝐵 → 𝐴ҧ
𝐵 𝐶ҧ (A eliminated)
ҧ 𝐶ҧ + 𝐴𝐵𝐶→
𝐴𝐵 ҧ 𝐴ҧ + 𝐴 𝐵 𝐶→𝐵
ҧ 𝐶ҧ
𝐵ത (A and C eliminated)
𝐹 = 𝐴ҧ𝐵𝐶
ത + 𝐴𝐵ത 𝐶ҧ + 𝐴𝐵𝐶
ത + 𝐴ҧ𝐵ത 𝐶ҧ + 𝐴𝐵
ҧ 𝐶ҧ BC
A
00 01 11 10

𝐹 = 𝐵ത + 𝐴ҧ𝐶ҧ 0 1 1 0 1
𝐴ҧ𝐵𝐶
ത + 𝐴𝐵ത 𝐶ҧ + 𝐴𝐵𝐶
ത + 𝐴ҧ𝐵ത 𝐶ҧ → 𝐴ҧ𝐵ത 𝐶 + 𝐶ҧ + 𝐴𝐵ത 𝐶ҧ + 𝐶
𝐴ҧ + 𝐴 𝐵ത → 𝐵ത 1 1 1 0 0
𝐴ҧ𝐵ത 𝐶ҧ + 𝐴𝐵
ҧ 𝐶ҧ → 𝐴ҧ 𝐵ത + 𝐵 𝐶ҧ → 𝐴ҧ𝐶ҧ
𝐴ҧ𝐶ҧ (B is eliminated)
Group the adjacent cells where only one variable changes 16
Digital Design
value so that it can be eliminated
 Minimization (MSOP) using K-Map
(cont.)
Four-variables: 𝐵ത 𝐶ҧ 𝐷
ഥ 𝐵𝐷 𝐶𝐷
CD 00 01 11 10
𝐹 = 𝐴ҧ𝐵ത 𝐶ҧ 𝐷
ഥ + 𝐴ҧ𝐵𝐶𝐷
ത ҧ 𝐶𝐷
+ 𝐴𝐵 ҧ + 𝐴𝐵𝐶𝐷
ҧ AB
ҧ + 𝐴𝐵𝐶𝐷 + 𝐴𝐵ത 𝐶ҧ 𝐷
ഥ + 𝐴𝐵𝐶𝐷
ത 00 1 0 1 0
+𝐴𝐵 𝐶𝐷
01 0 1 1 0
11 0 1 1 0
𝐹𝑀𝑆𝑂𝑃 = 𝐵ത 𝐶ҧ 𝐷
ഥ + 𝐵𝐷 + 𝐶𝐷
1 0 1 0
10

𝐵ത 𝐷
ഥ 𝐵𝐷
CD 00 01 11 10
𝐹 = 𝐴ҧ𝐵ത 𝐶ҧ 𝐷
ഥ + 𝐴ҧ𝐵𝐶
ത 𝐷 ҧ 𝐶𝐷
ഥ + 𝐴𝐵 ҧ + 𝐴𝐵𝐶𝐷
ҧ AB
+𝐴𝐵 𝐶𝐷 ҧ + 𝐴𝐵𝐶𝐷 + 𝐴𝐵ത 𝐶ҧ 𝐷
ഥ + 𝐴𝐵𝐶
ത 𝐷
ഥ 00 1 0 0 1
01 0 1 1 0
11 0 1 1 0
𝐹𝑀𝑆𝑂𝑃 = 𝐵ത 𝐷
ഥ + 𝐵𝐷
10 1 0 0 1

17
Digital Design
 Minimization (MPOS) using K-Map
maxterm-input correspondence: complement literals if 1
Boolean function in POS:
CD 00 01 11 10 𝐶ҧ + 𝐷
ഥ
𝐹 = 𝐴+𝐵+𝐶+𝐷 𝐴+𝐵+𝐶+𝐷 ҧ AB
𝐴 + 𝐵ത + 𝐶 + 𝐷 𝐴 + 𝐵ത + 𝐶ҧ + 𝐷 00 1 0 1 0
𝐴ҧ + 𝐵ത + 𝐶 + 𝐷 𝐴ҧ + 𝐵ത + 𝐶ҧ + 𝐷 01 0 1 1 0
(𝐴ҧ + 𝐵 + 𝐶 + 𝐷)(
ഥ 𝐴ҧ + 𝐵 + 𝐶ҧ + 𝐷)
11 0 1 1 0
10 1 0 1 0
ഥ ⋅ 𝐶ҧ + 𝐷 ⋅ (𝐵ത + 𝐷)
𝐹𝑀𝑃𝑂𝑆 = 𝐵 + 𝐶 + 𝐷
𝐴+𝐵+𝐶+𝐷 ഥ ⋅ 𝐴ҧ + 𝐵 + 𝐶 + 𝐷
ഥ
POS simplification using K-map: = 𝐴𝐴ҧ + 𝐴 ⋅ 𝐵 + 𝐶 + 𝐷ഥ
+ 𝐵+𝐶+𝐷 ഥ ⋅ 𝐴ҧ + 𝐵 + 𝐶 + 𝐷
ഥ
Group the squares that only contains “0”
⋅ 𝐵+𝐶+𝐷 ഥ = 𝐵+𝐶+𝐷 ഥ
Form an OR term (sum) for each group, instead of a product
Value “1”, instead of “0”, represent complement of the variable
Follow similar grouping rules for SOP
Either SOP or POS can be used to implement the Boolean function, depending on which gives
more efficient implementation.
summarizing: proceed as SOP, but group 0’s instead of 1’s (square = maxterm)
+ complement the values in row-col. to find maxterm associated with square
Digital Design
18
 Invalid groupings

Two variable change value

CD 00 01 11 10 CD 00 01 11 10
AB AB
00 1 0 1 0 00 0 1 0 1
01 0 1 1 0 01 1 0 0 1
11 0 1 1 0 11 0 1 1 1
10 1 0 1 0 10 0 1 1 1

Squares in the group are not in power of two not horizontal or vertical

19
Digital Design
Application Example - Boolean
Function Simplification
𝐹 𝑎, 𝑏, 𝑐, 𝑑 = 𝑎𝑏𝑐ҧ + 𝑎𝑏𝑐 + 𝑏𝑐𝑑 + 𝑎𝑐𝑑 ത
ത + 𝑎𝑏𝑐𝑑
= 𝑎𝑏 𝑐ҧ + 𝑐 + 𝑏𝑐𝑑 + 𝑎𝑐𝑑ത + 𝑎𝑏𝑐𝑑ത (𝐴 + 𝐴ҧ = 1)
= 𝑎 𝑏 + 𝑏ത 𝑐𝑑 ҧ + 𝑏𝑐𝑑 + 𝑎𝑐𝑑
ത (𝐴 + 𝐴ҧ ∙ 𝐵 = 𝐴 + 𝐵)
= 𝑎 𝑏 + 𝑐𝑑 ҧ + 𝑏𝑐𝑑 + 𝑎𝑐𝑑
ത
= 𝑎𝑏 + 𝑎ത 𝑐𝑑 + 𝑏 𝑐𝑑 + 𝑎𝑐𝑑 ҧ (𝐴𝐵 + 𝐴𝐶 ҧ + 𝐵𝐶 = 𝐴𝐵 + 𝐴𝐶)
ҧ - consensus
= 𝑎𝑏 + 𝑎𝑐𝑑
ത + 𝑎𝑐𝑑 ҧ

Find MSOP using K-Map :

20
Digital Design
Design Example - 7-Seg Decoder
A 7-segment display decoder takes a 4-bit input, D3:0, and produces seven outputs to
control LEDs, to display a digit from 0 to 9. The LEDs are named a through g, or Sa – Sg.
Write a truth table for the output Sa and derive
D3 D2 D1 D0 Sa
the MSOP.
0 0 0 0 1
You may assume illegal input values (10–15) will
0 0 0 1 0
never appear and use don’t cares.
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1
1 0 1 0 X
1 0 1 1 X
1 1 0 0 X
1 1 0 1 X
1 1 1 0 X
Digital Design
1 1 1 1 Page 21 X
 Design Example - 7-Seg Decoder
00 01 11 10
00
01 𝑆𝑎 =
11
10

oWe often assume that all combinations of input are valid (e.g. 3 inputs = 8
different input combinations that makes the function equal to 0 or 1)
oThere are applications in which some variable combinations never appear.
oThese conditions are called don’t-care conditions.
oDon’t-care condition is marked with “X” in K-map
oFor minimization, X can take either “1” or “0”.
Digital Design Page 22
 Design Example - 7-Seg Decoder
D3D2
D1D0 00 01 11 10 𝑫𝟐 . 𝑫𝟎
00 1 0 X 1
01 0 1 X 1 𝑆𝑎 = 𝐷2 𝐷0 + 𝐷2 𝐷0 + 𝐷1 + 𝐷3
𝑫𝟑
11 1 1 X X
10 1 1 X X
𝑫𝟏
𝑫 𝟐 . 𝑫𝟎
oWe often assume that all combinations of input are valid (e.g. 3 inputs = 8
different input combinations that makes the function equal to 0 or 1)
oThere are applications in which some variable combinations never appear.
oThese conditions are called don’t-care conditions.
oDon’t-care condition is marked with “X” in K-map
oFor minimization, every X can take either “1” or “0”.
Digital Design Page 23
EE2026
Digital Design
LOGIC MINIMIZATION, KARNAUGH MAPS
Chua Dingjuan elechuad@nus.edu.sg
 In Lab 1… Design Workflow!
idea! .v (verilog)
assign LED1 = (A & ~B) | (A & B);

Synthesized Schematic
RTL Schematic

Simulation Results .xdc (Constraints Mapping) .bit (Bitstream)

Page 2
LOGIC MINIMIZATION
Karnaugh Maps
Gate-Level Logic Design
Step 1 (simplify the Boolean function)
◦ Simplify the Boolean function to be implemented
◦ Methods of simplification
◦ Postulates and theorem
◦ Karnaugh Map

Step 2
◦ Implement the simplified Boolean function using logic gates
◦ Minimize the gate counts

Why minimization?
◦ Cost, power, performance, size, reliability, …

4
 Karnaugh Map (K-Map)
K-map is a diagram that consists of a number of squares
Each square represent one minterm (or maxterm) of a Boolean function
The Boolean function (SOP) can be expressed as a sum of minterms in the map
n-variables Boolean function has maximum 2n minterms

Two-variable K-map: m0  00  𝐴𝐴 𝐵𝐵
(maximum 4 minterms) m1  01  𝐴𝐴 𝐵𝐵
m2  10  𝐴𝐴 𝐵𝐵
B squares B B m3  11  𝐴𝐴𝐴𝐴
A 𝐵𝐵� B A 0 1 0 1
A
𝐴𝐴̅ 𝐴𝐴̅𝐵𝐵� ̅
𝐴𝐴𝐵𝐵 0 00 01 0 m0 m1

A 𝐴𝐴𝐵𝐵� 𝐴𝐴𝐵𝐵 1 10 11 1 m2 m3

“0”  Literal with overbar

“1”  Literal without overbar

5
Truth table  K-map

A B F B
0 0 0 A 0 1
0 1 0 0 0 0
1 0 1
1 1 1
1 1 1

oK – map is a two-dimensional truth table

oEach row of truth table corresponds to one square in the k-map
oIf the term in a row is a minterm of the function (F=1), place a “1” in the
corresponding square of the K-map, otherwise (maxterm), place a “0”.

6
 Three- and four-Variable K-Maps
*Note that any two adjacent squares differ by only one literal

Three-variable K-map Four-variable K-map

BC
𝐵𝐵� 𝐶𝐶̅ �
𝐵𝐵𝐶𝐶 𝐵𝐵𝐶𝐶 𝐵𝐵𝐶𝐶̅ CD
A 00 01 11 10
AB
𝐴𝐴̅ 𝐴𝐴̅𝐵𝐵� 𝐶𝐶̅ 𝐴𝐴̅𝐵𝐵𝐶𝐶
� ̅
𝐴𝐴𝐵𝐵𝐶𝐶 ̅ 𝐶𝐶̅
𝐴𝐴𝐵𝐵 00 0000 0001 0011 0010
𝐴𝐴 𝐴𝐴𝐵𝐵� 𝐶𝐶̅ �
𝐴𝐴𝐵𝐵𝐶𝐶 𝐴𝐴𝐵𝐵𝐵𝐵 𝐴𝐴𝐵𝐵𝐶𝐶̅ 01 0100 0101 0111 0110

BC 11 1100 1101 1111 1110

00 01 11 10
A 10 1000 1001 1011 1010
0 000 001 011 010

1 100 101 111 110 CD

00 01 11 10
AB
BC 00 m0 m1 m3 m2
A 00 01 11 10 01 m4 m5 m7 m6
0 m0 m1 m3 m2 11 m12 m13 m15 m14
1 m4 m5 m7 m6 10 m8 m9 m11 m10
7
 Boolean function in K-map
Represent the following functions on K-map:

𝐹𝐹 = 𝐴𝐴𝐵𝐵 + 𝐴𝐴𝐴𝐴 + 𝐴𝐴𝐵𝐵�

B Write the Boolean expression

0 1
A for the function in K-map:
0 0 1
B
1 1 1 0 1
A
0 0 1
Place a “1” in the square that represents
a minterm in the given function 1 1 0

𝑭𝑭 =?
in SOP: write F as sum of the minterms
(squares with “1”)

𝑭𝑭 = 𝐴𝐴𝐵𝐵 + 𝐴𝐴𝐵𝐵�

8
 Ex - Boolean function in K-map (cont.)
Represent the following function on K-map: Write the Boolean expression
𝐹𝐹 = 𝐴𝐴𝐵𝐵𝐵𝐵 + 𝐴𝐴𝐴𝐴𝐶𝐶̅ + 𝐴𝐴̅𝐵𝐵𝐶𝐶
� + 𝐴𝐴̅𝐵𝐵� 𝐶𝐶̅ for the function in K-map:
BC
BC A 00 01 11 10
A 00 01 11 10
0 1 0 0 0
0 1 1 1 0
1 0 1 0 0
1 0 0 0 1

̅ 𝐶𝐶𝐷𝐷
̅ + 𝐴𝐴̅𝐵𝐵𝐶𝐶𝐶𝐶
𝑭𝑭 =? 𝑭𝑭 = 𝐴𝐴 ⋅ 𝐵𝐵 ⋅ 𝐶𝐶 + 𝐴𝐴 ⋅ 𝐵𝐵� ⋅ 𝐶𝐶
𝐹𝐹 = 𝐴𝐴𝐵𝐵 � + 𝐴𝐴𝐴𝐴 𝐶𝐶̅ 𝐷𝐷
� + 𝐴𝐴̅𝐵𝐵𝐶𝐶
� 𝐷𝐷�
� 𝐷𝐷
+𝐴𝐴𝐵𝐵𝐶𝐶 � + 𝐴𝐴𝐵𝐵𝐶𝐶𝐶𝐶
� ̅ + 𝐴𝐴̅𝐵𝐵� 𝐶𝐶̅ 𝐷𝐷
+ 𝐴𝐴𝐵𝐵� 𝐶𝐶𝐷𝐷 �
CD 00 01 11 10
CD 00 01 11 10 AB
00 0 1 0 0
AB
00 1 0 1 1 01 0 0 0 1
01 0 1 0 0 11 0 1 0 0
11 1 0 0 0 10 0 0 0 0
10 0 1 1 1
𝑭𝑭 =? 𝑭𝑭 = 𝐴𝐴. 𝐵𝐵. 𝐶𝐶. 𝐷𝐷 + 𝐴𝐴𝐵𝐵𝐵𝐵𝐷𝐷 + 𝐴𝐴𝐴𝐴𝐶𝐶𝐷𝐷

9
 Boolean function in K-map (cont.)
What about Boolean function in non-canonical form?

Example-1: Example-2:

𝐹𝐹 = 𝐴𝐴𝐵𝐵 + 𝐴𝐴𝐴𝐴𝐶𝐶̅ + 𝐴𝐴̅𝐵𝐵𝐶𝐶

� 𝐹𝐹 = A + 𝐴𝐴̅𝐵𝐵𝐶𝐶𝐶𝐶
� + 𝐵𝐵 𝐶𝐶̅ 𝐷𝐷
�
CD 00 01 11 10
𝐴𝐴𝐵𝐵 = 𝐴𝐴𝐵𝐵 𝐶𝐶 + 𝐶𝐶 = 𝐴𝐴𝐵𝐵𝐶𝐶 + 𝐴𝐴𝐵𝐵𝐶𝐶 AB
00 1
BC 01 1
A 00 01 11 10
0 0 1 1 1 11 1 1 1 1
1 0 0 0 1 10 1 1 1 1

Or 𝐴𝐴𝐵𝐵  1 for 𝐶𝐶 = 0 𝑜𝑜𝑜𝑜 1

or just fill the truth table and derive the K-map

10
 Boolean function simplification
using K-map
Boolean function (SOP) simplification using K-map

Simplify: 𝐹𝐹 = 𝐴𝐴̅𝐵𝐵� + 𝐴𝐴𝐵𝐵 + 𝐴𝐴𝐴𝐴

Minimum Sum of
𝐴𝐴𝐵𝐵 + 𝐴𝐴̅𝐵𝐵� = 𝐴𝐴 𝐵𝐵 + 𝐵𝐵� = 𝐴𝐴 Products
B
A 0 1 eliminated MSOP:
𝐹𝐹 = 𝐴𝐴 + 𝐵𝐵
0 1 1

0 1
𝐴𝐴𝐵𝐵 + 𝐴𝐴𝐴𝐴 = 𝐵𝐵 𝐴𝐴̅ + 𝐴𝐴 = 𝐵𝐵
2-cell group 1
eliminated
Alternatively,
𝐹𝐹 = 𝐴𝐴𝐵𝐵 + 𝐴𝐴𝐴𝐴 + 𝐴𝐴̅𝐵𝐵� *The variable that changes value in the
= 𝐴𝐴̅ + 𝐴𝐴𝐴𝐴 group is eliminated, or the variable that
= 𝐴𝐴̅ + 𝐵𝐵 doesn’t change value in the group remains

11
 Minimization (MSOP) using K-Map
(cont.)
*** K-Map Grouping Rules *** :
• Group all squares that contains “1”.
• Groups must be either horizontal or vertical (diagonal is invalid), but can wrap
around edges of the map.
• Group size is always 2n , that is, 2, 4, 8, …
• Group should be as large as possible (contains as many as squares with “1” as
possible)
• Simplified term retains variables that don’t change value.
• A 1 in may be circled multiple times if doing so allows fewer circles to be used.
• Minimum essential number of groupings to cover all the “1”s.
Four-variables: �
𝐷𝐷 𝐵𝐵
CD 00 01 11 10
𝐹𝐹 = 𝐴𝐴̅𝐵𝐵� 𝐶𝐶̅ 𝐷𝐷
� + 𝐴𝐴̅𝐵𝐵𝐶𝐶
� 𝐷𝐷 ̅ 𝐶𝐶̅ 𝐷𝐷
� + 𝐴𝐴𝐵𝐵 � + 𝐴𝐴𝐵𝐵̅ 𝐶𝐶𝐷𝐷
̅ AB
̅ ̅ 𝐷𝐷� + 𝐴𝐴𝐴𝐴 𝐶𝐶̅ 𝐷𝐷 ̅
� + 𝐴𝐴𝐴𝐴 𝐶𝐶𝐷𝐷 00 1 0 0 1
+𝐴𝐴𝐵𝐵𝐵𝐵𝐵𝐵 + 𝐴𝐴𝐵𝐵𝐵𝐵
+𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴 + 𝐴𝐴𝐴𝐴𝐴𝐴 𝐷𝐷 � + 𝐴𝐴𝐵𝐵� 𝐶𝐶̅ 𝐷𝐷
� + 𝐴𝐴𝐵𝐵𝐶𝐶
� 𝐷𝐷 � 01 1 1 1 1
11 1 1 1 1
𝐹𝐹𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀 = 𝐵𝐵 + 𝐷𝐷 10 1 0 0 1

12
 Three-variables: Application Time!
𝐹𝐹 = 𝐴𝐴̅𝐵𝐵� 𝐶𝐶̅ + 𝐴𝐴̅𝐵𝐵𝐶𝐶 ̅ 𝐶𝐶̅ + 𝐴𝐴𝐴𝐴𝐶𝐶̅
� + 𝐴𝐴𝐵𝐵𝐵𝐵 + 𝐴𝐴𝐵𝐵 𝐹𝐹 = 𝐴𝐴̅𝐵𝐵𝐶𝐶
� + 𝐴𝐴𝐵𝐵� 𝐶𝐶̅ + 𝐴𝐴𝐵𝐵𝐶𝐶
� + 𝐴𝐴̅𝐵𝐵� 𝐶𝐶̅ + 𝐴𝐴𝐵𝐵
̅ 𝐶𝐶̅
BC BC
A
00 01 11 10 00 01 11 10
A
0 1 1 1 1 0 1 1 0 1

1 0 0 0 1 1 1 1 0 0

𝐹𝐹𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀 = 𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠 14 𝐹𝐹𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀 = 𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠 14

Four-variables:
𝐹𝐹 = 𝐴𝐴̅𝐵𝐵� 𝐶𝐶̅ 𝐷𝐷
� + 𝐴𝐴̅𝐵𝐵𝐶𝐶𝐶𝐶
� ̅ 𝐶𝐶𝐷𝐷
+ 𝐴𝐴𝐵𝐵 ̅ + 𝐴𝐴𝐵𝐵𝐶𝐶𝐷𝐷
̅ 𝐹𝐹 = 𝐴𝐴̅𝐵𝐵� 𝐶𝐶̅ 𝐷𝐷
� + 𝐴𝐴̅𝐵𝐵𝐶𝐶
� 𝐷𝐷 ̅ 𝐶𝐶𝐷𝐷
� + 𝐴𝐴𝐵𝐵 ̅ + 𝐴𝐴𝐵𝐵𝐵𝐵𝐵𝐵
̅
+𝐴𝐴𝐴𝐴 𝐶𝐶𝐷𝐷 ̅ + 𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴 + 𝐴𝐴𝐵𝐵� 𝐶𝐶̅ 𝐷𝐷
� + 𝐴𝐴𝐵𝐵𝐶𝐶𝐷𝐷
� +𝐴𝐴𝐴𝐴𝐶𝐶𝐷𝐷 ̅ + 𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴 + 𝐴𝐴𝐵𝐵� 𝐶𝐶̅ 𝐷𝐷
� + 𝐴𝐴𝐵𝐵𝐶𝐶
� 𝐷𝐷�

CD 00 CD 00 01 11 10
01 11 10 AB
AB 00 1 0 0 1
00 1 0 1 0
01 0 1 1 0 01 0 1 1 0

11 0 1 1 0 11 0 1 1 0

10 1 0 1 0 10 1 0 0 1

𝐹𝐹𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀 = 𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠 15 𝐹𝐹𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀 = 𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠 15

13
 Boolean function (SOP) simplification
using K-Map (cont.)
Three-variables: 𝐴𝐴̅ (B and C eliminated)
BC
A
00 01 11 10
𝐹𝐹 = 𝐴𝐴̅𝐵𝐵� 𝐶𝐶̅ + 𝐴𝐴̅𝐵𝐵𝐶𝐶 ̅ 𝐶𝐶̅ + 𝐴𝐴𝐴𝐴𝐶𝐶̅
� + 𝐴𝐴𝐵𝐵𝐵𝐵 + 𝐴𝐴𝐵𝐵
0 1 1 1 1

𝐹𝐹 = 𝐴𝐴̅ + 𝐵𝐵 𝐶𝐶̅ 1 0 0 0 1

𝐴𝐴̅𝐵𝐵� 𝐶𝐶̅ + 𝐴𝐴̅𝐵𝐵𝐶𝐶 ̅ 𝐶𝐶̅ → 𝐴𝐴̅𝐵𝐵� 𝐶𝐶̅ + 𝐶𝐶 + 𝐴𝐴𝐵𝐵 𝐶𝐶 + 𝐶𝐶̅

� + 𝐴𝐴𝐵𝐵𝐵𝐵 + 𝐴𝐴𝐵𝐵
→ 𝐴𝐴̅𝐵𝐵� + 𝐴𝐴𝐵𝐵 → 𝐴𝐴̅ 𝐵𝐵� + 𝐵𝐵 → 𝐴𝐴̅
𝐵𝐵 𝐶𝐶̅ (A eliminated)
̅ 𝐶𝐶̅ + 𝐴𝐴𝐴𝐴 𝐶𝐶→
𝐴𝐴𝐵𝐵 ̅ 𝐴𝐴̅ + 𝐴𝐴 𝐵𝐵𝐶𝐶→𝐵𝐵
̅ 𝐶𝐶̅
𝐵𝐵� (A and C eliminated)
𝐹𝐹 = 𝐴𝐴̅𝐵𝐵𝐶𝐶
� + 𝐴𝐴𝐵𝐵� 𝐶𝐶̅ + 𝐴𝐴𝐵𝐵𝐶𝐶
� + 𝐴𝐴̅𝐵𝐵� 𝐶𝐶̅ + 𝐴𝐴𝐵𝐵
̅ 𝐶𝐶̅ BC
A
00 01 11 10

𝐹𝐹 = 𝐵𝐵� + 𝐴𝐴̅𝐶𝐶̅ 0 1 1 0 1
𝐴𝐴̅𝐵𝐵𝐶𝐶
� + 𝐴𝐴𝐵𝐵� 𝐶𝐶̅ + 𝐴𝐴𝐵𝐵𝐶𝐶
� + 𝐴𝐴̅𝐵𝐵� 𝐶𝐶̅ → 𝐴𝐴̅𝐵𝐵� 𝐶𝐶 + 𝐶𝐶̅ + 𝐴𝐴𝐵𝐵� 𝐶𝐶̅ + 𝐶𝐶
𝐴𝐴̅ + 𝐴𝐴 𝐵𝐵� → 𝐵𝐵� 1 1 1 0 0
̅ 𝐶𝐶̅ → 𝐴𝐴̅ 𝐵𝐵� + 𝐵𝐵 𝐶𝐶̅ → 𝐴𝐴̅𝐶𝐶̅
𝐴𝐴̅𝐵𝐵� 𝐶𝐶̅ + 𝐴𝐴𝐵𝐵
𝐴𝐴̅𝐶𝐶̅ (B is eliminated)
Group the adjacent cells where only one variable changes 14
value so that it can be eliminated
 Minimization (MSOP) using K-Map
(cont.)
Four-variables: 𝐵𝐵� 𝐶𝐶̅ 𝐷𝐷
� 𝐵𝐵𝐷𝐷 𝐶𝐶𝐷𝐷
CD 00 01 11 10
𝐹𝐹 = 𝐴𝐴̅𝐵𝐵� 𝐶𝐶̅ 𝐷𝐷
� + 𝐴𝐴̅𝐵𝐵𝐶𝐶𝐶𝐶
� ̅ 𝐶𝐶𝐷𝐷
+ 𝐴𝐴𝐵𝐵 ̅ + 𝐴𝐴𝐵𝐵𝐶𝐶𝐷𝐷
̅ AB
̅ + 𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴 + 𝐴𝐴𝐵𝐵� 𝐶𝐶̅ 𝐷𝐷
� + 𝐴𝐴𝐵𝐵𝐶𝐶𝐷𝐷
� 00 1 0 1 0
+𝐴𝐴𝐴𝐴 𝐶𝐶𝐷𝐷
01 0 1 1 0
11 0 1 1 0
𝐹𝐹𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀 = 𝐵𝐵� 𝐶𝐶̅ 𝐷𝐷
� + 𝐵𝐵𝐵𝐵 + 𝐶𝐶𝐷𝐷
1 0 1 0
10

𝐵𝐵� 𝐷𝐷
� 𝐵𝐵𝐷𝐷
CD 00 01 11 10
𝐹𝐹 = 𝐴𝐴̅𝐵𝐵� 𝐶𝐶̅ 𝐷𝐷
� + 𝐴𝐴̅𝐵𝐵𝐶𝐶
� 𝐷𝐷 ̅ 𝐶𝐶𝐷𝐷
� + 𝐴𝐴𝐵𝐵 ̅ + 𝐴𝐴𝐵𝐵𝐵𝐵𝐵𝐵
̅ AB
+𝐴𝐴𝐴𝐴𝐶𝐶𝐷𝐷 ̅ + 𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴 + 𝐴𝐴𝐵𝐵� 𝐶𝐶̅ 𝐷𝐷
� + 𝐴𝐴𝐵𝐵𝐶𝐶
� 𝐷𝐷� 00 1 0 0 1
01 0 1 1 0
11 0 1 1 0
𝐹𝐹𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀 = 𝐵𝐵� 𝐷𝐷
� + 𝐵𝐵𝐵𝐵
10 1 0 0 1

15
 Minimization (MPOS) using K-Map
maxterm-input correspondence: complement literals if 1
Boolean function in POS:
CD 00 01 11 10 𝐶𝐶̅ + 𝐷𝐷
� ̅
𝐹𝐹 = 𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶 + 𝐷𝐷 𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶 + 𝐷𝐷 AB
𝐴𝐴 + 𝐵𝐵� + 𝐶𝐶 + 𝐷𝐷 𝐴𝐴 + 𝐵𝐵� + 𝐶𝐶̅ + 𝐷𝐷 00 1 0 1 0
𝐴𝐴̅ + 𝐵𝐵� + 𝐶𝐶 + 𝐷𝐷 𝐴𝐴̅ + 𝐵𝐵� + 𝐶𝐶̅ + 𝐷𝐷 01 0 1 1 0
(𝐴𝐴̅ + 𝐵𝐵 + 𝐶𝐶 + 𝐷𝐷
� )(𝐴𝐴̅ + 𝐵𝐵 + 𝐶𝐶̅ + 𝐷𝐷)
0 1 1 0
11
10 1 0 1 0
� ⋅ 𝐶𝐶̅ + 𝐷𝐷 ⋅ (𝐵𝐵� + 𝐷𝐷)
𝐹𝐹𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀 = 𝐵𝐵 + 𝐶𝐶 + 𝐷𝐷
� ⋅ 𝐴𝐴̅ + 𝐵𝐵 + 𝐶𝐶 + 𝐷𝐷
𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶 + 𝐷𝐷 �
POS simplification using K-map: = 𝐴𝐴𝐴𝐴̅ + 𝐴𝐴 ⋅ 𝐵𝐵 + 𝐶𝐶 + 𝐷𝐷
�
+ 𝐵𝐵 + 𝐶𝐶 + 𝐷𝐷 � ⋅ 𝐴𝐴̅ + 𝐵𝐵 + 𝐶𝐶 + 𝐷𝐷
�
Group the squares that only contains “0”
⋅ 𝐵𝐵 + 𝐶𝐶 + 𝐷𝐷� = 𝐵𝐵 + 𝐶𝐶 + 𝐷𝐷 �
Form an OR term (sum) for each group, instead of a product
Value “1”, instead of “0”, represent complement of the variable
Follow similar grouping rules for SOP
Either SOP or POS can be used to implement the Boolean function, depending on which gives
more efficient implementation.
summarizing: proceed as SOP, but group 0’s instead of 1’s (square = maxterm)
+ complement the values in row-col. to find maxterm associated with square 16
 Invalid groupings

Two variable change value

CD 00 01 11 10 CD 00 01 11 10
AB AB
00 1 0 1 0 00 0 1 0 1
01 0 1 1 0 01 1 0 0 1
11 0 1 1 0 11 0 1 1 1
10 1 0 1 0 10 0 1 1 1

Squares in the group are not in power of two not horizontal or vertical

17
 Application Example - Boolean
Function Simplification
𝐹𝐹 𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑 = 𝑎𝑎𝑎𝑎𝑐𝑐̅ + 𝑎𝑎𝑎𝑎𝑎𝑎 + 𝑏𝑏𝑏𝑏𝑏𝑏 + 𝑎𝑎𝑐𝑐𝑐𝑐 �
� + 𝑎𝑎𝑏𝑏𝑐𝑐𝑑𝑑
= 𝑎𝑎𝑎𝑎 𝑐𝑐̅ + 𝑐𝑐 + 𝑏𝑏𝑏𝑏𝑏𝑏 + 𝑎𝑎𝑐𝑐𝑐𝑐
� + 𝑎𝑎𝑏𝑏𝑐𝑐𝑑𝑑 � (𝐴𝐴 + 𝐴𝐴̅ = 1)
= 𝑎𝑎 𝑏𝑏 + 𝑏𝑏� 𝑐𝑐𝑑𝑑 ̅ + 𝑏𝑏𝑏𝑏𝑏𝑏 + 𝑎𝑎𝑐𝑐𝑐𝑐
� (𝐴𝐴 + 𝐴𝐴̅ � 𝐵𝐵 = 𝐴𝐴 + 𝐵𝐵)
= 𝑎𝑎 𝑏𝑏 + 𝑐𝑐𝑑𝑑 ̅ + 𝑏𝑏𝑏𝑏𝑏𝑏 + 𝑎𝑎𝑐𝑐𝑐𝑐
�
= 𝑎𝑎𝑏𝑏 + 𝑎𝑎� 𝑐𝑐𝑐𝑐 + 𝑏𝑏 𝑐𝑐𝑐𝑐 + 𝑎𝑎𝑐𝑐𝑑𝑑 ̅ (𝐴𝐴𝐵𝐵 + 𝐴𝐴𝐶𝐶̅ + 𝐵𝐵𝐶𝐶 = 𝐴𝐴𝐴𝐴 + 𝐴𝐴𝐶𝐶)
̅ - consensus
= 𝑎𝑎𝑎𝑎 + 𝑎𝑎𝑐𝑐𝑐𝑐
� + 𝑎𝑎𝑐𝑐𝑑𝑑 ̅

K-Map Simplification :
𝐹𝐹 𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑 = 𝑎𝑎𝑎𝑎𝑐𝑐̅ + 𝑎𝑎𝑎𝑎𝑎𝑎 + 𝑏𝑏𝑏𝑏𝑏𝑏 + 𝑎𝑎𝑐𝑐𝑐𝑐 �
� + 𝑎𝑎𝑏𝑏𝑐𝑐𝑑𝑑
CD 00 01 11 10
AB
00 1
01 1
𝐹𝐹𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀 𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑 = 𝑎𝑎𝑎𝑎 + 𝑎𝑎𝑐𝑐𝑐𝑐
� + 𝑎𝑎𝑐𝑐𝑑𝑑
11 1 1 1 1
10 1
18
Digital Design
Design Example - 7-Seg Decoder
A 7-segment display decoder takes a 4-bit input, D3:0, and produces seven outputs to
control LEDs, to display a digit from 0 to 9. The LEDs are named a through g, or Sa – Sg.
Write a truth table for the output Sa and derive D3 D2 D1 D0 Sa
the MSOP.
0 0 0 0 1
You may assume illegal input values (10–15) will
0 0 0 1 0
never appear and use don’t cares.
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1
1 0 1 0 X
1 0 1 1 X
1 1 0 0 X
1 1 0 1 X
1 1 1 0 X
1 1 1 1 Page 19 X
 Design Example - 7-Seg Decoder
D3D2
D1D0 00 01 11 10 𝑫𝑫𝟐𝟐 . 𝑫𝑫𝟎𝟎
00 1 0 X 1
01 0 1 X 1 𝑆𝑆𝑎𝑎 = 𝐷𝐷2 𝐷𝐷0 + 𝐷𝐷2 𝐷𝐷0 + 𝐷𝐷1 + 𝐷𝐷3
𝑫𝑫𝟑𝟑
11 1 1 X X
10 1 1 X X
𝑫𝑫𝟏𝟏
𝑫𝑫𝟐𝟐 . 𝑫𝑫𝟎𝟎
oWe often assume that all combinations of input are valid (e.g. 3 inputs = 8
different input combinations that makes the function equal to 0 or 1)
oThere are applications in which some variable combinations never appear.
oThese conditions are called don’t-care conditions.
oDon’t-care condition is marked with “X” in K-map
oFor minimization, X can take either “1” or “0”.
Page 20
EE2026
Digital Design
COMBINATIONAL BLOCKS (SELF READING)
Chua Dingjuan elechuad@nus.edu.sg
Combinational Building Blocks
o Combinational logic is often grouped into larger functional
‘blocks’
o This layer of abstraction hides gate levels details and helps us
to visualize using ‘functions’!
o Common building blocks :
o Multiplexers / Demultiplexers
o Decoders – Example BCD to 7-segment
o Encoders
o Adders – Half Adders, Full Adders, Ripple Adders
o Magnitude Comparators
o Tri-State Logic Elements (Not Examinable)

o Verilog modeling (parameter)

2
 Multiplexer
A multiplexer (MUX) is a combinational circuit element that
selects data from one of 2N inputs and directs it to a single
output, according to an N-bit selection signal

Functional block diagram Condensed truth table

4-input MUX S1 S0 Z
I0
I0
I1 0 0 I0
I1
I2 0 1 I1
Z I2 Z
1 0 I2
…

I3
In-1 S1 S0
1 1 I3
Actual truth table would
have 26 rows !
Selection (I0, I1, I2, I3, S0 and S1)
Selection inputs allow one
Control
of the inputs to pass
through to the output
 Multiplexer Example Application
A multiplexer (MUX) is a combinational circuit element that
selects data from one of 2N inputs and directs it to a single
output, according to an N-bit selection signal

I0
I1
I2
Z
…

In-1

Selection
Control
 Verilog Example: 4:1 MUX
Multiplexers sometimes E S1 S0 I0 I1 I2 I3 Z
0 X X X X X X 0
include enable input signal 1 0 0 0 X X X 0
𝑍 = 𝐸 ⋅ 𝑆0 𝑆ഥ1 𝐼0 + 𝑆0 𝑆ഥ1 𝐼1 + 𝑆0 𝑆1 𝐼2 + 𝑆0 𝑆1 𝐼3 1 0 0 1 X X X 1
1 0 1 X 0 X X 0
1 0 1 X 1 X X 1
1 1 0 X X 0 X 0
1 1 0 X X 1 X 1
1 1 1 X X X 0 0
1 1 1 X X X 1 1

module mux41(Z,S,I0,I1,I2,I3,E);
input I0, I1, I2, I3; // inputs
input [1:0] S; // 2-bit selection signal
input E; // enable
output Z;
assign Z = E ? ( S[1] ? (S[0] ? I3 : I2) : (S[0] ? I1 : I0) ) : 0;
endmodule
MUX Application Example
Multiplexers can be used as lookup tables (LUT) to perform
logic functions!
Alyssa needs to implement the function 𝑌 = 𝐴𝐵ത + 𝐵ത 𝐶ҧ +
ҧ
𝐴𝐵𝐶 for her project. However, the only part in her lab kit is
an 8:1 multiplexer. How does she implement the function?
A B C Y
0 0 0
0 0 1
0 1 0
0 1 1 Z
1 0 0
1 0 1
1 1 0
1 1 1
Page 7
Demultiplexer
A Demultiplexer (DEMUX) connects an input signal to
any of 2N output lines, based on an N-bit selection
control

N-output switch Functional block diagram

of 4-output demux Truth table
N-output switch 4-output DEMUX
D S1 S0 Z0 Z1 Z2 Z3
Z0
Z0 0 X X 0 0 0 0
Z1
Z1
D 1 0 0 1 0 0 0
Z2
Z3
1 0 1 0 1 0 0
ZN-1 S1 S0 1 1 0 0 0 1 0
1 1 1 0 0 0 1
Selection
Selection
control
control
 Verilog Example: 1:4 DEMUX
Boolean expression of output D S1 S0 Z0 Z1 Z2 Z3
0 X X 0 0 0 0
𝑍0 = 𝐷 ⋅ 𝑆0 ⋅ 𝑆ഥ1 1 0 0 1 0 0 0
𝑍1 = 𝐷 ⋅ 𝑆0 ⋅ 𝑆ഥ1 1 0 1 0 1 0 0
𝑍2 = 𝐷 ⋅ 𝑆0 ⋅ 𝑆1
1 1 0 0 0 1 0
𝑍3 = 𝐷 ⋅ 𝑆0 ⋅ 𝑆1
1 1 1 0 0 0 1

module demux41(Z0,Z1,Z2,Z3,S,D);

input D; // input
input [1:0] S; // 2-bit selection signal
output Z0, Z1, Z2, Z3;
assign Z0 = (S == 2'b00) ? D : 1'b0;
assign Z1 = (S == 2'b01) ? D : 1'b0;
assign Z2 = (S == 2'b10) ? D : 1'b0;
assign Z3 = (S == 2'b11) ? D : 1'b0;

endmodule
 Decoder
Input: N-bit input code, Output : 2N outputs
A decoder asserts ONE output as a function of the input
(these outputs are also called one-hot!)

Truth Table
Functional block diagram
A2 A1 A0 Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z7
3-to-8 decoder
0 0 0 1 0 0 0 0 0 0 0
Z0
0 0 1 0 1 0 0 0 0 0 0
A2 Z1
0 1 0 0 0 1 0 0 0 0 0
Z2
Z3 0 1 1 0 0 0 1 0 0 0 0
N A1
Z4
2N 1 0 0 0 0 0 0 1 0 0 0
Z5 1 0 1 0 0 0 0 0 1 0 0
A0 Z6 1 1 0 0 0 0 0 0 0 1 0
Z7 1 1 1 0 0 0 0 0 0 0 1

More examples here : https://youtu.be/0jRA3tfQSSw?si=pUya-aFZ80MM9OBL&t=1953

 Example: BCD-to-7 Segment Decoder
Converts a BCD number into signals required to display that number
on a 7-segment display

a
f b
g
e
d
c
+ -
ANODE CATHODE
A 7-segment display. Each segment is an LED LED

which will light when a logic T signal is applied to

it
• 7-segment displays are of 2 types: common anode and common
cathode
• Common anode display has all LED anodes connected and is active
low, whereas the common cathode display is active high
 Example - BCD-to-7 Seg Decoder
BCD-to-7- Truth Table
segment decoder D C B A a b c d e f g
a 0 0 0 0 1 1 1 1 1 1 0
D b 0 0 0 1 0 1 1 0 0 0 0
C c 0 0 1 0 1 1 0 1 1 0 1
d 0 0 1 1 1 1 1 1 0 0 1
B e 0 1 0 0 0 1 1 0 0 1 1
A f 0 1 0 1 1 0 1 1 0 1 1
g 0 1 1 0 1 0 1 1 1 1 1
0 1 1 1 1 1 1 0 0 0 0
Functional block diagram
1 0 0 0 1 1 1 1 1 1 1
a 1 0 0 1 1 1 1 1 0 1 1
1 0 1 0 X X X X X X X
f g b 1 0 1 1 X X X X X X X
1 1 0 0 X X X X X X X
e c 1 1 0 1 X X X X X X X
1 1 1 0 X X X X X X X
d 1 1 1 1 X X X X X X X
Verilog Example: Decoder 2-4
A 2:4 decoder has 22 output
lines for N inputs Z0
◦ output can be single- or multi-bit
A1
Enable signal A0 Z1
◦ if E = 1, normal operation
◦ if E= 0, disable outputs (all 0’s) Z2
E
Truth Table including Enable signal
Inputs Outputs
Z3
E A1 A0 Z0 Z1 Z2 Z3
0 X X 0 0 0 0 Functional block diagram
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1
 Decoder: Verilog
Dataflow Verilog description of a 2:4 decoder.
What if we would like to implement a 16:4 decoder instead?

module decoder24(Z,A,E); Inputs Outputs

input [1:0] A; E A1 A0 Z0 Z1 Z2 Z3
input E;
0 X X 0 0 0 0
output [0:3] Z;
1 0 0 1 0 0 0
assign Z = ((A == 2'b00) & E) ? 4'b1000 : 1 0 1 0 1 0 0
((A == 2'b01) & E) ? 4'b0100 : 1 1 0 0 0 1 0
((A == 2'b10) & E) ? 4'b0010 : 1 1 1 0 0 0 1
((A == 2'b11) & E) ? 4'b0001 :
4'b0000;
// 0000 is assigned if E=0
endmodule
 parameter
o Parameters are constants in Verilog (hence illegal to
modify their value at runtime).
o They are often used to customize modules, helping to
create more reusable code.
Parameterized dataflow Verilog description (arbitrary bit width)
module decoder(Z,A,E);
parameter M = 4; // parameterized design (sets # inputs)
parameter N = 2**M; // parameterized design (sets # outputs=2^M)

input [ M-1 : 0 ] A;
input E;
output [ 0 : N-1 ] Z;

wire [N-1:0] zerovec = {N{1'b0}}; // replication operator to create all zeroes.

assign Z = (E) ? (1 << A) : zerovec ;

// if enable=0, output is set to to zerovec (all zeroes)
// if enable=1, shift “1” A times and fill all other positions with zeros
endmodule
 parameter
o Modules can also be configured by passing parameters at
instantiation!
module decoder #(parameter M = 4) (Z,A,E);
parameter N = 2**M ;
input [ M-1 : 0 ] A; Default value when none is provided
input E;
output [ 0 : N-1 ] Z;

wire [N-1:0] zerovec = {N{1'b0}};

assign Z = (E) ? (1 << A) : zerovec ;

endmodule

module top (input [4:0] sw, output [15:0] led);

decoder #(2) u1 (led[3:0], sw[1:0], sw[4]); //This creates a 2:4 decoder

//decoder #(4) u2 (led[15:0], sw[3:0], sw[4]); //This creates a 4:16 decoder

endmodule
 Encoder
• For different input bits (usually 2N), encoder generates a code
with fewer bits (usually N bits) uniquely identifying the input
– performs the inverse of the decoding function

Functional block diagram Truth Table (an 8-3 encoder)

I0 I0 I1 I2 I3 I4 I5 I6 I7 C2 C1 C0
I1 1 0 0 0 0 0 0 0 0 0 0
C2 0 1 0 0 0 0 0 0 0 0 1
I2
0 0 1 0 0 0 0 0 0 1 0
I3
C1 0 0 0 1 0 0 0 0 0 1 1
I4
0 0 0 0 1 0 0 0 1 0 0
I5
C0 0 0 0 0 0 1 0 0 1 0 1
I6 0 0 0 0 0 0 1 0 1 1 0
I7 0 0 0 0 0 0 0 1 1 1 1
Example: Priority Encoder
• Generic encoders: error flagged if multiple input bits are 1
• Priority encoder allows multiple input bits to be 1
– output set by the input bit with highest priority (i.e., most significant
position), ignoring those with lower priority

I0 I1 I2 I3 I4 I5 I6 I7 C2 C1 C0
1 0 0 0 0 0 0 0 0 0 0
X 1 0 0 0 0 0 0 0 0 1
X X 1 0 0 0 0 0 0 1 0
X X X 1 0 0 0 0 0 1 1
X X X X 1 0 0 0 1 0 0
X X X X X 1 0 0 1 0 1
X X X X X X 1 0 1 1 0
X X X X X X X 1 1 1 1
 Example: Priority Encoder
Dataflow Verilog description of 4-2 priority encoder I0 I1 I2 I3 C1 C0
1 0 0 0 0 0
X 1 0 0 0 1
X X 1 0 1 0
X X X 1 1 1
Use nested conditional operators, starting from MSB and progressively
moving to the LSB

module priorityencoder(C,I);
input [3:0] I;
output [1:0] C;
assign C = (I[3]) ? (2'b11) : (I[2] ? (2'b10) : (I[1] ? (2'b01) : (2'b00)) );
// if I[3]=1, C=11
// else, if I[2]=1, C=10, etc.
endmodule

• No clever parameterized dataflow Verilog description

 Half Adders
It is a one bit binary adder with two inputs of Ai and Bi

Ai Ai Bi Sumi Carryi+1
SUMi
Bi 0 0 0 0
0+0=0
0+1=1 0 1 1 0
1+0=1 1 0 1 0
CARRYi+1
1 + 1 = 10 1 1 0 1

𝑆 = 𝐴ҧ ⋅ 𝐵 + 𝐴 ⋅ 𝐵ത = 𝐴⨁𝐵
𝐶 =𝐴⋅𝐵
Carry in from previous bit cannot be added
module ha(S,Cout,A,B);
input A, B;
output S, Cout; // Cout is the carry output
assign S = A ^ B;
assign Cout = A & B;
endmodule
Full Adders
Full adders can add carry bit from previous stage of addition
Carry → 𝐶𝑖+1
A : An Ai +1 Ai A0 Ai Bi Ci Si Ci+1
B : Bn Bi +1 Bi B0 0 0 0 0 0
Sum → 𝑆𝑖 0 0 1 1 0
0 1 0 1 0

Full adder
0 1 1 0 1
1 0 0 1 0
Current
Ai Si sum 1 0 1 0 1
Current
bits
1 1 0 0 1
Bi
1 1 1 1 1
carry-in from carry-out to
previous stg Ci Ci+1 next stg
 Full Adders (cont.)
K-map for SUM K-map for CARRY
Ai Ai
0 1 0 1
BiCi BiCi
00 0 1 00 0 0
Note: Ci+1 is not a MSOP, but
01 1 0 01 0 1
less overall hardware is reqd.
11 0 1 if we use this expression. It 11 1 1
allows sharing of Ai XOR Bi 10 0 1
10 1 0
between SUMi and Ci+1.

SUM = A iBiCi + A iBiCi + A iBiCi + A iBiCi C i+1 = A iB i + A i Bi C i + A iB i C i

= A i (BiCi + BiCi ) + A i (BiCi + BiCi ) = A iB i + C i ( A i Bi + A iB i )
= A i (Bi  Ci ) + A i (Bi  Ci ) = A iB i + C i ( A i  B i )
= A i  Bi  Ci
 Full Adder Circuit
SUM = ( Ai  Bi )  Ci Full adder

half adder half adder

Ci+1 = Ai Bi + Ci ( Ai  Bi ) Ai SUMi
Bi

Note: A full adder adds 3 bits

(3 input signals, each of 1 bit). Ci+1
Ci

module fa(S,Cout,A,B,Cin);
input A, B, Cin; // Cin is the carry input
output S, Cout; // Cout is the carry output
assign S = A ^ B ^ Cin;
assign Cout = A & B | Cin & (A ^ B);
endmodule
Parallel Adders

Ai Bi
C4 C3 C2 C1

Ci+1 Full Ci A3 A2 A1 A0
Adder B3 B2 B1 B0

Si

MSB LSB

A3 B3 A2 B2 A1 B1 A0 B0

carry-out C4
Stage 3
C3
Stage 2
C2
Stage 1
C1
Stage 0
C0
FA FA FA FA 0

S3 S2 S1 S0

Note: no carry-in
4 cascaded full adders
Parallel Adders (cont.)
In general, n full adders need to be used to form an n-bit adder
Carry ripple effect
◦ output of each full adder is not available until the carry-in from the previous
stage is delivered
◦ carry bits have to propagate from one stage to the next
◦ as the carries ripple through the carry chain → also known as ripple carry
adders

A0 B 0 A1 B 1 AN-1 B N-1

Cin1 Cin2 Cin(N-1) Cout

Cin0 FA0 FA1 FA(N-1)

critical path
S0 S1 SN-1
This slow rippling effect is substantially reduced by using carry look ahead
adders
 Parallel Adders (cont.)
Structural Verilog description (parameterized, arbitrary bit width)

module rca(S,Cout,A,B,Cin); // 4-bit ripple carry adder

parameter N = 4; // parameterized bit width
input [N-1:0] A, B;
input Cin; // Cin is the adder carry input (at LSB)
output [N-1:0] S;
output Cout; // Cout is the adder carry output (at MSB)
wire [N:0] C; // carry inputs of all full adders + carry output of last one
assign C[0] = Cin;
assign Cout = C[N];
genvar i; // temp variable used only in generate loop
generate for(i=0;i<N;i=i+1) begin
fa FAinstance (.S(S[i]),.Cout(C[i+1]),.A(A[i]),.B(B[i]),.Cin(C[i]));
end
endgenerate
endmodule
Magnitude Comparator
Outputs are functions of relative magnitudes of
input binary numbers A and B

Magnitude comparator

(A > B)
N AN-1 ...A0
(A = B)
N
BN-1...B0
(A < B)

Functional block diagram

Magnitude Comparator: Truth Table
2-bit magnitude comparator
A1 A0 B1 B0 (A > B) (A = B) (A < B)
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0
 K-maps for A>B and A<B

A>B A<B
A1 A0 A1 A 0
00 01 11 10 00 01 11 10
B1B0 B1B0
00 0 1 1 1 00 0 0 0 0
01 0 0 1 1 01 1 0 0 0
11 0 0 0 0 11 1 1 0 1
10 0 0 1 0 10 1 1 0 0

( A  B) = A1 B1 + A0 B1B0 + A1 A0 B0 ( A  B) = A1B1 + A1 A0 B0 + A0 B1B0

K-map for A=B

A=B
A1 A0 ( A = B) = A1 A0 B1B0 + A1 A0 B1B0
00 01 11 10
B1B0
+ A1 A0 B1B0 + A1 A0 B1B0
00 1 0 0 0
01 0 1 0 0 This can be generated
indirectly
11 0 0 1 0
using (A<B) and (A>B)
10 0 0 0 1

( A = B) = ( A  B)  ( A  B)
 Magnitude Comparator: Verilog
Dataflow Verilog description (parameterized, arbitrary bit width)

module magcomp(AgreaterB,AequalB,AlowerB,A,B);
parameter N = 4;

input [N-1:0] A, B;
output AgreaterB, AequalB, AlowerB;

assign AgreaterB = (A > B);

assign AequalB = (A == B);
assign AlowerB = (A < B);
/* to reduce complexity at the cost of slightly worse performance: assign
AlowerB = ~AgreaterB & ~AequalB */
endmodule
Tri-State Logic Elements
Ordinarily, a digital device has 2 states
◦ tri-state devices also have high impedance state (Z)
◦ floating output: the device does not force any voltage
◦ voltage set by the output of some other device
◦ if only one device is enabled at a time (all others in Z), multiple
devices can drive the same node without conflicting
◦ several tri-state logic gates
◦ example: tri-state buffer with active-high enable

Functional block diagram Voltage table

E D Y
1 0 0
1 1 1
E
D Y
0 X Z  Z = high impedance
 Tri-State Logic Gates: Verilog
Dataflow Verilog description of various logic gates
tristate buffer with active-high enable tristate buffer with active-low enable
module tristatebuffer(Y,D,E); module tristatebuffer(Y,D,E);
input D, E; input D, E;
output Y; output Y;
assign Y = E ? D : 1’bz; assign Y = E ? 1’bz : D;
endmodule endmodule
tristate inverter with active-high enable tristate inverter with active-low enable
module tristateinv(Y,D,E); module tristateoinv(Y,D,E);
input D, E; input D, E;
output Y; output Y;
assign Y = E ? ~D : 1’bz; assign Y = E ? 1’bz : ~D;
endmodule endmodule
MUXes Based on Tri-State Elements
Tri-state gates with common output A0.H

implement MUXes
B0.H
When Control = 00, tri-state device for A0 is X0
Device X
enabled, others are disabled. Hence A0 is C0.H X1

connected to X0, etc. D0.H

Control signals select which input goes to X 2-to-4 decoder Physically connected,
 effectively it behaves like a MUX but only one is
Control enabled

• Useful to connect several resources to same bus

– avoids expensive point-to-point interconnection
– the enabled resource drives the bus (others in Z may receive)
... 1
1 2 3 N 2
n ...
n n n n
n n n n
BUS
n
Summary
Introduction to combinational building blocks and their
Verilog description
Multiplexers / Demultiplexers
Decoders – Example BCD to 7-segment
Encoders
Adders – Half Adders, Full Adders, Ripple Adders
Magnitude Comparators
Tri-State Logic Elements (Not Examinable)
EE2026
Digital Design
COMBINATIONAL BLOCKS (SELF READING)
Chua Dingjuan elechuad@nus.edu.sg
Combinational Building Blocks
o Combinational logic is often grouped into larger functional
‘blocks’
o This layer of abstraction hides gate levels details and helps us
to visualize using ‘functions’!
o Common building blocks :
o Multiplexers / Demultiplexers
o Decoders – Example BCD to 7-segment
o Encoders
o Adders – Half Adders, Full Adders, Ripple Adders
o Magnitude Comparators
o Tri-State Logic Elements (Not Examinable)

o Verilog modeling (parameter)

2
 Multiplexer
A multiplexer (MUX) is a combinational circuit element that
selects data from one of 2N inputs and directs it to a single
output, according to an N-bit selection signal

Functional block diagram Condensed truth table

4-input MUX S1 S0 Z
I0
I0
I1 0 0 I0
I1
I2 0 1 I1
Z I2 Z
1 0 I2
…

I3
In-1 S1 S0
1 1 I3
Actual truth table would
have 26 rows !
Selection (I0, I1, I2, I3, S0 and S1)
Selection inputs allow one
Control
of the inputs to pass
through to the output
 Multiplexer Example Application
A multiplexer (MUX) is a combinational circuit element that
selects data from one of 2N inputs and directs it to a single
output, according to an N-bit selection signal

I0
I1
I2
Z
…

In-1

Selection
Control
 Verilog Example: 4:1 MUX
Multiplexers sometimes E S1 S0 I0 I1 I2 I3 Z
0 X X X X X X 0
include enable input signal 1 0 0 0 X X X 0
𝑍 = 𝐸 ⋅ 𝑆0 𝑆ഥ1 𝐼0 + 𝑆0 𝑆ഥ1 𝐼1 + 𝑆0 𝑆1 𝐼2 + 𝑆0 𝑆1 𝐼3 1 0 0 1 X X X 1
1 0 1 X 0 X X 0
1 0 1 X 1 X X 1
1 1 0 X X 0 X 0
1 1 0 X X 1 X 1
1 1 1 X X X 0 0
1 1 1 X X X 1 1

module mux41(Z,S,I0,I1,I2,I3,E);
input I0, I1, I2, I3; // inputs
input [1:0] S; // 2-bit selection signal
input E; // enable
output Z;
assign Z = E ? ( S[1] ? (S[0] ? I3 : I2) : (S[0] ? I1 : I0) ) : 0;
endmodule
MUX Application Example
Multiplexers can be used as lookup tables (LUT) to perform
logic functions!
Alyssa needs to implement the function 𝑌 = 𝐴𝐵ത + 𝐵ത 𝐶ҧ +
ҧ
𝐴𝐵𝐶 for her project. However, the only part in her lab kit is
an 8:1 multiplexer. How does she implement the function?
A B C Y
0 0 0
0 0 1
0 1 0
0 1 1 Z
1 0 0
1 0 1
1 1 0
1 1 1
Page 7
MUX Application Example
Multiplexers can be used as lookup tables (LUT) to perform
logic functions!
Alyssa needs to implement the function 𝑌 = 𝐴𝐵ത + 𝐵ത 𝐶ҧ +
ҧ
𝐴𝐵𝐶 for her project. However, the only part in her lab kit is
an 8:1 multiplexer. How does she implement the function?
A B C Y 1
0 0 0 1 0
0 0 1 0
0
0 1 0 0
1
0 1 1 1 Z
1
1 0 0 1
1
1 0 1 1
0
1 1 0 0
1 1 1 0 0

A B C Page 8
Demultiplexer
A Demultiplexer (DEMUX) connects an input signal to
any of 2N output lines, based on an N-bit selection
control

N-output switch Functional block diagram

of 4-output demux Truth table
N-output switch 4-output DEMUX
D S1 S0 Z0 Z1 Z2 Z3
Z0
Z0 0 X X 0 0 0 0
Z1
Z1
D 1 0 0 1 0 0 0
Z2
Z3
1 0 1 0 1 0 0
ZN-1 S1 S0 1 1 0 0 0 1 0
1 1 1 0 0 0 1
Selection
Selection
control
control
 Verilog Example: 1:4 DEMUX
Boolean expression of output D S1 S0 Z0 Z1 Z2 Z3
0 X X 0 0 0 0
𝑍0 = 𝐷 ⋅ 𝑆0 ⋅ 𝑆ഥ1 1 0 0 1 0 0 0
𝑍1 = 𝐷 ⋅ 𝑆0 ⋅ 𝑆ഥ1 1 0 1 0 1 0 0
𝑍2 = 𝐷 ⋅ 𝑆0 ⋅ 𝑆1
1 1 0 0 0 1 0
𝑍3 = 𝐷 ⋅ 𝑆0 ⋅ 𝑆1
1 1 1 0 0 0 1

module demux41(Z0,Z1,Z2,Z3,S,D);

input D; // input
input [1:0] S; // 2-bit selection signal
output Z0, Z1, Z2, Z3;
assign Z0 = (S == 2'b00) ? D : 1'b0;
assign Z1 = (S == 2'b01) ? D : 1'b0;
assign Z2 = (S == 2'b10) ? D : 1'b0;
assign Z3 = (S == 2'b11) ? D : 1'b0;

endmodule
 Decoder
Input: N-bit input code, Output : 2N outputs
A decoder asserts ONE output as a function of the input
(these outputs are also called one-hot!)

Truth Table
Functional block diagram
A2 A1 A0 Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z7
3-to-8 decoder
0 0 0 1 0 0 0 0 0 0 0
Z0
0 0 1 0 1 0 0 0 0 0 0
A2 Z1
0 1 0 0 0 1 0 0 0 0 0
Z2
Z3 0 1 1 0 0 0 1 0 0 0 0
N A1
Z4
2N 1 0 0 0 0 0 0 1 0 0 0
Z5 1 0 1 0 0 0 0 0 1 0 0
A0 Z6 1 1 0 0 0 0 0 0 0 1 0
Z7 1 1 1 0 0 0 0 0 0 0 1

More examples here : https://youtu.be/0jRA3tfQSSw?si=pUya-aFZ80MM9OBL&t=1953

 Example: BCD-to-7 Segment Decoder
Converts a BCD number into signals required to display that number
on a 7-segment display

a
f b
g
e
d
c
+ -
ANODE CATHODE
A 7-segment display. Each segment is an LED LED

which will light when a logic T signal is applied to

it
• 7-segment displays are of 2 types: common anode and common
cathode
• Common anode display has all LED anodes connected and is active
low, whereas the common cathode display is active high
 Example - BCD-to-7 Seg Decoder
BCD-to-7- Truth Table
segment decoder D C B A a b c d e f g
a 0 0 0 0 1 1 1 1 1 1 0
D b 0 0 0 1 0 1 1 0 0 0 0
C c 0 0 1 0 1 1 0 1 1 0 1
d 0 0 1 1 1 1 1 1 0 0 1
B e 0 1 0 0 0 1 1 0 0 1 1
A f 0 1 0 1 1 0 1 1 0 1 1
g 0 1 1 0 1 0 1 1 1 1 1
0 1 1 1 1 1 1 0 0 0 0
Functional block diagram
1 0 0 0 1 1 1 1 1 1 1
a 1 0 0 1 1 1 1 1 0 1 1
1 0 1 0 X X X X X X X
f g b 1 0 1 1 X X X X X X X
1 1 0 0 X X X X X X X
e c 1 1 0 1 X X X X X X X
1 1 1 0 X X X X X X X
d 1 1 1 1 X X X X X X X
Verilog Example: Decoder 2-4
A 2:4 decoder has 22 output
lines for N inputs Z0
◦ output can be single- or multi-bit
A1
Enable signal A0 Z1
◦ if E = 1, normal operation
◦ if E= 0, disable outputs (all 0’s) Z2
E
Truth Table including Enable signal
Inputs Outputs
Z3
E A1 A0 Z0 Z1 Z2 Z3
0 X X 0 0 0 0 Functional block diagram
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1
 Decoder: Verilog
Dataflow Verilog description of a 2:4 decoder.
What if we would like to implement a 16:4 decoder instead?

module decoder24(Z,A,E); Inputs Outputs

input [1:0] A; E A1 A0 Z0 Z1 Z2 Z3
input E;
0 X X 0 0 0 0
output [0:3] Z;
1 0 0 1 0 0 0
assign Z = ((A == 2'b00) & E) ? 4'b1000 : 1 0 1 0 1 0 0
((A == 2'b01) & E) ? 4'b0100 : 1 1 0 0 0 1 0
((A == 2'b10) & E) ? 4'b0010 : 1 1 1 0 0 0 1
((A == 2'b11) & E) ? 4'b0001 :
4'b0000;
// 0000 is assigned if E=0
endmodule
 parameter
o Parameters are constants in Verilog (hence illegal to
modify their value at runtime).
o They are often used to customize modules, helping to
create more reusable code.
Parameterized dataflow Verilog description (arbitrary bit width)
module decoder(Z,A,E);
parameter M = 4; // parameterized design (sets # inputs)
parameter N = 2**M; // parameterized design (sets # outputs=2^M)

input [ M-1 : 0 ] A;
input E;
output [ 0 : N-1 ] Z;

wire [N-1:0] zerovec = {N{1'b0}}; // replication operator to create all zeroes.

assign Z = (E) ? (1 << A) : zerovec ;

// if enable=0, output is set to to zerovec (all zeroes)
// if enable=1, shift “1” A times and fill all other positions with zeros
endmodule
 parameter
o Modules can also be configured by passing parameters at
instantiation!
module decoder #(parameter M = 4) (Z,A,E);
parameter N = 2**M ;
input [ M-1 : 0 ] A; Default value when none is provided
input E;
output [ 0 : N-1 ] Z;

wire [N-1:0] zerovec = {N{1'b0}};

assign Z = (E) ? (1 << A) : zerovec ;

endmodule

module top (input [4:0] sw, output [15:0] led);

decoder #(2) u1 (led[3:0], sw[1:0], sw[4]); //This creates a 2:4 decoder

//decoder #(4) u2 (led[15:0], sw[3:0], sw[4]); //This creates a 4:16 decoder

endmodule
 Encoder
• For different input bits (usually 2N), encoder generates a code
with fewer bits (usually N bits) uniquely identifying the input
– performs the inverse of the decoding function

Functional block diagram Truth Table (an 8-3 encoder)

I0 I0 I1 I2 I3 I4 I5 I6 I7 C2 C1 C0
I1 1 0 0 0 0 0 0 0 0 0 0
C2 0 1 0 0 0 0 0 0 0 0 1
I2
0 0 1 0 0 0 0 0 0 1 0
I3
C1 0 0 0 1 0 0 0 0 0 1 1
I4
0 0 0 0 1 0 0 0 1 0 0
I5
C0 0 0 0 0 0 1 0 0 1 0 1
I6 0 0 0 0 0 0 1 0 1 1 0
I7 0 0 0 0 0 0 0 1 1 1 1
Example: Priority Encoder
• Generic encoders: error flagged if multiple input bits are 1
• Priority encoder allows multiple input bits to be 1
– output set by the input bit with highest priority (i.e., most significant
position), ignoring those with lower priority

I0 I1 I2 I3 I4 I5 I6 I7 C2 C1 C0
1 0 0 0 0 0 0 0 0 0 0
X 1 0 0 0 0 0 0 0 0 1
X X 1 0 0 0 0 0 0 1 0
X X X 1 0 0 0 0 0 1 1
X X X X 1 0 0 0 1 0 0
X X X X X 1 0 0 1 0 1
X X X X X X 1 0 1 1 0
X X X X X X X 1 1 1 1
 Example: Priority Encoder
Dataflow Verilog description of 4-2 priority encoder I0 I1 I2 I3 C1 C0
1 0 0 0 0 0
X 1 0 0 0 1
X X 1 0 1 0
X X X 1 1 1
Use nested conditional operators, starting from MSB and progressively
moving to the LSB

module priorityencoder(C,I);
input [3:0] I;
output [1:0] C;
assign C = (I[3]) ? (2'b11) : (I[2] ? (2'b10) : (I[1] ? (2'b01) : (2'b00)) );
// if I[3]=1, C=11
// else, if I[2]=1, C=10, etc.
endmodule

• No clever parameterized dataflow Verilog description

 Half Adders
It is a one bit binary adder with two inputs of Ai and Bi

Ai Ai Bi Sumi Carryi+1
SUMi
Bi 0 0 0 0
0+0=0
0+1=1 0 1 1 0
1+0=1 1 0 1 0
CARRYi+1
1 + 1 = 10 1 1 0 1

𝑆 = 𝐴ҧ ⋅ 𝐵 + 𝐴 ⋅ 𝐵ത = 𝐴⨁𝐵
𝐶 =𝐴⋅𝐵
Carry in from previous bit cannot be added
module ha(S,Cout,A,B);
input A, B;
output S, Cout; // Cout is the carry output
assign S = A ^ B;
assign Cout = A & B;
endmodule
Full Adders
Full adders can add carry bit from previous stage of addition
Carry → 𝐶𝑖+1
A : An Ai +1 Ai A0 Ai Bi Ci Si Ci+1
B : Bn Bi +1 Bi B0 0 0 0 0 0
Sum → 𝑆𝑖 0 0 1 1 0
0 1 0 1 0

Full adder
0 1 1 0 1
1 0 0 1 0
Current
Ai Si sum 1 0 1 0 1
Current
bits
1 1 0 0 1
Bi
1 1 1 1 1
carry-in from carry-out to
previous stg Ci Ci+1 next stg
 Full Adders (cont.)
K-map for SUM K-map for CARRY
Ai Ai
0 1 0 1
BiCi BiCi
00 0 1 00 0 0
Note: Ci+1 is not a MSOP, but
01 1 0 01 0 1
less overall hardware is reqd.
11 0 1 if we use this expression. It 11 1 1
allows sharing of Ai XOR Bi 10 0 1
10 1 0
between SUMi and Ci+1.

SUM = A iBiCi + A iBiCi + A iBiCi + A iBiCi C i+1 = A iB i + A i Bi C i + A iB i C i

= A i (BiCi + BiCi ) + A i (BiCi + BiCi ) = A iB i + C i ( A i Bi + A iB i )
= A i (Bi  Ci ) + A i (Bi  Ci ) = A iB i + C i ( A i  B i )
= A i  Bi  Ci
 Full Adder Circuit
SUM = ( Ai  Bi )  Ci Full adder

half adder half adder

Ci+1 = Ai Bi + Ci ( Ai  Bi ) Ai SUMi
Bi

Note: A full adder adds 3 bits

(3 input signals, each of 1 bit). Ci+1
Ci

module fa(S,Cout,A,B,Cin);
input A, B, Cin; // Cin is the carry input
output S, Cout; // Cout is the carry output
assign S = A ^ B ^ Cin;
assign Cout = A & B | Cin & (A ^ B);
endmodule
Parallel Adders

Ai Bi
C4 C3 C2 C1

Ci+1 Full Ci A3 A2 A1 A0
Adder B3 B2 B1 B0

Si

MSB LSB

A3 B3 A2 B2 A1 B1 A0 B0

carry-out C4
Stage 3
C3
Stage 2
C2
Stage 1
C1
Stage 0
C0
FA FA FA FA 0

S3 S2 S1 S0

Note: no carry-in
4 cascaded full adders
Parallel Adders (cont.)
In general, n full adders need to be used to form an n-bit adder
Carry ripple effect
◦ output of each full adder is not available until the carry-in from the previous
stage is delivered
◦ carry bits have to propagate from one stage to the next
◦ as the carries ripple through the carry chain → also known as ripple carry
adders

A0 B 0 A1 B 1 AN-1 B N-1

Cin1 Cin2 Cin(N-1) Cout

Cin0 FA0 FA1 FA(N-1)

critical path
S0 S1 SN-1
This slow rippling effect is substantially reduced by using carry look ahead
adders
 Parallel Adders (cont.)
Structural Verilog description (parameterized, arbitrary bit width)

module rca(S,Cout,A,B,Cin); // 4-bit ripple carry adder

parameter N = 4; // parameterized bit width
input [N-1:0] A, B;
input Cin; // Cin is the adder carry input (at LSB)
output [N-1:0] S;
output Cout; // Cout is the adder carry output (at MSB)
wire [N:0] C; // carry inputs of all full adders + carry output of last one
assign C[0] = Cin;
assign Cout = C[N];
genvar i; // temp variable used only in generate loop
generate for(i=0;i<N;i=i+1) begin
fa FAinstance (.S(S[i]),.Cout(C[i+1]),.A(A[i]),.B(B[i]),.Cin(C[i]));
end
endgenerate
endmodule
Magnitude Comparator
Outputs are functions of relative magnitudes of
input binary numbers A and B

Magnitude comparator

(A > B)
N AN-1 ...A0
(A = B)
N
BN-1...B0
(A < B)

Functional block diagram

Magnitude Comparator: Truth Table
2-bit magnitude comparator
A1 A0 B1 B0 (A > B) (A = B) (A < B)
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0
 K-maps for A>B and A<B

A>B A<B
A1 A0 A1 A 0
00 01 11 10 00 01 11 10
B1B0 B1B0
00 0 1 1 1 00 0 0 0 0
01 0 0 1 1 01 1 0 0 0
11 0 0 0 0 11 1 1 0 1
10 0 0 1 0 10 1 1 0 0

( A  B) = A1 B1 + A0 B1B0 + A1 A0 B0 ( A  B) = A1B1 + A1 A0 B0 + A0 B1B0

K-map for A=B

A=B
A1 A0 ( A = B) = A1 A0 B1B0 + A1 A0 B1B0
00 01 11 10
B1B0
+ A1 A0 B1B0 + A1 A0 B1B0
00 1 0 0 0
01 0 1 0 0 This can be generated
indirectly
11 0 0 1 0
using (A<B) and (A>B)
10 0 0 0 1

( A = B) = ( A  B)  ( A  B)
 Magnitude Comparator: Verilog
Dataflow Verilog description (parameterized, arbitrary bit width)

module magcomp(AgreaterB,AequalB,AlowerB,A,B);
parameter N = 4;

input [N-1:0] A, B;
output AgreaterB, AequalB, AlowerB;

assign AgreaterB = (A > B);

assign AequalB = (A == B);
assign AlowerB = (A < B);
/* to reduce complexity at the cost of slightly worse performance: assign
AlowerB = ~AgreaterB & ~AequalB */
endmodule
Tri-State Logic Elements
Ordinarily, a digital device has 2 states
◦ tri-state devices also have high impedance state (Z)
◦ floating output: the device does not force any voltage
◦ voltage set by the output of some other device
◦ if only one device is enabled at a time (all others in Z), multiple
devices can drive the same node without conflicting
◦ several tri-state logic gates
◦ example: tri-state buffer with active-high enable

Functional block diagram Voltage table

E D Y
1 0 0
1 1 1
E
D Y
0 X Z  Z = high impedance
 Tri-State Logic Gates: Verilog
Dataflow Verilog description of various logic gates
tristate buffer with active-high enable tristate buffer with active-low enable
module tristatebuffer(Y,D,E); module tristatebuffer(Y,D,E);
input D, E; input D, E;
output Y; output Y;
assign Y = E ? D : 1’bz; assign Y = E ? 1’bz : D;
endmodule endmodule
tristate inverter with active-high enable tristate inverter with active-low enable
module tristateinv(Y,D,E); module tristateoinv(Y,D,E);
input D, E; input D, E;
output Y; output Y;
assign Y = E ? ~D : 1’bz; assign Y = E ? 1’bz : ~D;
endmodule endmodule
MUXes Based on Tri-State Elements
Tri-state gates with common output A0.H

implement MUXes
B0.H
When Control = 00, tri-state device for A0 is X0
Device X
enabled, others are disabled. Hence A0 is C0.H X1

connected to X0, etc. D0.H

Control signals select which input goes to X 2-to-4 decoder Physically connected,
 effectively it behaves like a MUX but only one is
Control enabled

• Useful to connect several resources to same bus

– avoids expensive point-to-point interconnection
– the enabled resource drives the bus (others in Z may receive)
... 1
1 2 3 N 2
n ...
n n n n
n n n n
BUS
n
Summary
Introduction to combinational building blocks and their
Verilog description
Multiplexers / Demultiplexers
Decoders – Example BCD to 7-segment
Encoders
Adders – Half Adders, Full Adders, Ripple Adders
Magnitude Comparators
Tri-State Logic Elements (Not Examinable)
Chapter 02.qxd 1/31/07 9:55 PM Page 93

Exercises 93

Exercises
Exercise 2.1 Write a Boolean equation in sum-of-products canonical form for
each of the truth tables in Figure 2.80.

(a) (b) (c) (d) (e)

A B Y A B C Y A B C Y A B C D Y A B C D Y
0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1
0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0
1 0 1 0 1 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0
1 1 1 0 1 1 0 0 1 1 0 0 0 1 1 1 0 0 1 1 1
1 0 0 0 1 0 0 1 0 1 0 0 0 0 1 0 0 0
1 0 1 0 1 0 1 1 0 1 0 1 0 0 1 0 1 1
1 1 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 1
1 1 1 1 1 1 1 1 0 1 1 1 0 0 1 1 1 0
1 0 0 0 1 1 0 0 0 0
1 0 0 1 0 1 0 0 1 1
1 0 1 0 1 1 0 1 0 1
1 0 1 1 0 1 0 1 1 0
1 1 0 0 0 1 1 0 0 1
1 1 0 1 0 1 1 0 1 0
1 1 1 0 1 1 1 1 0 0
1 1 1 1 0 1 1 1 1 1
Figure 2.80 Truth tables

Exercise 2.2 Write a Boolean equation in product-of-sums canonical form for

the truth tables in Figure 2.80.

Exercise 2.3 Minimize each of the Boolean equations from Exercise 2.1.

Exercise 2.4 Sketch a reasonably simple combinational circuit implementing

each of the functions from Exercise 2.3. Reasonably simple means that you are
not wasteful of gates, but you don’t waste vast amounts of time checking every
possible implementation of the circuit either.

Exercise 2.5 Repeat Exercise 2.4 using only NOT gates and AND and OR
gates.

Exercise 2.6 Repeat Exercise 2.4 using only NOT gates and NAND and NOR
gates.

Exercise 2.7 Simplify the following Boolean equations using Boolean theorems.
Check for correctness using a truth table or K-map.

(a) Y  AC  ABC

(b) Y  AB  A BC  (A  C)

(c) Y ABC D  ABC  ABCD  ABD ABCD  BCD  A

Chapter 02.qxd 1/31/07 9:55 PM Page 94

94 CHAPTER TWO Combinational Logic Design

Exercise 2.8 Sketch a reasonably simple combinational circuit implementing

each of the functions from Exercise 2.7.

Exercise 2.9 Simplify each of the following Boolean equations. Sketch a reason-
ably simple combinational circuit implementing the simplified equation.

(a) Y  BC  ABC  BC

(b) Y  A  AB  AB  A  B
(c) Y  ABC  ABD  ABE  ACD  ACE  (A  D  E)  B C D
 B CE  B D E  C D E

Exercise 2.10 Give an example of a truth table requiring between 3 billion and
5 billion rows that can be constructed using fewer than 40 (but at least 1)
two-input gates.

Exercise 2.11 Give an example of a circuit with a cyclic path that is nevertheless
combinational.

Exercise 2.12 Alyssa P. Hacker says that any Boolean function can be written in
minimal sum-of-products form as the sum of all of the prime implicants of the
function. Ben Bitdiddle says that there are some functions whose minimal equa-
tion does not involve all of the prime implicants. Explain why Alyssa is right or
provide a counterexample demonstrating Ben’s point.

Exercise 2.13 Prove that the following theorems are true using perfect induction.
You need not prove their duals.

(a) The idempotency theorem (T3)

(b) The distributivity theorem (T8)

(c) The combining theorem (T10)

Exercise 2.14 Prove De Morgan’s Theorem (T12) for three variables, B2, B1, B0,
using perfect induction.

Exercise 2.15 Write Boolean equations for the circuit in Figure 2.81. You need
not minimize the equations.
Chapter 02.qxd 1/31/07 9:55 PM Page 95

Exercises 95

A B C D

Y Z
Figure 2.81 Circuit schematic

Exercise 2.16 Minimize the Boolean equations from Exercise 2.15 and sketch an
improved circuit with the same function.

Exercise 2.17 Using De Morgan equivalent gates and bubble pushing methods,
redraw the circuit in Figure 2.82 so that you can find the Boolean equation by
inspection. Write the Boolean equation.

A
B
C
D
Y
E
Figure 2.82 Circuit schematic

Exercise 2.18 Repeat Exercise 2.17 for the circuit in Figure 2.83.
Chapter 02.qxd 1/31/07 9:55 PM Page 96

96 CHAPTER TWO Combinational Logic Design

A
B
C
D
Y
E

F
G
Figure 2.83 Circuit schematic

Exercise 2.19 Find a minimal Boolean equation for the function in Figure 2.84.
Remember to take advantage of the don’t care entries.

A B C D Y
0 0 0 0 X
0 0 0 1 X
0 0 1 0 X
0 0 1 1 0
0 1 0 0 0
0 1 0 1 X
0 1 1 0 0
0 1 1 1 X
1 0 0 0 1
1 0 0 1 0
1 0 1 0 X
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 X
1 1 1 1 1
Figure 2.84 Truth table

Exercise 2.20 Sketch a circuit for the function from Exercise 2.19.

Exercise 2.21 Does your circuit from Exercise 2.20 have any potential glitches
when one of the inputs changes? If not, explain why not. If so, show how to
modify the circuit to eliminate the glitches.

Exercise 2.22 Ben Bitdiddle will enjoy his picnic on sunny days that have no
ants. He will also enjoy his picnic any day he sees a hummingbird, as well as on
days where there are ants and ladybugs. Write a Boolean equation for his enjoy-
ment (E) in terms of sun (S), ants (A), hummingbirds (H), and ladybugs (L).
Chapter 02.qxd 1/31/07 9:55 PM Page 97

Exercises 97

Exercise 2.23 Complete the design of the seven-segment decoder segments Sc

through Sg (see Example 2.10):

(a) Derive Boolean equations for the outputs Sc through Sg assuming that inputs
greater than 9 must produce blank (0) outputs.

(b) Derive Boolean equations for the outputs Sc through Sg assuming that inputs
greater than 9 are don’t cares.
(c) Sketch a reasonably simple gate-level implementation of part (b). Multiple
outputs can share gates where appropriate.

Exercise 2.24 A circuit has four inputs and two outputs. The inputs, A3:0, repre-
sent a number from 0 to 15. Output P should be TRUE if the number is prime
(0 and 1 are not prime, but 2, 3, 5, and so on, are prime). Output D should be
TRUE if the number is divisible by 3. Give simplified Boolean equations for each
output and sketch a circuit.

Exercise 2.25 A priority encoder has 2N inputs. It produces an N-bit binary out-
put indicating the most significant bit of the input that is TRUE, or 0 if none of
the inputs are TRUE. It also produces an output NONE that is TRUE if none of
the input bits are TRUE. Design an eight-input priority encoder with inputs A7:0
and outputs Y2:0 and NONE. For example, if the input is 00100000, the output
Y should be 101 and NONE should be 0. Give a simplified Boolean equation for
each output, and sketch a schematic.

Exercise 2.26 Design a modified priority encoder (see Exercise 2.25) that
receives an 8-bit input, A7:0, and produces two 3-bit outputs, Y2:0 and Z2:0.
Y indicates the most significant bit of the input that is TRUE. Z indicates the
second most significant bit of the input that is TRUE. Y should be 0 if none of
the inputs are TRUE. Z should be 0 if no more than one of the inputs is TRUE.
Give a simplified Boolean equation for each output, and sketch a schematic.

Exercise 2.27 An M-bit thermometer code for the number k consists of k 1’s in
the least significant bit positions and M  k 0’s in all the more significant bit
positions. A binary-to-thermometer code converter has N inputs and 2N1
outputs. It produces a 2N1 bit thermometer code for the number specified by
the input. For example, if the input is 110, the output should be 0111111.
Design a 3:7 binary-to-thermometer code converter. Give a simplified Boolean
equation for each output, and sketch a schematic.

Exercise 2.28 Write a minimized Boolean equation for the function performed
by the circuit in Figure 2.85.
Chapter 02.qxd 1/31/07 9:55 PM Page 98

98 CHAPTER TWO Combinational Logic Design

C, D
A
00
01
10 0
11
Y
1

Figure 2.85 Multiplexer circuit

Exercise 2.29 Write a minimized Boolean equation for the function performed
by the circuit in Figure 2.86.

C, D A, B
00 00
01 01
10 10
Y
11 11

Figure 2.86 Multiplexer circuit

Exercise 2.30 Implement the function from Figure 2.80(b) using

(a) an 8:1 multiplexer

(b) a 4:1 multiplexer and one inverter

(c) a 2:1 multiplexer and two other logic gates

Exercise 2.31 Implement the function from Exercise 2.9(a) using

(a) an 8:1 multiplexer

(b) a 4:1 multiplexer and no other gates

(c) a 2:1 multiplexer, one OR gate, and an inverter

Exercise 2.32 Determine the propagation delay and contamination delay of the
circuit in Figure 2.83. Use the gate delays given in Table 2.8.
Chapter 02.qxd 1/31/07 9:55 PM Page 99

Exercises 99

Table 2.8 Gate delays for Exercises 2.32–2.35

Gate tpd (ps) tcd (ps)

NOT 15 10

2-input NAND 20 15

3-input NAND 30 25

2-input NOR 30 25

3-input NOR 45 35

2-input AND 30 25

3-input AND 40 30

2-input OR 40 30

3-input OR 55 45

2-input XOR 60 40

Exercise 2.33 Sketch a schematic for a fast 3:8 decoder. Suppose gate delays are
given in Table 2.8 (and only the gates in that table are available). Design your
decoder to have the shortest possible critical path, and indicate what that path is.
What are its propagation delay and contamination delay?

Exercise 2.34 Redesign the circuit from Exercise 2.24 to be as fast as possible.
Use only the gates from Table 2.8. Sketch the new circuit and indicate the critical
path. What are its propagation delay and contamination delay?

Exercise 2.35 Redesign the priority encoder from Exercise 2.25 to be as fast
as possible. You may use any of the gates from Table 2.8. Sketch the new
circuit and indicate the critical path. What are its propagation delay and
contamination delay?

Exercise 2.36 Design an 8:1 multiplexer with the shortest possible delay from
the data inputs to the output. You may use any of the gates from Table 2.7 on
page 88. Sketch a schematic. Using the gate delays from the table, determine
this delay.
Chapter 02.qxd 1/31/07 9:55 PM Page 100

100 CHAPTER TWO Combinational Logic Design

Interview Questions
The following exercises present questions that have been asked at interviews for
digital design jobs.

Question 2.1 Sketch a schematic for the two-input XOR function using only
NAND gates. How few can you use?

Question 2.2 Design a circuit that will tell whether a given month has 31 days
in it. The month is specified by a 4-bit input, A3:0. For example, if the inputs
are 0001, the month is January, and if the inputs are 1100, the month is
December. The circuit output, Y, should be HIGH only when the month speci-
fied by the inputs has 31 days in it. Write the simplified equation, and draw
the circuit diagram using a minimum number of gates. (Hint: Remember to
take advantage of don’t cares.)

Question 2.3 What is a tristate buffer? How and why is it used?

Question 2.4 A gate or set of gates is universal if it can be used to construct any
Boolean function. For example, the set {AND, OR, NOT} is universal.

(a) Is an AND gate by itself universal? Why or why not?

(b) Is the set {OR, NOT} universal? Why or why not?

(c) Is a NAND gate by itself universal? Why or why not?

Question 2.5 Explain why a circuit’s contamination delay might be less than
(instead of equal to) its propagation delay.
 David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, © 2007 by Elsevier Inc.
Exercise Solutions

SOLUTIONS 11

CHAPTER 2

2.1
(a) Y = AB + AB + AB
(b) Y = ABC + ABC
(c) Y = ABC + ABC + ABC + ABC + ABC
(d)
Y = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
(e)
Y = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD

2.3
(a) Y = A + B
(b) Y = ABC + ABC
(c) Y = AC + AB + AC
(d) Y = AB + BD + ACD
(e)
Y = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
This can also be expressed as:
Y = (A ⊕ B)(C ⊕ D) + (A ⊕ B)(C ⊕ D)

2.5
(a) Same as 2.4(a).
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, © 2007 by Elsevier Inc.
Exercise Solutions

12 SOLUTIONS chapter 2

2.4 (b)

A
B
C
Y

(c)

A B C

(d)

A B C D

(e)

A B C D

Y
 David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, © 2007 by Elsevier Inc.
Exercise Solutions

SOLUTIONS 13

2.7
(a) Y = AC + BC
(b) Y = A
(c) Y = A + B C + B D + BD

2.9
(a) Y = B + AC

B
A Y
C

(b) Y = AB

A
Y
B

(c) Y = AB + AC + AD + AE + BCD + BCE + DE

A B CD E

Y
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, © 2007 by Elsevier Inc.
Exercise Solutions

14 SOLUTIONS chapter 2

2.11

A
Y
B

Y=A

2.13
(a)

B B B
0 0
1 1

(b)

B C D (B C) + (B D) B (C + D)
0 0 0 0 0
0 0 1 0 0
0 1 0 0 0
0 1 1 0 0
1 0 0 0 0
1 0 1 1 1
1 1 0 1 1
1 1 1 1 1

(c)

B C (B C) + (B C)
0 0 0
0 1 0
1 0 1
1 1 1

2.15
Y = AD + ABC + ACD + ABCD
Z = ACD + BD
 David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, © 2007 by Elsevier Inc.
Exercise Solutions

SOLUTIONS 15

2.17

A
B
C
D
Y
E

Y = (A + B)(C + D) + E

2.19
Two possible options are shown below:

Y Y
AB AB
CD 00 01 11 10 CD 00 01 11 10

00 X 0 1 1 00 X 0 1 1

01 X X 1 0 01 X X 1 0

11 0 X 1 1 11 0 X 1 1

10 X 0 X X 10 X 0 X X

(a) Y = AD + AC + BD (b) Y = A(B + C + D)

2.21
Option (a) could have a glitch when A=1, B=1, C=0, and D transitions from
1 to 0. The glitch could be removed by instead using the circuit in option (b).
Option (b) does not have a glitch. Only one path exists from any given input
to the output.
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, © 2007 by Elsevier Inc.
Exercise Solutions

16 SOLUTIONS chapter 2

2.23 (a)

Sc Sd
D3:2 D3:2
D1:0 00 01 11 10 D1:0 00 01 11 10

00 1 1 0 1 00 1 0 0 1

01 1 1 0 1 01 0 1 0 0

11 1 1 0 0 11 1 0 0 0

10 0 1 0 0 10 1 1 0 0

Sc = D3D0 + D3D2 + D2D1 Sd = D3D1D0 + D3D2D0+ D3D2D1 +

D3D2D1D0 + D3D2D1D0
Se Sf
D3:2 D3:2
D1:0 00 01 11 10 D1:0 00 01 11 10

00 1 0 0 1 00 1 1 0 1

01 0 0 0 0 01 0 1 0 1

11 0 0 0 0 11 0 0 0 0

10 1 1 0 0 10 0 1 0 0

Se = D2D1D0 + D3D1D0 Sf = D3D1D0 + D3D2D1+ D3D2D0 + D3D2D1

 David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, © 2007 by Elsevier Inc.
Exercise Solutions

SOLUTIONS 17

Sg
D3:2
D1:0 00 01 11 10

00 0 1 0 1

01 0 1 0 1

11 1 0 0 0

10 1 1 0 0

Sg = D3D2D1 + D3D1D0+ D3D2D1 + D3D2D1

David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, © 2007 by Elsevier Inc.
Exercise Solutions

18 SOLUTIONS chapter 2

(b)

Sa Sb
D3:2 D3:2
D1:0 00 01 11 10 D1:0 00 01 11 10

00 1 0 X 1 00 1 1 X 1

01 0 1 X 1 01 1 0 X 1

11 1 1 X X 11 1 1 X X

10 0 1 X X 10 1 0 X X

Sa = D2D1D0 + D2D0 + D3 + D2D1 + D1D0 Sb = D1D0 + D1D0 + D2

Sc Sd
D3:2 D3:2
D1:0 00 01 = D D 11
S 10 + D + D
D + D2D D1:0 00 01 11 10
a 2 1 0 0 3 1

00 1 1 X 1 00 1 0 X 1

01 1 1 X 1 01 0 1 X 0

11 1 1 X X 11 1 0 X X

10 0 1 X X 10 1 1 X X

Sc = D1 + D0 + D2 Sd = D2D1D0 + D2D0+ D2D1 + D1D0

David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, © 2007 by Elsevier Inc.
Exercise Solutions

SOLUTIONS 19

Se Sf
D3:2 D3:2
D1:0 00 01 11 10 D1:0 00 01 11 10

00 1 0 X 1 00 1 1 X 1

01 0 0 X 0 01 0 1 X 1

11 0 0 X X 11 0 0 X X

10 1 1 X X 10 0 1 X X

Se = D2D0 + D1D0 Sf = D1D0 + D2D1+ D2D0 + D3

Sg
D3:2
D1:0 00 01 11 10

00 0 1 X 1

01 0 1 X 1

11 1 0 X X

10 1 1 X X

Sg = D2D1 + D2D0+ D2D1 + D3

David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, © 2007 by Elsevier Inc.
Exercise Solutions

20 SOLUTIONS chapter 2

(c)
D3 D2 D1 D0

Sa Sb Sc Sd Se Sf Sg
 David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, © 2007 by Elsevier Inc.
Exercise Solutions

SOLUTIONS 21

2.25
A7 A6 A5 A4 A3 A2 A1 A0 Y2 Y1 Y0 NONE
0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 1 0 0 0 0
0 0 0 0 0 0 1 X 0 0 1 0
0 0 0 0 0 1 X X 0 1 0 0
0 0 0 0 1 X X X 0 1 1 0
0 0 0 1 X X X X 1 0 0 0
0 0 1 X X X X X 1 0 1 0
0 1 X X X X X X 1 1 0 0
1 X X X X X X X 1 1 1 0

Y2 = A7 + A6 + A5 + A4

Y1 = A7 + A6 + A5 A4 A3 + A5 A4 A2

Y0 = A7 + A6 A5 + A6 A5 A4 A3 + A6 A5 A4 A2 A1

NONE = A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0

A7 A6 A5 A4 A3 A2 A1 A0

Y2

Y1

Y0

NONE
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, © 2007 by Elsevier Inc.
Exercise Solutions

22 SOLUTIONS chapter 2

2.27
Y6 = A2 A1 A0
Y5 = A2 A1
Y4 = A2 A1 + A2 A0
Y3 = A2
Y2 = A2 + A1 A0
Y1 = A2 + A1
Y0 = A2 + A1 + A0

A2 A1 A0

Y6

Y5

Y4

Y3
Y2

Y1

Y0
 HARRIS SOLUTION CHAPTER 2 (CORRECTION)
QUESTION 2.29

⊕ ⊕
 David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, © 2007 by Elsevier Inc.
Exercise Solutions

SOLUTIONS 23

2.31

A B C A C Y A Y
A B C Y 0 0 1 0 B+C
0 0 0 1 000 0 1 B 1 B
0 0 1 0 001 1 0 B
0 1 0 1 010 1 1 B
0 1 1 1 011 A
Y AC
1 0 0 0 100
C
1 0 1 0 101 00 0
B
1 1 0 1 110 B 01 Y
Y
1 1 1 1 111 10 1
11

(a) (b) (c)

2.33
tpd = tpd_NOT + tpd_AND3
= 15 ps + 40 ps
= 55 ps
tcd = tcd_AND3
= 30 ps

A2 A1 A0

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, © 2007 by Elsevier Inc.
Exercise Solutions

24 SOLUTIONS chapter 2

2.35
A7 A6 A5 A4 A3 A2 A1 A0

Y2

Y1

Y0

NONE

tpd = tpd_INV + 3tpd_NAND2 + tpd_NAND3

= [15 + 3 (20) + 30] ps
= 105 ps
tcd = 2tcd_NOR3 + tcd_AND3
= [35 + 30] ps
= 65 ps

Question 2.1

A
Y
B
 David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, © 2007 by Elsevier Inc.
Exercise Solutions

SOLUTIONS 25

Question 2.3
A tristate buffer has two inputs and three possible outputs: 0, 1, and Z. One
of the inputs is the data input and the other input is a control input, often called
the enable input. When the enable input is 1, the tristate buffer transfers the data
input to the output; otherwise, the output is high impedance, Z. Tristate buffers
are used when multiple sources drive a single output at different times. One and
only one tristate buffer is enabled at any given time.

Question 2.5
A circuit’s contamination delay might be less than its propagation delay be-
cause the circuit may operate over a range of temperatures and supply voltages,
for example, 3-3.6 V for LVCMOS (low voltage CMOS) chips. As temperature
increases and voltage decreases, circuit delay increases. Also, the circuit may
have different paths (critical and short paths) from the input to the output. A gate
itself may have varying delays between different inputs and the output, affect-
ing the gate’s critical and short paths. For example, for a two-input NAND gate,
a HIGH to LOW transition requires two nMOS transistor delays, whereas a
LOW to HIGH transition requires a single pMOS transistor delay.