Presentation:
Digital Logic Design
P R ESENT E D BY:
A ROOJ S H EH ZA DI
M EH R A B I M A N
KAIF
A L I H A MZA
JK Flip Flop:
A sequential logic circuit that can store a bit of information.
Characteristics:
1. Two inputs: J (set) and K (reset)
2. Two outputs: Q (output) and Q' (complement of output)
3. Clock input: CLK (or CP)
Circuit Diagram:
Characteristics Table:
Characteristic Equation: K̅Qn + JQ̅n
Excitation Table:
The excitation table shows us which input combinations we should use for a JK flip-flop to get
the output we want.
•X - Don't Care
•Qn - Current State
•Q(n+1) - Next State
•J and K - Two input values
SR Flip Flop:
Flip-Flop is a term that comes under digital electronics, and it is an electronic
component that is used to store one single bit of information.Diagrammatic
Representation of Flip FlopDiagrammatic.
Representation of Flip FlopSince Flip Flop is a sequential circuit so its input is based
upon two parameters, one is the current input and other is the output from
previous state. It has two outputs, both are complement of each other.
It may be in one of two stable states, either 0 or 1
Prerequisite:
Introduction of Sequential CircuitsConstruction of SR Flip FlopWe can construct SR
flip flop with two ways, one is with 2 NOR Gates + 2 AND Gates and other is with 4
NAND Gates.
Basic Block Diagram of SR Flip Flop
The basic block diagram contains S and R inputs, and between them is
clock pulse, Q and Q' is the complemented outputs.
Truth Table of SR Flip Flop
Given Below is the Truth Table of SR Flip Flop
Function Table of SR Flip Flop
Characteristic Equation
•The characteristic equation tells us about what will be the
next state of flip flop in terms of present state.
•In order to get the characteristic equation, K-Map is
constructed which will be shown as below:
•If we solve the above K-Map then the characteristic
equation will be Qn+1 = S + QnR’
Excitation Table
➢ Excitation Table basically tells about the
excitation which is required by flip flop to
go from current state to next state.
➢ Here, Qn is the current state, Qn+1 is the
next state outputs and S , R are the set
and reset inputs respectively.
D Flip Flop:
D flip flop is an electronic devices that is known as "delay flip flop" or "data flip flop"
which is used to store single bit of data.
•D flip flops can be either synchronous or asynchronous.
•The clock signal is required for the synchronous version of D flip flops but not for the
asynchronous one.
•The D flip flop has two inputs, data and clock input which controls the flip flop.
•When clock input is high, the data is transferred to the output of the flip flop.
•When the clock input is low, the output of the flip flop is held in its previous state.
Logic Circuit:
Working of D Flip Flop
D flip flop consist of a single input D and two outputs (Q and Q').
The basic working of D Flip Flop is as follows:
•When the clock signal is low, the flip flop holds its current state
and ignores the D input.
•When the clock signal is high, the flip flop samples and stores D
input.
•The value that was previously fed into the D input is reflected at
the flip flop's Q output.
• If D = 0 then Q will be 0.
• If D = 1 then Q will be 1.
•The Q' output of the flip flop is complemented by the Q output.
• If Q = 0 then Q' will be 1.
• If Q = 1 then Q' will be 0.
Characteristic Table of D Flip Flop
The characteristic table of the D flip flop displays the behavior of the flip flop for each
combination of input and current state. The characteristic table for a D flip flop is as
follows.
•D is the input, and Q is current state,
Q(n+1) is the next state outputs.
•Q(n+1) will always be zero when D is 0,
irrespective of current state of flip flop.
•When the input of the flip flop is 1, next
state of flip flop will always be 1,
regardless of the current state of flip flop.
D Flip Flop Excitation Table
•When the Q(n) is 0 and the D(n) is also 0, then
the Q(n+1) becomes 0. This situation explains the
condition of "hold" state.
•When the Q(n) is 0 but D(n) is 1, then the Q(n+1)
becomes 1. This situation explains the condition of
"set" state.
•When the Q(n) is 1 but D(n) is 0, then the Q(n+1)
becomes 0. This situation explains the condition of
"reset" state.
•When the Q(n) is 1 and the D(n) is also 1, then
the Q(n+1) becomes 1. This situation explains the
condition of "hold" state.
