OB233F
OB233F
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the design and audio noise is eliminated during (UVLO)
operation. o Over temperature protection (OTP) with
OB233F is offered in DIP7 package. auto- recovery
o On-Bright proprietary line input
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APPLICATIONS
Offline AC/DC flyback converter for
■ AC/DC adapter
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o Cycle-by-Cycle over-current threshold
setting for constant output power limiting
over universal input voltage range.
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■ PDA power supplies o Accurate overload protection (OLP).
■ Digital cameras and camcorder adapter o Over voltage protection(OVP)
■ VCR, SVR, STB, DVD&DVCD Player SMPS o Secondary rectifier short protection
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■ Open-frame SMPS
TYPICAL APPLICATION
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GENERAL INFORMATION
Pin Configuration Package Dissipation Rating
The OB233F is offered in DIP7 package as shown Package RJA (℃/W)
below. DIP7 75
Note: Drain Pin Connected to 100mm2 PCB copper clad.
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Min/Max storage temperature
-55 to 150℃
Tstg
Lead temperature (soldering,
260℃
10secs)
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Note: Stresses beyond those listed under “absolute
Ordering Information
Part Number Description
tia maximum ratings” may cause permanent damage to the device.
These are stress ratings only, functional operation of the
device at these or any other conditions beyond those indicated
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under “recommended operating conditions” is not implied.
OB233FSP DIP7, Pb-free Exposure to absolute maximum-rated conditions for extended
periods may affect device reliability.
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OB233F X X
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S:DIP7 P : Pb-free
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Marking Information
TERMINAL ASSIGNMENTS
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Pin Name I/O Description
GND P Ground
Feedback input pin. The PWM duty cycle is determined by voltage level into this pin
FB I
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and the current-sense signal at Pin 4.
VDD-G
Sense
P
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Internal gate driver power supply
Current sense input
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VDD P IC DC power supply Input
HV MOSFET drain pin. The drain pin is connected to the primary lead of the
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Drain O
transformer
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BLOCK DIAGRAM
VDD_G
2 Drain
5/6
Current Soft
Reference OTP Power
Driver MOSFET
VDD
3
Soft Start
Internal supply R Q
S OCP
LDO Extended
OSC Burst mode
SENSE
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Slope
UVLO compensation 4
POR
LEB
CPL Vth
Internal supply
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OVP
Burst
mode
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PWM Comparator
R FB
Debounce OLP 1
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R
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7 GND
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ELECTRICAL CHARACTERISTICS
(TA = 25℃, VDD=16V, unless otherwise noted)
Symbol Parameter Test Conditions Min Typ Max Unit
Supply Voltage (VDD)
VDD=UVLO(OFF)-1V,
Istartup VDD start up current measure leakage current 5 20 uA
into VDD
IVDD_Operation Operation current VFB=3V 1.6 mA
VDD under voltage lockout
UVLO(ON) 7.0 8.0 9.0 V
enter
VDD under voltage Lockout
UVLO(OFF) 15.2 16.2 17.2 V
Exit (Recovery)
Over voltage protection CS=0V,FB=3V ramp up
OVP(ON) 27.5 29 30.5 V
voltage VDD until gate clock is off
Feedback input section(FB pin)
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VFB_OPEN VFB Open Loop Voltage 4.9 5.5 6.1 V
Short FB pin to GND and
IFB_SHORT FB pin short circuit current 0.35 mA
measure current
Zero duty cycle FB
VTH_0D 0.8 V
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threshold voltage
VTH_PL
Power limiting
threshold voltage
Power limiting debounce
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FB
4.6 V
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TD_PL 50 mSec
time
ZFB_IN Input impedance 15.7 Kohm
Current sense input(Sense pin)
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control delay
start to turn off
Internal current limiting
VTH_OC FB=3.3V 0.72 0.75 0.78 V
threshold voltage
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Oscillator
Normal oscillation
FOSC 60 65 70 KHZ
frequency
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Frequency temperature
△fTemp 5 %
stability
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Mosfet section
MOSFET drain-source
BVdss 600 V
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breakdown voltage
Static drain to source on
Rdson 2.2 Ώ
resistance
Frequency shuffling
Frequency modulation
∆fOSC -4 4 %
range /base frequency
Over temperature protection
Over temperature protection trip point 150 ℃
CHARACTERIZATION PLOTS
(The characteristic graphs are normalized at Ta=25℃)
UVLO(OFF) (V)
18
UVLO(ON)(V)
9
16
8
14
7 12
6 10
-40 -10 20 50 80 110 140 -40 -10 20 50 80 110 140
Temperature(℃ ) Temperature(℃ )
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I_startup vs Temperature VDD vs Iop_n(uA)
5
1000
4
I_startup(uA)
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800
3
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Iop_n(uA)
600
2
400
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1 200
0 0
-40 -10 20 50 80 110 140 0 4 8 12 16 20 24 28
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Temperature(℃ ) VDD(V)
nf
1.05 70.00
1 68.00
Fosc(KHz)
Vth_oc(V)
0.95 66.00
0.9
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64.00
0.85
62.00
0.8
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0.75 60.00
0 10 20 30 40 50 60 70 -40 -10 20 50 80 110 140
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Duty(%) Temperature(℃)
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Rdson(Ω) vs Temperature
6
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5
4
Rdson(Ω)
3
2
1
0
25 50 75 100 125 150
Temperature(℃)
OPERATION DESCRIPTION
The OB233F is a low power off-line SMPS improve the conversion efficiency. At light load or
switcher optimized for off-line flyback converter no load condition, the FB input drops below burst
applications. The ‘extended burst mode’ control mode threshold level and device enters Burst
greatly reduces the standby power consumption Mode control. The gate drive output switches only
and helps the design easily to meet the when VDD voltage drops below a preset level and
international power conservation requirements. FB input is active to output an on state. Otherwise
the gate drive remains at off state to minimize the
Startup current and start up control switching loss and reduces the standby power
Startup current of OB233F is designed to be very consumption to the greatest extend.
low so that VDD could be charged up above The switching frequency control also eliminates
UVLO threshold level and device starts up quickly. the audio noise at any loading conditions.
A large value startup resistor can therefore be
used to minimize the power loss yet achieve a Oscillator operation
reliable startup in application. For AC/DC adapter The switching frequency of OB233F is internally
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with universal input range design, startup resistors fixed at 65kHz (typical). No external frequency
could be used together with a VDD capacitor to setting components are required for PCB design
provide a fast startup and yet low power simplification.
dissipation design solution.
Current sensing and leading edge blanking
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Operating current
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The operating current of OB233F is low at 1.6mA
(typical). Good efficiency is achieved with OB233F
Cycle-by-Cycle current limiting is offered in
OB233F current mode PWM control. The switch
current is detected by a sense resistor into the
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low operating current together with the ‘extended sense pin. An internal leading edge blanking
burst mode’ control features. circuit chops off the sensed voltage spike at initial
internal power MOSFET on state due to snubber
Soft start diode reverse recovery and surge gate current of
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OB233F features an internal 4ms (typical) soft internal power MOSFET so that the external RC
start to soften the electrical stress occurring in the filtering on sense input is no longer needed. The
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power supply during startup. It is activated during current limiting comparator is disabled and cannot
the power on sequence. As soon as VDD reaches turn off the internal power MOSFET during the
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UVLO(OFF), the peak current is gradually blanking period. The PWM duty cycle is
increased from nearly zero to the maximum level determined by the current sense input voltage and
of 0.75V. Every restart up is followed by a soft the FB input voltage.
start.
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modulation) is implemented in OB233F. The PWM generation. This greatly improves the close
oscillation frequency is modulated so that the tone loop stability at CCM and prevents the sub-
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energy is spread out. The spread spectrum harmonic oscillation and thus reduces the output
minimizes the conduction band EMI and therefore ripple voltage.
eases the system design.
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Driver
Extended burst mode operation The internal power MOSFET in OB233F is driven
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At light load or zero load condition, most of the by a dedicated gate driver for power switch control.
power dissipation in a switching mode power A too weak the gate drive strength results in
supply is from switching loss on the MOSFET, the higher conduction and switch loss of MOSFET
core loss of the transformer and the loss in the while too strong gate drive results in the
snubber circuit. The magnitude of power loss is in compromise of EMI.
proportion to the switching frequency. Lower
switching frequency leads to the reduction on the A good tradeoff is achieved through the built-in
power loss and thus conserves the energy. totem pole gate design with right output strength
The switching frequency is internally adjusted at and dead time control. The low idle loss and good
no load or light load condition. The switch EMI system design is easier to achieve with this
frequency reduces at light/no load condition to dedicated control scheme.
In addition to the gate drive control scheme shutdowns the power MOSFET when an over
mentioned, the gate drive strength can also be temperature condition is detected or the sense pin
adjusted externally by a resistor connected is opened
between VDD and VDDG, the falling edge of the
Drain output can be well controlled. It provides VDD is supplied by transformer auxiliary winding
great flexibility for system EMI design. output. When VDD voltage exceeds the internal
OVP threshold voltage (29V, typical) due to
Protection controls abnormal conditions, The power MOSFET is shut
Good power supply system reliability is achieved down until VDD drops below 8V (typical) , and
with its rich protection features including Cycle-by- device enters power on restart-up sequence
Cycle current limiting (OCP), over load protection thereafter.
(OLP), over voltage protection and under voltage
lockout on VDD (UVLO). When the secondary rectifier is shorted, the
transformer acts like a leakage inductance.
With On-Bright Proprietary technology, the OCP is Meanwhile, the current spike is extremely high.
line voltage compensated to achieve constant During high line input, the current in power
output power limit over the universal input voltage MOSFET is too high to wait for OLP delay time. To
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range. offer reliable design, OB233F shuts down the
switch and enters auto-recovery mode in this case.
At overload condition when FB input voltage
exceeds power limit threshold value for more than
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TD_PL, control circuit reacts to shut down the
switcher. Switcher restarts when VDD voltage
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drops below UVLO limit. Similarly, control circuit
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A1 0.381 0.015
A2 2.921 4.953 0.115 0.195
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IMPORTANT NOTICE
RIGHT TO MAKE CHANGES
On-Bright Electronics Corp. reserves the right to make corrections, modifications, enhancements,
improvements, and other changes to its products and services at any time and to discontinue any product
or service without notice. Customers should obtain the latest relevant information before placing orders
and should verify that such information is current and complete.
WARRANTY INFORMATION
On-Bright Electronics Corp. warrants performance of its hardware products to the specifications
applicable at the time of sale in accordance with its standard warranty. Testing and other quality control
techniques are used to the extent it deems necessary to support this warranty. Except where mandated
by government requirements, testing of all parameters of each product is not necessarily performed.
On-Bright Electronics Corp. assumes no liability for applications assistance or customer product design.
Customers are responsible for their products and applications using On-Bright’s components, data sheet
and application notes. To minimize the risks associated with customer products and applications,
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customers should provide adequate design and operating safeguards.
LIFE SUPPORT
On-Bright Electronics Corp.’s products are not designed to be used as components in devices intended to
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support or sustain human life. On-bright Electronics Corp. will not be held liable for any damages or
claims resulting from the use of its products in medical applications.
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MILITARY
On-Bright Electronics Corp.’s products are not designed for use in military applications. On-Bright
Electronics Corp. will not be held liable for any damages or claims resulting from the use of its products in
military applications.
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