AP64060

4.5V TO 40V INPUT, 600mA SYNCHRONOUS BUCK WITH ENHANCED EMI REDUCTION

Description Pin Assignments

The DIODES™ AP64060 is a 600mA, synchronous buck converter
TOP VIEW
with a wide input voltage range of 4.5V to 40V. The device fully
integrates a 600mΩ high-side power MOSFET and a 300mΩ low-side
power MOSFET to provide high-efficiency step-down DC-DC
ADVANCED INFORMATION

conversion. BST 1 6 SW

The AP64060 device is easily used by minimizing the external

component count due to its adoption of peak current mode control
along with its integrated loop compensation network.
GND 2 5 VIN
The AP64060 design is optimized for electromagnetic interference
(EMI) reduction. The device has a proprietary gate driver scheme to
resist switching node ringing without sacrificing MOSFET turn-on and
turn-off times, which reduces high-frequency radiated EMI noise FB 3 4 EN
caused by MOSFET switching.

The device is available in the TSOT26 package.

TSOT26

Features Applications
 VIN 4.5V to 40V  5V, 12V, and 24V distributed power bus supplies
 600mA Continuous Output Current  eMeters
 Less than 0.1% Output Ripple at 12V  Automotive devices
 90µA Low Quiescent Current (Pulse Frequency Modulation)  White goods and small home appliances
 2.2MHz Switching Frequency  FPGA, DSP, and ASIC supplies
 Supports Pulse Frequency Modulation (PFM)  General-purpose point-of-load devices
 Proprietary Gate Driver Design for Best EMI Reduction
 Precision Enable Threshold to Adjust UVLO
 Protection Circuitry
 Undervoltage Lockout (UVLO)
 Output Overvoltage Protection (OVP)
 Cycle-by-Cycle Peak Current Limit
 Thermal Shutdown
 Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)
 Halogen and Antimony Free. “Green” Device (Note 3)
 An automotive-compliant part is available under separate
datasheet (AP64060Q)

Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS), 2011/65/EU (RoHS 2) & 2015/863/EU (RoHS 3) compliant.
2. See https://www.diodes.com/quality/lead-free/ for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green" and
Lead-free.
3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and
<1000ppm antimony compounds.

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Typical Applications Circuit

5 1 C5
VIN BST
100nF
ADVANCED INFORMATION

AP64060 6
L1 OUTPUT
4 SW
OFF EN
D2
Optional C4 R1
.
OPEN 115kΩ
CIN COUT
2.2µF
3 2x10 µF
FB
2
R2
GND
22.1kΩ

Figure 1. Typical Application Circuit

VIN = 12V, VOUT = 5V, L =10μH VIN = 12V, VOUT = 3.3V, L =8.2μH
VIN = 24V, VOUT = 5V, L =10μH VIN = 24V, VOUT = 3.3V, L =8.2μH
100

90

80

70
Efficiency (%)

60

50

40

30

20

10

0
0.001 0.010 0.100 1.000
IOUT (A)

Figure 2. AP64060 Efficiency vs. Output Current

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Pin Descriptions
Pin Name Pin Number Function

High-Side Gate Drive Boost Input. BST supplies the drive for the high-side N-Channel power MOSFET. A 100nF
BST 1
capacitor is recommended from BST to SW to power the high-side driver.
ADVANCED INFORMATION

GND 2 Power Ground.

Feedback sensing terminal for the output voltage. Connect this pin to the resistive divider of the output.
FB 3
See Setting the Output Voltage section for more details.
Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn on the regulator and low to
EN 4 turn it off. Connect to VIN for automatic startup. The EN has a precision threshold of 1.21V for programing the UVLO.
See Enable section for more details.
Power Input. VIN supplies the power to the IC as well as the step-down converter power MOSFETs. Drive VIN with a
VIN 5 4.5V to 40V power source. Bypass VIN to GND with a suitably large capacitor to eliminate noise due to the switching
of the IC. See Input Capacitor section for more details.
Power Switching Output. SW is the switching node that supplies power to the output. Connect the output LC filter
SW 6
from SW to the output load.

Functional Block Diagram

VCC VCC
5 VIN
Regulator

EN 4 + ON Internal 0.8V
1.21V Reference
–
480kΩ +
CSA
-
FB 3 + OVP
0.88V -
1 BST

+ OCP
Ref -
- OVP
0.8V
+
Internal SS +
Error
Amplifier
COMP
- Control
VSUM 6 SW
+ Logic
PWM
+ Comparator

Thermal TSD
SE = 0.8V/T Shutdown
2MHz
Oscillator OSC
2 GND

Figure 3. Functional Block Diagram

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Absolute Maximum Ratings (@TA = +25°C, unless otherwise specified.) (Note 4)

Symbol Parameter Rating Unit
-0.3 to +42.0 (DC)
VIN Supply Pin Voltage V
-0.3 to +46.0 (400ms)
VFB Feedback Pin Voltage -0.3V to +6.0 V
ADVANCED INFORMATION

VEN Enable Pin Voltage -0.3 to +42.0 V

-0.3 to VIN + 0.3 (DC)
VSW Switch Pin Voltage V
-2.5 to VIN + 2.0 (20ns)
VBST Bootstrap Pin Voltage VSW - 0.3 to VSW + 6.0 V
TST Storage Temperature -65 to +150 °C
TJ Junction Temperature +170 °C
TL Lead Temperature +260 °C
ESD Susceptibility (Note 5)
HBM Human Body Model ±2000 V
CDM Charged Device Model ±1000 V
Notes: 4. Stresses greater than the Absolute Maximum Ratings specified above can cause permanent damage to the device. These are stress ratings only;
functional operation of the device at these or any other conditions exceeding those indicated in this specification is not implied. Device reliability can
be affected by exposure to absolute maximum rating conditions for extended periods of time.
5. Semiconductor devices are ESD sensitive and can be damaged by exposure to ESD events. Suitable ESD precautions should be taken when
handling and transporting these devices.

Thermal Resistance (Note 6)

Symbol Parameter Rating Unit
θJA Junction to Ambient TSOT26 80 °C/W
θJC Junction to Case TSOT26 39 °C/W

Note: 6. Test condition for TSOT26: Device mounted on FR-4 substrate, single-layer PC board, 2oz copper, with minimum recommended pad layout.

Recommended Operating Conditions (Note 7) (@ TA = +25°C, unless otherwise specified.)

Symbol Parameter Min Max Unit
VIN Supply Voltage 4.5 40 V
VOUT Output Voltage 0.8 26 V
TA Operating Ambient Temperature Range -40 +85 °C
TJ Operating Junction Temperature Range -40 +125 °C

Note: 7. The device function is not guaranteed outside of the recommended operating conditions.

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Electrical Characteristics (@ TJ = +25°C, VIN = 12V, unless otherwise specified. Min/Max limits apply across the recommended
junction temperature range, -40°C to +125°C, and input voltage range, 3.8V to 40V, unless otherwise specified.)

Symbol Parameter Test Conditions Min Typ Max Unit

ISHDN Shutdown Supply Current VEN = 0V — 1 10 μA
VEN = Floating,
ADVANCED INFORMATION

IQ Supply Current (Quiescent) R2 = OPEN, No Load, — 90 — μA

VBST - VSW = 5V
VIN Undervoltage Rising Threshold — — 4.2 4.4 V
UVLO
VIN Undervoltage Hysteresis — — 440 — mV
RDS(ON)1 High-Side Power MOSFET On-Resistance (Note 8) — — 600 — mΩ
RDS(ON)2 Low-Side Power MOSFET On-Resistance (Note 8) — — 300 — mΩ
IPEAK_LIMIT HS Peak Current Limit (Note 8) — 0.80 0.90 1.30 A
IVALLEY_LIMIT LS Valley Current Limit (Note 8) — — 0.7 — A
IPFMPK PFM Peak Current Limit VOUT = 5V, L = 10μH — 40 — mA
IZC Zero Cross Current Threshold — — 10 — mA
fSW Oscillator Frequency — — 2 — MHz
tON_MIN Minimum On-Time — — 60 — ns
VFB Feedback Voltage CCM, TJ = -40ºC to +125 ºC 784 800 816 mV
VEN_H EN Logic High — — 1.21 1.25 V
VEN_L EN Logic Low — 1.03 1.10 — V
tSS Soft-Start Time — — 1 — ms
TSD Thermal Shutdown Threshold (Note 8) — — 170 — °C
THys Thermal Shutdown Hysteresis (Note 8) — — 35 — °C

Note: 8. Compliance to the datasheet limits is assured by one or more methods: production test, characterization, and/or design.

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Typical Performance Characteristics (@ TA = +25°C, VIN = 12V, VOUT = 5V, unless otherwise specified.)

VIN = 12V, VOUT = 5V, L =15μH VIN =24V, VOUT = 5V, L =15μH
VIN = 12V, VOUT = 3.3V, L =10μH VIN = 24V, VOUT = 3.3V, L = 10μH
100 100
ADVANCED INFORMATION

90 90
80 80

Efficiency (%)
Efficiency (%)

70 70
60 60
50 50
40 40
30 30
20 20
10 10
0 0
0.001 0.010 0.100 1.000 0.001 0.010 0.100 1.000
IOUT (A) IOUT (A)

Figure 4. Efficiency vs. Output Current, VIN = 12V Figure 5. Efficiency vs. Output Current, VIN = 24V

IOUT = 0A IOUT = 0.3A IOUT = 0.6A VIN = 12V VIN = 24V

5.12 5.120
5.10 5.100
5.08 5.080
5.06 5.060
VOUT (V)

5.04 5.040
VOUT (V)

5.02 5.020
5.00 5.000
4.98 4.980
4.96 4.960
4.94 4.940
4.92 4.920
5 10 15 20 25 30 35 40 45 0.000 0.075 0.150 0.225 0.300 0.375 0.450 0.525 0.600
VIN (V) IOUT (A)

Figure 6. Line Regulation Figure 7. Load Regulation

0.809 88.0
0.808 84.0
0.807 80.0
0.806 76.0
0.805 72.0
Ton-min (nS)
VFB (V)

0.804 68.0
0.803 64.0
0.802 60.0
0.801 56.0
0.800 52.0
0.799 48.0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Temperature (°C) Temperature (°C)
Figure 8. Feedback Voltage vs. Temperature Figure 9. Ton-Min vs. Temperature

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Typical Performance Characteristics (@ TA = +25°C, VIN = 12V, VOUT = 5V, unless otherwise specified.) (continued)

116 2.00
112 1.80
108 1.60
ADVANCED INFORMATION

104 1.40
100 1.20

ISHDN (μA)
IQ (μA)

96 1.00
92 0.80
88 0.60
84 0.40
80 0.20
76 0.00
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Temperature (°C) Temperature (°C)
Figure 10. IQ vs. Temperature Figure 11. ISHDN vs. Temperature

VIN Rising POR VIN Falling UVLO 2.5

2.4
4.5
2.3
4.4
Frequency (MHz)

4.3 2.2
4.2 2.1
4.1
VIN (V)

2.0
4
3.9 1.9
3.8 1.8
3.7 1.7
3.6
3.5 1.6
-50 -25 0 25 50 75 100 125 150 1.5
0.00 0.08 0.15 0.23 0.30 0.38 0.45 0.53 0.60
Temperature (°C)
IOUT (A)
Figure 12. VIN Power-On Reset and UVLO vs. Temperature Figure 13. fSW vs. IOUT (A)

VOUT (10mV/div) VOUT (10mV/div)

IL (100mA/div)
IL (500mA/div)

VSW (10V/div) VSW (10V/div)

500ns/div 500ns/div

Figure 14. Output Voltage Ripple, VOUT = 5V; IOUT = 50mA Figure 15. Output Voltage Ripple, VOUT = 5V; IOUT = 600mA

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Typical Performance Characteristics (@ TA = +25°C, VIN = 12V, VOUT = 5V, unless otherwise specified.)

VOUT (10mV/div) VOUT (10mV/div)

ADVANCED INFORMATION

IL (100mA/div)
IL (500mA/div)

VSW (10V/div) VSW (10V/div)

500ns/div 500ns/div

Figure 16. Output Voltage Ripple, VOUT = 3.3V; IOUT = 50mA Figure 17. Output Voltage Ripple, VOUT = 3.3V; IOUT = 600mA

VOUT (200mV/div) VOUT (200mV/div)

IOUT (200mA/div) IOUT (200mA/div)

100μs/div 100μs/div

Figure 18. Load Transient, VIN = 12V, IOUT = 50mA to 600mA Figure 19. Load Transient, VIN = 24V, IOUT = 50mA to 600mA

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Typical Performance Characteristics (@ TA = +25°C, VIN = 12V, VOUT = 5V, unless otherwise specified.)

VEN (5V/div)

VEN (5V/div)
ADVANCED INFORMATION

VOUT (2V/div)

VOUT (2V/div)

IL (500mA/div) IL (500mA/div)

VSW (10V/div)

VSW (10V/div)

500μs/div 50μs/div

Figure 20. Startup Using EN, IOUT = 600mA Figure 21. Shutdown Using EN, IOUT = 600mA

VOUT (2V/div)

VOUT (2V/div)

IL (500mA/div)
IL (500mA/div)

VSW (10V/div) VSW (10V/div) 200μs/div

10μs/div

Figure 22. Output Short Protection, IOUT = 600mA Figure 23. Output Short Recovery, IOUT = 600mA

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 AP64060

Application Information

1 Pulse Width Modulation (PWM) Operation

The AP64060 device is a 4.5V-to-340V input, 600mA output, EMI friendly, fully integrated synchronous buck converter. Refer to the block diagram
in Figure 4. The device employs fixed-frequency peak current mode control. The internal 2MHz clock’s rising edge initiates turning on the
ADVANCED INFORMATION

integrated high-side power MOSFET, Q1, for each cycle. When Q1 is on, the inductor current rises linearly and the device charges the output
capacitor. The current across Q1 is sensed and converted to a voltage with a ratio of R T via the CSA block. The CSA output is combined with an
internal slope compensation, SE, resulting in VSUM. When VSUM rises higher than the COMP node, the device turns off Q1 and turns on the low-
side power MOSFET, Q2. The inductor current decreases when Q2 is on. On the rising edge of next clock cycle, Q2 turns off and Q1 turns on.
This sequence repeats every clock cycle.

The error amplifier generates the COMP voltage by comparing the voltage on the FB pin with an internal 0.8V reference. An increase in load
current causes the feedback voltage to drop. The error amplifier thus raises the COMP voltage until the average inductor current matches the
increased load current. This feedback loop regulates the output voltage. The internal slope compensation circuitry prevents subharmonic
oscillation when the duty cycle is greater than 50% for peak current mode control.

The peak current mode control, integrated loop compensation network, and built-in 4ms soft-start time simplifies the AP64060 footprint as well as
minimizes the external component count.

2 Pulse Frequency Modulation (PFM) Operation

In heavy load conditions, the AP64060 operates in forced PWM mode. As the load current decreases, the internal COMP node voltage also
decreases. At a certain limit, if the load current is low enough, the COMP node voltage is clamped and is prevented from decreasing any further.
The voltage at which COMP is clamped corresponds to the 200mA PFM peak inductor current limit. As the load current approaches zero, the
AP64060 enters PFM mode to increase the converter power efficiency at light load conditions. When the inductor current decreases to 50mA, zero
cross detection circuitry on the low-side power MOSFET, Q2, forces it off. The buck converter does not sink current from the output when the
output load is light and while the device is in PFM. Because the AP64060 works in PFM during light load conditions, it can achieve power
efficiency of up to 82% at a 5mA load condition.

The quiescent current of the AP64060 is 90μA typical under a no-load, non-switching condition.

3 Enable
When disabled, the device shutdown supply current is only 1μA. When applying a voltage greater than the EN logic high threshold (typical 1.21V,
rising), the AP64060 enables all functions and the device initiates the soft-start phase. The EN pin is a high-voltage pin and can be directly
connected to VIN to automatically start up the device as VIN increases. The AP64060 has a built-in 1ms soft-start time to prevent output voltage
overshoot and inrush current. When the EN voltage falls below its logic low threshold (typical 1.10V, falling), the internal SS voltage discharges to
ground and device operation disables.

The EN pin can also be used to program the undervoltage lockout thresholds. See Undervoltage Lockout (UVLO) section for more details.

4 Adjusting Undervoltage Lockout (UVLO)

Undervoltage lockout is implemented to prevent the IC from insufficient input voltages. The AP64060 device has a UVLO comparator that monitors
the input voltage and the internal bandgap reference. The AP64060 disables if the input voltage falls below 3.8V. In this UVLO event, both the
high-side and low-side power MOSFETs turn off.

For applications requiring higher VIN UVLO threshold voltages than is provided by the default setup, an external resistor R3 added in series to the
EN pin along with an internal 480kΩ configures the VIN UVLO threshold voltages as shown in Figure 24.

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Application Information (continued)

VIN
ADVANCED INFORMATION

R3

EN 2 +
1.21V
–
480kΩ

Figure 24. Programming UVLO

The resistive divider resistor values are calculated by:

(𝐕𝐎𝐍 − 𝟏. 𝟐𝟏𝐕)
𝐑𝟑 = 𝟒𝟖𝟎𝐤Ω Eq. 1
𝟏. 𝟐𝟏𝐕

Where:
 VON is the rising edge VIN voltage to enable the regulator and is greater than 4.2V

5 Output Overvoltage Protection (OVP)

The AP64060 implements output OVP circuitry to minimize output voltage overshoots during decreasing load transients. The high-side power
MOSFET turns off and the low-side power MOSFET turns on when the output voltage exceeds its target value by 10% in order to prevent the
output voltage from continuing to increase.

6 Overcurrent Protection (OCP)

The AP64060 has cycle-by-cycle peak current limit protection by sensing the current through the internal high-side power MOSFET, Q1. While Q1
is on, the internal sensing circuitry monitors its conduction current. Once the current through Q1 exceeds the peak current limit, Q1 immediately
turns off.

7 Thermal Shutdown (TSD)

If the junction temperature of the device reaches the thermal shutdown limit of 170°C, the AP64060 shuts down both its high-side and low-side
power MOSFETs. When the junction temperature reduces to the required level (135°C typical), the device initiates a normal power-up cycle with
soft-start.

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Application Information (continued)

8 Power Derating Characteristics

To prevent the regulator from exceeding the maximum recommended operating junction temperature, some thermal analysis is required. The
regulator’s temperature rise is given by:
ADVANCED INFORMATION

𝐓𝐑𝐈𝐒𝐄 = 𝐏𝐃 ∙ (𝛉𝐉𝐀 ) Eq. 2

Where:
 PD is the power dissipated by the regulator
 θJA is the thermal resistance from the junction of the die to the ambient temperature

The junction temperature, TJ, is given by:

𝐓𝐉 = 𝐓𝐀 + 𝐓𝐑𝐈𝐒𝐄 Eq. 3

Where:
 TA is the ambient temperature of the environment

For the TSOT26 package, the θJA is 80°C/W. The actual junction temperature should not exceed the maximum recommended operating junction
temperature of 150°C when considering the thermal design. Figure 25 shows a typical derating curve versus ambient temperature.

VOUT = 1.2V, 1.5V, 1.8V, 2.5V, 3.3V VOUT = 5V

1.00

0.90

0.80

0.70

0.60
IOUT (A)

0.50

0.40

0.30

0.20

0.10

0.00
0 20 40 60 80 100 120 140 160
Ambient Temperature (°C)

Figure 25. Output Current Derating Curve vs. Ambient Temperature, VIN = 12V

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Application Information (continued)

9 Setting the Output Voltage

The AP64060 has adjustable output voltages starting from 0.8V using an external resistive divider. An optional external capacitor, C4 in Figure 1,
of 10pF to 220pF improves the transient response. The resistor values of the feedback network are selected based on a design trade-off between
ADVANCED INFORMATION

efficiency and output voltage accuracy. There is less current consumption in the feedback network for high resistor values, which improves
efficiency at light loads. However, values too high cause the device to be more susceptible to noise affecting its output voltage accuracy. R1 can
be determined by the following equation:

𝐕𝐎𝐔𝐓
𝐑𝟏 = 𝐑𝟐 ∙ ( − 𝟏) Eq. 4
𝟎. 𝟖𝐕

Table 1 shows a list of recommended component selections for common AP64060 output voltages referencing Figure 1.

Table 1. Recommended Component Selections

AP64060
Output Voltage R1 R2 L CIN COUT C3 C4
(V) (kΩ) (kΩ) (µH) (µF) (µF) (nF) (pF)
1.8 27.4 22.1 4.7 2.2 10x2 100 OPEN
2.5 47.5 22.1 6.8 2.2 10x2 100 OPEN
3.3 69.8 22.1 8.2 2.2 10x2 100 OPEN
5.0 115 22.1 10 2.2 10x2 100 OPEN
12.0 309 22.1 22 2.2 10x3 100 OPEN

10 Inductor
Calculating the inductor value is a critical factor in designing a buck converter. For most designs, the following equation can be used to calculate
the inductor value:

𝐕𝐎𝐔𝐓 ∙ (𝐕𝐈𝐍 − 𝐕𝐎𝐔𝐓)

𝐋= Eq. 5
𝐕𝐈𝐍 ∙ ∆𝐈𝐋 ∙ 𝐟𝐬𝐰

Where:
 ∆IL is the inductor current ripple
 fSW is the buck converter switching frequency

For the AP64060, choose ∆IL to be 20% to 30% of the maximum load current of 1A.

The inductor peak current is calculated by:

∆𝐈𝐋
𝐈𝐋𝐏𝐄𝐀𝐊 = 𝐈𝐋𝐎𝐀𝐃 + Eq. 6
𝟐

Peak current determines the required saturation current rating, which influences the size of the inductor. Saturating the inductor decreases the
converter efficiency while increasing the temperatures of the inductor and the internal power MOSFETs. Therefore, choosing an inductor with the
appropriate saturation current rating is important. For most applications, it is recommended to select an inductor of approximately 4.7µH to 22µH
with a DC current rating of at least 35% higher than the maximum load current. For highest efficiency, the inductor’s DC resistance should be less
than 70mΩ. Use a larger inductance for improved efficiency under light load conditions.

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Application Information (continued)

11 Input Capacitor
The input capacitor reduces both the surge current drawn from the input supply as well as the switching noise from the device. The input capacitor
must sustain the ripple current produced during the on-time of Q1. It must have a low ESR to minimize power dissipation due to the RMS input
ADVANCED INFORMATION

current.

The RMS current rating of the input capacitor is a critical parameter and must be higher than the RMS input current. As a rule of thumb, select an
input capacitor with an RMS current rating greater than half of the maximum load current.

Due to large dI/dt through the input capacitor, electrolytic or ceramic capacitors with low ESR should be used. If using a tantalum capacitor, it must
be surge protected or else capacitor failure could occur. Using a ceramic capacitor greater than 10µF is sufficient for most applications.

12 Output Capacitor
The output capacitor keeps the output voltage ripple small, ensures feedback loop stability, and reduces both the overshoots and undershoots of
the output voltage during load transients. During the first few microseconds of an increasing load transient, the converter recognizes the change
from steady-state and enters 100% duty cycle to supply more current to the load. However, the inductor limits the change to increasing current
depending on its inductance. Therefore, the output capacitor supplies the difference in current to the load during this time. Likewise, during the first
few microseconds of a decreasing load transient, the converter recognizes the change from steady-state and sets the on-time to minimum to
reduce the current supplied to the load. However, the inductor limits the change in decreasing current as well. Therefore, the output capacitor
absorbs the excess current from the inductor during this time.

The effective output capacitance, COUT, requirements can be calculated from the equations below.

The ESR of the output capacitor dominates the output voltage ripple. The amount of ripple can be calculated by:

𝟏
𝐕𝐎𝐔𝐓𝐑𝐢𝐩𝐩𝐥𝐞 = ∆𝐈𝐋 ∙ (𝐄𝐒𝐑 + ) Eq. 7
𝟖 ∙ 𝐟𝐬𝐰 ∙ 𝐂𝐎𝐔𝐓

An output capacitor with large capacitance and low ESR is the best option. For most applications, a 22µF to 68µF ceramic capacitor is sufficient.
To meet the load transient requirements, the calculated COUT should satisfy the following inequality:

𝟐 𝟐
𝐋 ∙ 𝐈𝐓𝐫𝐚𝐧𝐬 𝐋 ∙ 𝐈𝐓𝐫𝐚𝐧𝐬
𝐂𝐎𝐔𝐓 > 𝐦𝐚𝐱 ( , ) Eq. 8
∆𝐕𝐎𝐯𝐞𝐫𝐬𝐡𝐨𝐨𝐭 ∙ 𝐕𝐎𝐔𝐓 ∆𝐕𝐔𝐧𝐝𝐞𝐫𝐬𝐡𝐨𝐨𝐭 ∙ (𝐕𝐈𝐍 − 𝐕𝐎𝐔𝐓)

Where:
 ITrans is the load transient
 ∆VOvershoot is the maximum output overshoot voltage
 ∆VUndershoot is the maximum output undershoot voltage

13 Bootstrap Capacitor and Low-Dropout (LDO) Operation

To ensure proper operation, a ceramic capacitor must be connected between the BST and SW pins. A 100nF ceramic capacitor is sufficient. If the
bootstrap capacitor voltage falls below 2.3V, the boot undervoltage protection circuit turns Q2 on for 220ns to refresh the bootstrap capacitor and
raise its voltage back above 2.85V. The bootstrap capacitor voltage threshold is always maintained to ensure enough driving capability for Q1.
This operation may arise during long periods of no switching such as in PFM with light load conditions. Another event that requires the refreshing
of the bootstrap capacitor is when the input voltage drops close to the output voltage. Under this condition, the regulator enters low-dropout mode
by holding Q1 on for multiple clock cycles. To prevent the bootstrap capacitor from discharging, Q2 is forced to refresh.

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 AP64060

Layout

PCB Layout
1. The AP64060 works at 600mA load current so heat dissipation is a major concern in the layout of the PCB. 2oz copper for both the top and
bottom layers is recommended.
ADVANCED INFORMATION

2. Place the input capacitors as closely across VIN and GND as possible.
3. Place the inductor as close to SW as possible.
4. Place the output capacitors as close to GND as possible.
5. Place the feedback components as close to FB as possible.
6. If using four or more layers, use at least the 2nd and 3rd layers as GND to maximize thermal performance.
7. Add as many vias as possible around both the GND pin and under the GND plane for heat dissipation to all the GND layers.
8. Add as many vias as possible around both the VIN pin and under the VIN plane for heat dissipation to all the VIN layers.
9. See Figure 26 for more details.

SW
C5
L1
BST 1 6 SW

GND 2

VIN
5 VIN
R1

FB 3 4 EN

VOUT
Cout
R2

CIN

GND
Figure 26. Recommended PCB Layout

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Document number: DS44123 Rev. 2 - 2 www.diodes.com © Diodes Incorporated
 AP64060

Ordering Information

AP64060 XX - X
ADVANCED INFORMATION

Package Packing
WU: TSOT26 7: Tape & Reel

Packing
Part Number Operation Mode Package Package Code
Qty. Carrier
AP64060WU-7 PFM/PWM TSOT26 WU 3000 7” Tape & Reel

Marking Information
TSOT26

( Top View )
6 5 4
7

XX : Identification Code
Y : Year 0~9
XX Y W X W : Week : A~Z : 1~26 week;
a~z : 27~52 week; z represents
1 2 3
52 and 53 week
X : Internal Code

Part Number Package Identification Code

AP64060WU-7 TSOT26 TG

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Document number: DS44123 Rev. 2 - 2 www.diodes.com © Diodes Incorporated
 AP64060

Package Outline Dimensions

Please see http://www.diodes.com/package-outlines.html for the latest version.

TSOT26
D
TSOT26
e1 01(4x)
ADVANCED INFORMATION

Dim Min Max Typ

E1/2
A — 1.00 —
A1 0.010 0.100 —
E/2
A2 0.840 0.900 —
c D 2.800 3.000 2.900
E1 E
Gauge Plane E 2.800 BSC
0 E1 1.500 1.700 1.600
Seating Plane
b 0.300 0.450 —
L
L2 c 0.120 0.200 —
e 0.950 BSC
e b 01(4x)
e1 1.900 BSC
A2 L 0.30 0.50 —
L2 0.250 BSC
A1
A θ 0° 8° 4°
Seating Plane
θ1 4° 12° —
All Dimensions in mm

Suggested Pad Layout

Please see http://www.diodes.com/package-outlines.html for the latest version.

TSOT26

Dimensions Value (in mm)

C 0.950
Y1 X 0.700
Y 1.000
Y1 3.200
Y

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 AP64060

IMPORTANT NOTICE

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ADVANCED INFORMATION

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AP64060 18 of 18 August 2022

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