Aging Phenomena
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              Bias Temperature Instability (BTI)
 Bias Temperature Instability (BTI) is recognized as the most
  relevant aging mechanism for current integrated circuits (ICs)
 BTI increases the absolute value of pMOS/nMOS conduction
  threshold voltage Vth (e.g., more than 50mV ↑ for pMOS, over
  ten years)
 Vth ↑  ↓ of transistors’ current  ↓ of transistors’ speed 
  ↑ IC’s delay over time
 If IC’s delay above a certain limit  the IC may fail to meet
  its timing constraints  reliability issues
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       Impact of BTI on Time-Critical Data-Paths
 Time-critical data-path consisting of:
       A combinational block Ci with propagation delay tpd
              Qi                  Si             Qi+1
  Di
        FFi
                     Ci
                                         FFi+1
                                                         Flip-flops FFi & FFi+1:
 CK
                   TCK
                             CK                           both sampling on the CK
                                                           rising edge
 CK
 Qi
                                                          tset : setup time of both FFs
 Si                             tpcq : for each FF, time interval
       tpcq         tpd           from the CK  edge to the
                                  tset
                                  instant at which the FF output
                                  reaches its final state value
 Si should reach its final state before the FFi+1 tset
 Due to BTI  Ci may become slower  possible late
  transitions of Si occurring during the FFi+1 tset  incorrect
  sampled datum
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       BTI Degradation: Reaction-Diffusion Model
 Stress phase (pMOS ON):
  high electric fields and temperatures
    Silicon-Hydrogen bonds at the Si-
   SiO2 interface dissociate  H
   atoms/molecules diffuse towards the
   gate & broken Si bonds acting as
   interface traps (IT) for holes in the
   channel  ↑ Vth
                                                                      ∆Vth
                                                           𝒒
 Vth increase given by: ∆𝑽𝒕𝒉 =            𝒕 ,               𝑵
                                                          𝑪𝒐𝒙 𝑰𝑻
  where NIT (t) is the # of ITs (changing in time)                           Stress             time
                                                                             (ON) t0
       𝑵𝑰𝑻 (𝒕) ∝ 𝑵𝟎 𝑫𝑯 𝒕                  𝒏   N0: initial number of unbroken Si-H bonds;
                                              n: fitting parameter (n=1/6);
                                              D : diffusion coefficient for H Cecilia Metra
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 BTI Degradation: Reaction-Diffusion Model
                  (cnt’d)
 Recovery phase (pMOS OFF):
   Some of the H atoms/molecules
    diffuse back towards the Si-SiO2
    interface and anneal some of the Si
    bonds  ↓ NIT  ↓Vth
   However, the previous Vth value
    (during the previous stress phase) is                         ∆Vth
    not fully recovered, since only some
    of the previously generated NIT are
    annealed  NIT (t1) > NIT (t=0)                                      Stress Recovery Stress   time
                                                                         (ON) t0 (OFF) t (ON)
                                                                                        1
                                 𝜹(𝒕 − 𝒕𝟎 )            NIT(t0): number of interface traps at
         𝑵𝑰𝑻 (𝒕) ∝ 𝑵𝑰𝑻 (𝒕𝟎 )                            the end of the stress phase
                                     𝒕
                                                       δ= H diffusion parameter
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     BTI Degradation: Frequency Independence
  With operating time,
    BTI degradation becomes independent of the transistor
      ON/OFF frequency, and becomes dependent only on the
      total ON time, with respect to the total OFF time
                                  Duty-Cycle = 50%
                                                                   ∆𝑽𝒕𝒉_𝒇𝟏 = ∆𝑽𝒕𝒉_𝒇𝟐
                                  Duty-Cycle = 50%
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                              BTI Degradation Modelling
 The trend of Vth variation over time (Vth) induced by BTI can
  be modeled as [2, 3]:          ∆V                                      th
   ∆𝑽𝒕𝒉 (𝒕) = 𝜸 𝒃 𝜶𝒏 ∆𝒕𝒏
 where:                                Stress
                                       (ON)
                                              Recovery
                                               (OFF)
                                                       Stress
                                                       (ON)
                                                                 time
     = ton/t, where t is the IC operating time; ton is the time
      during which the pMOS (nMOS) is under stress (ON)
    n (process dependent parameter) = 1/6 and b (process,
      temperature, and Vdd dependent parameter) = 3.910-3
      [V/(s1/6)], both for 65nm CMOS technology
    γ (fitting parameter) = 1 for pMOS and γ = 0.5 for nMOS
[2] S. Hamdioui, et al., “BTI Impact on Logical Gates in Nano-scale CMOS Technology”, in Proc. of IEEE International Symp. On Design and
    Diagnostics of Electronic Circuits & Systems (DDECS), 2012, pp. 348 – 353.
[3] W. Wang, et al., “An Efficient Model to Identify Critical Gates under Circuit Aging”, in Proc. of IEEE/ACM Int. Conf. on Computer-Aided
    Design, 2007, pp. 735-740.
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                            BTI Degradation:
                   Increasing with Technology Scaling
 As highlighted in [2], with technology scaling:
      Increase in the ICs’ power consumption  increase of ICs’
       operating temperature
      Lower scaling of Vdd than of oxide thickness  increase of
       electric field across the gate oxide during stress phase
       (transistor ON)
      BTI degradation is expected to increase with technology scaling
[2] M. Alam, et al., “A Comprehensive model of PMOS NBTI Degradation”, Microelectronics Rel. (Elsevier), 2005 (45), pp. 71 - 81.
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