DSD QUESTION BANK
PART- A
What is the logical expression for Y = A + A´B ?
(a) AB (b) A´B (c) A´+B (d) A + B
Minimum number of 2 input NOR Gates required to realize f = C + AB is?
(a) 2 (b) 3 (c) 4 (d) 5
Realize W = AB + CD + EF + GH using 2 input NAND gates.
(a) 6 (b) 7 (c) 8 (d) 9
Simplify f (a , b , c) = ∑m(0, 2, 5, 7)
(a) a'c' (b) a'c' + a'c (c) a'c' + ac’ (d) a'c' + ac
Find Product of Sum (POS) form of f (a, b, c, d) = πM (1, 4, 6, 9)
(a) (d + a + b'). (b’ + c’ + d') (b) (d + a + b'). (b + c + d')
(c) (d + a + b'). (b’ + c + d) (d) (d + a + b'). (b + c’ + d')
The number of inputs in a half adder is?
a) 8 b)2 c)11 d)32
How much input and output needed for demultiplexer?
a) Many outputs to one input b) One input many outputs
b) One input one output d) None of these
Why is a decoder used in digital electronics?
a) To convert non coded information into a binary coded form.
b) To convert coded information into a non-coded form.
c) It is used to divide address bus and data bus.
d) None of these
The basic building blocks of the arithmetic logic unit in digital computers are known as
a) Adders b) Attenuator c) Demultiplexer d) Subtractors
How many inputs does a full adder logic circuit will have?
a) 1 b) 2 c)3 d)4
Simplify A + AB + ABC + ABCD + ABCDE
(A )A+B (B) A (C) AB (D) 1
--------is the average transition delay for the signal to propagate from input to output when the binary input
changes in value.
(A)Propagation delay (B) Noise Margin
(C) Power Dissipation (D) Speed
De Morgan’s Theorem states that
(A) (A+B)’ = A’.B’ ; (A.B)’ = A’+B’
(B) (A+B)’ = A.B ; (A.B)’ = A+B
(C) (A+B)’ = A.B ; (A.B)’ = A’+B’
(D) (A+B)’ = A’.B’ ; (A.B)’ = A+B
Tell what value is to be considered for a “don’t care condition”?
A) 0
B) 1
C) Either 0 or 1
D) Any number except 0 and 1
Select which of the following is/are the universal logic gates?
A) OR and NOR
B) AND
C) NAND and NOR
D) NOT
Recall the number of control lines for an 8 to 1 multiplexer is
(A)1 (B) 2 (C) 3 (D) 4
Decoder has _____ input lines and _______ output lines
(A) 2ⁿ,1 (B) 1, 2ⁿ (C) 2ⁿ, n (D) n, 2ⁿ
Multiplexer has _____ input lines and _______ output line____selection lines
(A) 2ⁿ,1, n (B) 1, 2ⁿ, n (C) 2ⁿ, n, n (D) n, 2ⁿ, n
Which of the following gives the correct number of multiplexers required to build a 32 x 1 multiplexer?
A) Two 16 x 1 mux
B) Three 8 x 1 mux
C) Two 8 x 1 mux
D) Three 16 x 1 mux
Identify an important characteristic of a CMOS circuit
A) Noise immunity
B) Duality
C) Symmetricity
D) Noise Margin
PART-B
Design Half Adder circuit.
Simplify the given Boolean expression
F=[(A + B’) (C + D’)]’
F=[P (Q + R)]’
Draw and explain about TTL NAND Gate with Totem-pole Output
Illustrate 4 to 1 line Multiplexer with function table and logic diagram
Explain about Carry Look Ahead Adder with suitable diagram
Derive Commutative and Associative Law in Boolean Algebra
Define Decoder. Design & implement a 3 to 8 line Decoder
Explain Priority Encoder with Logical Diagram
PART – C
Simplify the following Boolean function for minimal SOP & POS
form using K-map i) F (A, B, C, D) = Σ (0,1,2,5,8,9,10) ii) F (A, B, C, D) =
πM(1,3,5,7,12,13,14,15)
Explain the different types of Programmable Logic Devices
Simply the Boolean Expression F (w, x, y, z) = Σ m(0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14) using K
map and implement with basic logic gates
Design a 32-bit ALU with 4 functions AND, OR, ADD, and SUBTRACT operations
Part-B
Design Half Adder circuit. Unit 1
Simplify the given Boolean expression UNIT 1
F=[(A + B’) (C + D’)]’
F=[P (Q + R)]’
Draw and explain about TTL NAND Gate with Totem-pole Output
UNIT 2
illustrate 4 to 1 line Multiplexer with function table and
logic diagram UNIT 2
Explain about Carry Look Ahead Adder with suitable diagram UNIT 1
Derive Commutative and Associative Law in Boolean Algebra
UNIT 1
define Decoder. Design & implement a 3 to 8 line Decoder.
UNIT 2
Explain Priority Encoder with Logical Diagram UNIT 2
Part c
Simplify the following Boolean function for minimal SOP & POS
form using K-map i) F (A, B, C, D) = Σ (0,1,2,5,8,9,10) ii)
F (A, B, C, D) = πM(1,3,5,7,12,13,14,15)
Explain the different types of Programmable Logic Devices
Simply the Boolean Expression F (w, x, y, z) = Σ m(0, 1, 2, 4,
5, 6, 8, 9, 12, 13, 14) using K map and implement with basic
logic gates
Design a 32-bit ALU with 4 functions AND, OR, ADD, and SUBTRACT operations
