COURSE FILE– AS PER NBA REQUIREMENTS

Part-I
- Syllabus
- Course information sheet
- Course Objectives, Course Outcomes
- Mapping onto PEO & PO
- Model Lesson Plan
- Lecture notes
- OHP/LCD Sheets/CDs
- University question papers
- Internal Question Papers with key
- Assignment Topics
- Tutorial Sheets
- Unit wise-Question Bank
- Gaps & Plans for Add-on programs
- Topics beyond Syllabus-References
- Result Analysis, Remedial/Corrective Action
- Learning Outcome Assessment, Mapping onto PO
- Web References

Part-II
- Lesson Plan, Time Table
- Teacher Log Book/ Attendance Register
- Daily Delivery Recording
- Continuous Evaluation-Marks (Tests, Assignments etc)
- Sample Answer Sheets (of Test Papers)
- Sample Assignment Sheets
- Record of Tutorial Classes
- Record of Remedial Classes
- Makeup Tests
- Guest Lecturers Conducted
- Details of Add-on Programs

The Internal Quality Audit Cell (IQAC) team along with 2 faculty members from each
department should verify and certify all course files and submit the same to the NBA
coordinator.
 SYLLABUS
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY
HYDERABAD
III Year B.Tech, ECE -II Sem L T/P/D C
4 1/-/- 4
MICROPROCESSORS AND MICRCONTROLLERS-56012
UNIT-I
8086ARCHITECTURE: Introduction to 8085 Microprocessor, 8086 Architecture-Functional
diagram, Register Organization, Memory Segmentation, Programming Model, Memory addresses,
Physical memory organization, Architecture of 8086, signal descriptions of 8086- common
function signals, Minimum and Maximum mode signals, Timing diagrams, Interrupts of 8086.
UNIT-II
INSTRUCTION SET AND ASSEMBLY LANGUAGE PROGRAMMING OF 8086:
Instruction formats, addressing modes, instruction set, assembler directives, macros, simple
programs involving logical, branch and call instructions, sorting, evaluating arithmetic
expressions, string manipulations.
UNIT-III
I/O INTERFACE: 8255 PPI, various modes of operation and interfacing to 8086, Interfacing
keyboard, display, stepper motor interfacing, D/A & A/D converter.
UNIT-IV
INTERFACING WITH ADVANCED DEVICES: Memory interfacing to 8086, Interrupt
structure of 8086, Vector interrupt table, Interrupt service routine. Introduction to DOS and BIOS
interrupts, Interfacing Interrupt Controller 8259 DMA Controller 8257 to 8086.
UNIT-V
COMMUNICATION INTERFACE: Serial communication standards, Serial data transfer
schemes. 8251 USART architecture and interfacing. RS- 232, IEEE-488, Prototyping and trouble
shooting.

UNIT-VI
INTRODUCTION TO MICROCONTROLLERS: Overview of 8051 microcontroller,
Architecture, I/O Ports, Memory organization, addressing modes and instruction set of 8051,
simple programs.
UNIT-VII:
8051 REAL TIME CONTROL: Interrupts, timer/ Counter and serial communication,
programming Timer Interrupts, programming external hardware interrupts, programming the
serial communication interrupts, programming 8051 timers and counters.
UNIT-VIII
THE AVR RISC MICROCONTROLLER ARCHITECTURE: Introduction, AVR Family
architecture, Register File, The ALU, Memory access and Instruction execution. I/O memory.
EEPROM, I/O ports, Timers. UART, Interrupt Structure.

COURSE INFORMATION SHEET

PROGRAMME: Electronics and Communication DEGREE: BTECH
Engineering
COURSE: Microprocessors and Microcontrollers SEMESTER: III /II CREDITS: 4
COURSE CODE: 56012 REGULATION: COURSE TYPE: CORE
R09
COURSE AREA/DOMAIN: CORE CONTACT HOURS: 4+1 (Tutorial) hours/Week
CORRESPONDING LAB COURSE CODE (IF ANY): LAB COURSE NAME: Microprocessors and
56606 Microcontrollers

0SYLLABUS

UNIT DETAILS HOURS

I 8086ARCHITECTURE: Introduction to 8085 Microprocessor, 8086 Architecture-Functional diagram, 8

Register Organization, Memory Segmentation, Programming Model, Memory addresses, Physical memory
organization, Architecture of 8086, signal descriptions of 8086- common function signals, Minimum and
Maximum mode signals, Timing diagrams, Interrupts of 8086.
II INSTRUCTION SET AND ASSEMBLY LANGUAGE PROGRAMMING OF 8086: Instruction 6
formats, addressing modes, instruction set, assembler directives, macros, simple programs involving logical,
branch and call instructions, sorting, evaluating arithmetic expressions, string manipulations.
III 6
I/O INTERFACE: 8255 PPI, various modes of operation and interfacing to 8086, Interfacing keyboard,
display, stepper motor interfacing, D/A & A/D converter.
IV INTERFACING WITH ADVANCED DEVICES: Memory interfacing to 8086, Interrupt structure of 6
8086, Vector interrupt table, Interrupt service routine. Introduction to DOS and BIOS interrupts, Interfacing
Interrupt Controller 8259 DMA Controller 8257 to 8086.
V COMMUNICATION INTERFACE: Serial communication standards, Serial data transfer schemes. 8251 6
USART architecture and interfacing. RS- 232, IEEE-488, Prototyping and trouble shooting.
VI INTRODUCTION TO MICROCONTROLLERS: Overview of 8051 microcontroller, Architecture, I/O 7
Ports, Memory organization, addressing modes and instruction set of 8051, simple programs.
VII 8051 REAL TIME CONTROL: Interrupts, timer/ Counter and serial communication, programming Timer 6
Interrupts, programming external hardware interrupts, programming the serial communication interrupts,
programming 8051 timers and counters.
VIII THE AVR RISC MICROCONTROLLER ARCHITECTURE: Introduction, AVR Family architecture, 6
Register File, The ALU, Memory access and Instruction execution. I/O memory. EEPROM, I/O ports,
Timers. UART, Interrupt Structure.
TOTAL HOURS 51
Tutorial Classes 10
Descriptive Tests 02
Classes for beyond syllabus 03
Remedial Classes/NPTEL 04
Total Number of Classes 70

TEXT/REFERENCE BOOKS:
 T/R BOOK TITLE/AUTHORS/PUBLICATION

Text Book Advanced microprocessor and Peripherals - A.K.Ray and K.M.Bhurchandi, TMH, 2000.
Text Book The 8051 Micro controllers Programming – Kenneth J Ayala –3rd Edition- Penram International publications
Text Book The AVR RISC Microcontroller and Embedded Systems using assembly and c –Mohammad Ali Mazidi,
Sarmad Naimi,sepehr Naimi.
Reference Micro Processors & Interfacing – Douglas V. Hall, 2007.
Book
Reference The 8088 and 8086 Micro Processors: Programming, Interfacing, Software, hardware and Applications –
Book Walter. A.Triebel, Avatar Singh, N.K.Srinath, 2007, Pearson

COURSE PRE-REQUISITES:

CODE COURSE NAME DESCRIPTION YEAR-SEM

Students will learn the basic concepts like
54010 Switching Theory and Logic Design Number Systems, A&L operations, II - II
Latches, Memories and their designing.
Students learn the computer types, bus
54012 Computer Organization structures, stack organization, memory III -I
system, pipelining

COURSE OBJECTIVE:

1 To develop an in-depth understanding of the operation of microprocessors and microcontrollers, machine language
programming & interfacing techniques.

COURSE OUTCOMES:

PO
S.NO DESCRIPTION MAPPING
CO1: Students will be able to learn working of various processors and their applications A

CO2: Students can be able to differentiate the Micro processor and Micro controller and will be B,K,L
able to write programs and execute them based on instruction set
CO3: Understand the interfacings of various I/O peripherals with 8086 and 8051 E,I
CO4: Understand various Data transfer schemes; interrupt structures of 8085, 8086 and 8051, J,K,L
AVR and communication interfaces

GAPS IN THE SYLLABUS - TO MEET INDUSTRY/PROFESSION REQUIREMENTS:

 S.NO DESCRIPTION PROPOSED ACTIONS
1 Pin configuration of 8085
2 Addressing modes of 8085 NPTEL videos
3 Various types of ADC and DAC circuits
4 Logic families Extra classes by using PPT’s

TOPICS BEYOND SYLLABUS/ADVANCED TOPICS/DESIGN:

1 Procedures or Subroutines
2 Differences b/w 80186,80286,80386,80486 Microprocessors
3 Pentium series
4 Dual core Processor

WEB SOURCE REFERENCES:

1 www.nptel.edu.in
Microprocessor & Microcontroller Prof. AjitPal, IITK
2 http://makeuseofit.weebly.com/uploads/6/4/1/7/6417762/8088__8086_microprocessrs_by_walter_a_tribal_and_avtar_singh.pdf
(Solution Manual: The 8088 and 8086 Micro Processors – Walter A.Triebel and Avatar singh, PHI, 4th Edition, 2003)
3 http://www.slideshare.net/vivekspatel7/programming-8051-timers
4 http://cse.iitkgp.ac.in/~soumya/embcs/the-8051-microcontroller-0314772782.pdf (Solution Manual 8051 Book- Ayala)
5 http://nec.edu.np/faculty/chandrat/8086imp.pdf
6 http://cse.iitkgp.ac.in/~soumya/embcs/the-8051-microcontroller-0314772782.pdf
7 http://galia.fc.uaslp.mx/~cantocar/microprocesadores/EL_Z80_PDF_S/8051.PDF

DELIVERY/INSTRUCTIONAL METHODOLOGIES:
√CHALK & TALK √STUD. ASSIGNMENT ☐ WEB RESOURCES √LCD/SMART BOARDS
☐ STUD. SEMINARS ☐ ADD-ON COURSES

ASSESSMENT METHODOLOGIES-DIRECT OOLS:

√HOME ASSIGNMENTS √ ASSIGNMENTS √ ONLINE EXAMINATIONS √ SESSIONALS
√SEMESTER END EXAMINATION

ASSESSMENT METHODOLOGIES-INDIRECT TOOLS:

√PROGRAM LEVEL STATISTICS √EXIT STUDENT FEEDBACK
√ALUMINI FEEDBACK √EMPLOYER FEEDBACK
√COURSE LEARNING FEEDBACK

Prepared by Approved by
(Faculty)
INSTITUTE VISION & MISSION
VISION:
To be a world –class educational and research institution in the service of humanity by promoting
high quality Engineering, Management and Pharmacy education.

MISSION:
Institute Mission in pursuance of its vision is:
1: Imbibe soft skills and technical skills.
2: Develop the faculty to reach the international standards.
3: Maintain high academic standards and teaching quality that promotes the analytical thinking
and independent judgment.
4: Promote research, innovation and Product development by collaboration with reputed foreign
universities.
5: Offer collaborative industry programs in emerging areas and spirit of enterprise.

DEPARTMENT VISION & MISSION

VISION:
To be a premier department of Electronics & Communication Engineering in the region.

MISSION:
1. Nurture young individuals into knowledgeable, skillful and ethical professionals in their
pursuit of electronics and communication engineering.
2. Nurture the faculty to expose them to world-class infrastructure.
3. Sustain high performance by excellence in teaching, research and innovations.
4. Extensive partnerships and collaborations with foreign universities for technology up
gradation.
5. Develop Industry-Interaction for innovation and product development.

PROGRAMME EDUCATIONAL OBJECTIVES

1. Graduates shall have the ability to apply knowledge across the disciplines and in emerging
areas of Electronics and Communication Engineering for higher studies, research
employability and handle the realistic problems.
2. Graduates shall have good communication skills, possess ethical conduct, sense of
responsibility to serve the society, and protect the environment.
3. Graduates shall have strong foundation in academic excellence, soft skills, managerial
skills, leadership qualities and understand the need for lifelong learning for a successful
professional career.

PROGRAMME OUTCOMES
 A. An ability to apply knowledge of mathematics, science, and engineering
B. An ability to design and conduct experiments, as well as to analyze and interpret data
C. An ability to design a system, component, or process to meet desired needs within realistic
constraints such as economic, environmental, social, political, ethical, health and safety,
manufacturability, and sustainability
D. An ability to function on multidisciplinary teams
E. An ability to identify, formulate, and solve engineering problems
F. An understanding of professional and ethical responsibility
G. An ability to communicate effectively
H. The broad education necessary to understand the impact of engineering solutions in a
global, eco-nomic, environmental, and societal context
I. An recognition of the need for, and an ability to engage in life-long learning
J. A knowledge of contemporary issues
K. An ability to use the techniques, skills, and modern engineering tools necessary for
engineering Practice
L. An in-depth ability to use a combination of Software, Hardware and experimental
techniques practiced in circuits, physical electronics, communication, networks, systems
and programming

MAPPING OF PEOs WITH POs:

Programme
Educational Programme outcomes
objectives

A B C D E F G H I J K L

PEO1 √ √ √ √ √ √ √ √ √

PEO2 √ √ √ √ √ √ √

PEO3 √ √ √ √ √ √ √ √ √ √

MODEL LESSION PLAN

 Cumulative
No of Classes
S. No Name of the Topic number of Teaching AID
required
periods
8086 ARCHITECTURE
Introduction to 8085 Microprocessor 01 01 LCD
8086 Architecture-Functional diagram 01 02 LCD
Register Organization, Memory Segmentation 01 03 Chalk & Talk
Programming Model, Memory addresses, Physical memory
UNIT-I 01 04 Chalk & Talk
organization
Architecture of 8086, signal descriptions of 8086- common
02 06 Chalk & Talk
function signals
Minimum and Maximum mode signals, Timing diagrams, 01 07 Chalk & Talk
Interrupts of 8086 01 08 Chalk & Talk
INSTRUCTION SET AND ASSEMBLY LANGUAGE
PROGRAMMING OF 8086
Instruction formats, Addressing modes 02 10 Chalk & Talk
Instruction set, Assembler directives 01 11 LCD
UNIT-II
Macros, Simple programs involving logical, branch and call 02 13 Chalk & Talk
instructions
Sorting, evaluating arithmetic expressions, String 01 14 Chalk & Talk
manipulations
I/O INTERFACE
8255 PPI Architecture 01 15 Chalk & Talk
Various modes of operation 01 16 Chalk & Talk
UNIT-III Interfacing to 8086 01 17 Chalk & Talk
Interfacing keyboard , Interfacing display 01 18 LCD
Stepper motor interfacing 01 19 LCD
D/A and A/D converters 01 20 LCD
INTERFACING WITH ADVANCED DEVICES
Memory interfacing to 8086 01 21 Chalk & Talk
Interrupt structure of 8086 01 22 Chalk & Talk
Vector interrupt table, Interrupt service routine 01 23 Chalk & Talk
UNIT-IV Introduction to DOS and BIOS interrupts 01 24 Chalk & Talk
Interfacing Interrupt Controller 8259 to 8086 01 25 LCD
DMA Controller 8257 to 8086 01 26 LCD
COMMUNICATION INTERFACE
Serial communication standards 01 27 Chalk & Talk
Serial data transfer schemes 01 28 Chalk & Talk
UNIT-V
8251 USART architecture and interfacing 02 30 LCD
RS- 232, IEEE-488 01 31 Chalk & Talk
Prototyping and trouble shooting 01 32 Chalk & Talk
INTRODUCTION TO MICROCONTROLLERS
Overview of 8051 microcontroller 01 33 Chalk & Talk
8051Architecture 01 34 LCD
I/O Ports, Memory organization 02 36 Chalk & Talk
UNIT-VI
Addressing modes 01 37 Chalk & Talk
Instruction set of 8051 01 38 Chalk & Talk
Simple programs based on 8051 01 39 Chalk & Talk
 8051 REAL TIME CONTROL
Interrupts of 8051 01 40 Chalk & Talk
Timer/ Counter and serial communication 01 41 Chalk & Talk
Programming Timer Interrupts 01 42 Chalk & Talk
UNIT-VII
Programming external hardware interrupts 01 43 Chalk & Talk
Programming the serial communication interrupts 01 44 Chalk & Talk
Programming 8051 timers/ counters 01 45 Chalk & Talk
THE AVR RISC MICROCONTROLLER
ARCHITECTURE
Introduction, AVR Family architecture 01 46 LCD
Register File, The ALU 01 47 Chalk & Talk
UNIT-VIII
Memory access and Instruction execution 01 48 Chalk & Talk
I/O memory, EEPROM 01 49 Chalk & Talk
I/O ports, Timers 01 50 Chalk & Talk
UART Architecture, Interrupt Structure 01 51 Chalk & Talk
TOTAL HOURS 51
Tutorial Classes 10
Descriptive Tests 02
Classes for beyond syllabus 03
Remedial Classes/NPTEL 04
Total Number of Classes 70

OBJECTIVE BITS
UNIT I
 1. The binary representation of hexadecimal number ABC is ……………………

A.101010111100

B.101010111000

C.011010111100

D.101010111111

2.8085 microprocessor is an --------------- device

A.PMOS

B.CMOS

C.NMOS

D.QMOS

3.------------------ register deals with sequencing the execution of instructions

A.Stack pointer

B.program counter

C.accumulator

D.flag
4. -----------------flag is used in 8086 for string manipulation instructions

A.DF

B.AF

C.OF

D.PF

5. 8086 as -------------------- of segment registers

A.3

B.5

C.4

D.2

6. Data storage in stack is designed in _______________method.

A.First in first out

 B.last in last out

C.first in last out

D.last in first out

7. ----------- is a special component used in 8086 for block transfer of data to or from a port

A.BMA

B.DNA

C.DMA
D.BNA

8.The first operand in the IN instruction must be ----------register for byte transfer

A.CL

B.BL

C.AL

D.DL

9. …………….IC is used as clock generator for 8086

A.8087

B.8284

C.8088

D.8294

10. A processor is in minimum mode when its MN/MX pin is strapped to -------volts

A.+50

B.+5

C.0

D.-5

11.An instruction to be executed by the coprocessor is indicted when ----------instruction appears in the program
sequence

A.TRUE
 B.FALSE

C.TEST

D.ESC

12.One of the following addressing modes is not possible in 8085.

A.Indexed addressing

B.Indirect addressing

C.Direct addressing

D.Indirect register address

13.The speed of a microprocessor is usually measured by the

A.Microprocessor’s throughput.

B.Speed with which it performs I/P and O/P operations.

C.Time required executing a basic instruction.

D.Time required processing a small operation.

14.Which of the following is an 8085 hardware interrupt?

A.TRAP

B.RST6.5

C.RST7.5

D.All the above

15.Which of the following is does NOT belong to 8085 flag register

A.Carry flag

B.Sign flag

C.Zero flag

D.One flag

16.Instruction that sets the carry flag

A. CY set
 B. STR

C. STC

D. Set CY

17.Which of the following does the task of displaying the result computed by the microprocessor?

A. Cathode Ray Tube (CRT)

B. Light-Emitting diodes (LED’S)

C. Laser printer

D. All of the above.

18.In 8086 microprocessor which of the following is Not a register pair register

A.B-C pair

B.F-G pair

C.H-L pair

D.D-E pair

19.Zero Flag is to _____ if the result of an arithmetic operation is zero.

A.1

B.0

C.-1

D.2

20. An interrupt initiated by a signal on the NMI pin is called a __________

A.NON maskable interrupt

B.Number mask able interrupt

C.NOT mask able interrupt

D.None of the above

21.There are two power connection for +5 volts in 8085 they are

A.Vss and Vgg

 B.Vcc and Vss

C.Vcc and Vgg

D.None of the above

22. Which of the following is the function of microprocessor

A. Receiving input

B. Performing computations.

C. Storing data & instructions

D. All of the above.

23. 8086 processor has ------------- address pins out of which ---------------- number of pins are used as data pins

A. 16,8

B. 16,14

C. 20,16

D. 20,8
24.In 8086 is a --------------------bit microprocessor and is fabricated using ------------technology

A. 16,CMOS

B. 8,HMOS

C. 20,NMOS

D. 16,HMOS

25.8086 can be operated in Two modes they are -----------------------and--------------

A. Minimum, Maximum

B. External, internal

C. Mode1, Mode2

D. Data, address

UNIT-II
1. A ..……….. is an identifier that is assigned the address of the first byte of the instruction in which it appears
A. Operand

B.mnemonic

C.Label

D.Comment

2. In which instruction the flags are not affected

A.LDS

B.DAA

C.ADC

D.DAS

3.--------------- instruction is used to call a procedure

A.CALL

B.RET

C.PROC

D.NEAR
4.---------------is a prefix used in 8086 machine language that simplifies the use of string primitives with loops

A.REP

B.LOOP

C.LODS

D.MOVS

5.LODSB instruction will automatically increment __________register.

A.DI

B.SI

C.DS

D.ES
6.DAD re instruction mean

A.Add the content of specified reg. to center of HL & store the result in HL

B.Add 8 bit data given in inst” to center of one & store the result in reg

C.Add 10 bit data given in inst to contact of HL & stout the result in HL
 D.None of the above
7. Instruction that avoids unnecessary jumps to terminate the prog

A. NOP

B. HLT

C. EOP

D. OI

8. Instruction cycle can be dined as sum of

A. Instruction fetch + Instruction decode

B. Instruction fetch + instruction Execute

C. Instruction fetch + instruction exit

D. All of above

9. Instruction cycle use ________ m/c cycle,

A. 1-5

B. 1-16

C. 1-8

D. None of above

10. If there are two operands, the _______ operand appears first.

A.destination

B.Destination

C.source

D.label
11.----------------and ------------------- instructions provide a means of moving two bytes between HL
register and a RAM address

A .LDAX & STAX

B. LHLD & SHLD

C. LDA& STA

D. PUSH & POP

12. _________ and___________instructions are specifically used to change the status of carry flag

A. STI,CLI

B.STC,CLC
 C. MOV,LEA

D. DAA,XCHG

13. In 8086 the …………instruction is used to simplify the decrementing, testing and branching.
This instruction uses _______as Counter register.

A. Loop, CX

B. JMP, CX

C. DEC, AX

D. INC, AX
14. In 8086 all programmed communication with the I/O ports is done by the ----------- and ------------
instructions

A. MOV, OUT

B. LOAD, MOVE

C. IN, OUT

D. IN, LOAD
15. The 8086 receives bus request through its ………. pin and issues grants from its ………… pin .A request
is made when a potential master sends ……. to ………… pin

A. HOLD,HLDA,1,HOLD

B. HLDA,HOLD,1,HLDA

C. HOLD,HLDA,0,HOLD

D. HLDA,HOLD,0,HLDA

16. one period of the clock to the MPU is called

A. Instruction cycle

B. Machine cycle

C. T-State

17. The abbreviated word that denotes the operation performed by an instruction is called

A. Opcode

B. Mnemonic

C. Operand
18. when an instruction operates on only one particular operand the addressing mode used is

A. Register

B. Direct

C. Register indirect

D. Implicit

19. for the instructions of the type MVI M, XX where M denotes a memory location the number of
machine cycles required is

A. 1

B. 2

C.3

D.4

20. The addressing mode used in the instruction XCHG

A. Register

B. Direct

C. Register indirect

D. Implicit

E. Immediate

21.the flags affected by the double byte addition instructions are

A. All flags

B. All flags other than carry

C. Only carry flag

22. For the instruction ADD M, the number of machine cycles required is

A.1

B.2

C.3

D.4

23. In the instruction SUB M, the addressing mode used is

 A. Register

B. Direct

C. Register indirect

D. Implicit

E. Immediate

24. In the instruction INRM, M denotes

A.16 bit memory address

B. 8 bit data

C. Memory location pointed by HL register pair

25. The 16 bit registers which cannot be stored in the stack using a single PUSH instruction are

A. HL

B. BC

C. SP

D. PSW

E. PC

UNIT III
1. The device that enables the microprocessor to read data from the external devices is
a) printer b) joystick c) display d) reader
Answer: b
Explanation: Since joystick is an input device, it reads data from the external devices.

2. The example of output device is

a) CRT display b) 7-segment display c) printer d) all of the mentioned
Answer: d
Explanation: The output device transfers data from microprocessor to the external devices.

3. The input and output operations are respectively similar to the operations,
a) read, read b) write, write c) read, write d) write, read
Answer: c
Explanation: The input activity is similar to read operation and the output activity is similar to
write operation.

4. The operation, IOWR (active low) performs

a) write operation on input data b) write operation on output data
c) read operation on input data d) read operation on output data
Answer: b
Explanation: IOWR (active low) operation means writing data to an output device and not an
input device.

5. The latch or IC 74LS373 acts as

a) good input port b) bad input port
c) good output port d) bad output port
Answer: c
Explanation: If the output port is to source large currents, the port lines must be buffered. So, the
latch is used as it acts as good output port.

6. While performing read operation, one must take care that much current should not be
a) sourced from data lines b) sinked from data lines
c) sourced or sinked from data lines d) sinked from address lines
Answer: c
Explanation: More current should not be sourced or sinked from data lines while reading to
avoid loading.

7. To avoid loading during read operation, the device used is

a) latch b) flipflop c) buffer d) tristate buffer
Answer: d
Explanation: A tristate buffer is used as an input device to overcome loading.
8. The chip 74LS245 is
a) bidirectional buffer b) 8-bit input port
c) one that has 8 buffers d) all of the mentioned
Answer: d
Explanation: The chip 74LS245 is a bidirectional buffer that contains 8 buffers and may be used
as an 8-bit input port. But while using as an input device, only one direction is useful.

9. In 74LS245, if DIR is 1, then the direction is from

a) inputs to outputs b) outputs to inputs
c) source to sink d) sink to source
Answer: a
Explanation: If DIR is 1, then the direction is from A(inputs) to B(outputs).

10. In memory-mapped scheme, the devices are viewed as

a) distinct I/O devices b) memory locations
c) only input devices d) only output devices
Answer: b
Explanation: In memory-mapped scheme, the devices are viewed as memory locations and are
addressed likewise.

11. DAC (Digital to Analog Converter) finds application in

a) digitally controlled gains b) motor speed controls
c) programmable gain amplifiers d) all of the mentioned
Answer: d
Explanation: DAC is used in digitally controlled gains, motor speed controls and programmable
gain amplifiers.

12. To save the DAC from negative transients the device connected between OUT1 and OUT2 of
AD 7523 is
a) p-n junction diode b) Zener
c) FET d) BJT (Bipolar Junction transistor)
Answer: b
Explanation: Zener is connected between OUT1 and OUT2 pins of AD7523 to save from
negative transients.

13. An operational amplifier connected to the output of AD 7523 is used

a) to convert current output to output voltage
b) to provide additional driving capability
c) as current-to-voltage converter
d) all of the mentioned
Answer: d
Explanation: An operational amplifier is used as a current-to-voltage converter to convert current
output to output voltage and also provides additional driving capability to the DAC.
14. The DAC 0800 has a settling time of
a) 100 milliseconds b) 100 microseconds
c) 50 milliseconds d) 50 microseconds
Answer: a
Explanation: DAC 0800 has a settling time of 100 milliseconds.

15. The device that is used to obtain an accurate position control of rotating shafts in terms of
steps is
a) DC motor b) AC motor c) Stepper motor d) Servo motor
Answer: c
Explanation: Stepper motor employs rotation of its shaft in terms of steps, rather than continuous
rotation as in case of AC or DC motors.

16. The internal schematic of a typical stepper motor has

a) 1 winding b) 2 windings c) 3 windings d) 4 windings
Answer: d
Explanation: the internal schematic of a typical stepper motor has 4 windings.

17. The number of pulses required for one complete rotation of the shaft of the stepper motor is
equal to the
a) number of internal teeth on a rotor
b) number of internal teeth on a stator
c) number of internal teeth on a rotor and stator
d) number of external teeth on a stator
View Answer
Answer: a
Explanation: The number of pulses required for one complete rotation of the shaft of the stepper
motor is equal to the number of internal teeth on its rotor.

18. A simple scheme for rotating the shaft of a stepper motor is called
a) rotating scheme
b) shaft scheme
c) wave scheme
d) none
View Answer
Answer: c
Explanation: In this scheme, the windings are applied with the required voltage pulses, in a
cyclic fashion.

19. The firing angles of thyristors are controlled by

a) pulse generating circuits
b) relaxation oscillators
c) microprocessor
d) all of the mentioned
View Answer
Answer: d
Explanation: In early days, the firing angles were controlled by pulse generating circuits like
relaxation oscillators and now, they are accurately fired using a microprocessor.

20. The Isolation transformers are generally used for

a) protecting low power circuit
b) isolation
c) protecting low power circuit and isolation
d) none
View Answer
Answer: c
Explanation: Any switching component of a high power circuit may be sufficient to damage the
microprocessor system. So, to protect the low power circuit isolation transformers are used. They
are also used if isolation is necessary.

UNIT –IV
1. The time taken by the ADC from the active edge of SOC(start of conversion) pulse till the
active edge of EOC(end of conversion) signal is called
a) edge time
b) conversion time
c) conversion delay
d) time delay
View Answer
Answer: c
Explanation: Broadly speaking, the time taken by the converter to calculate the equivalent digital
data output from the moment of the start of conversion is called conversion delay.
2. The popular technique that is used in the integration of ADC chips is
a) successive approximation
b) dual slope integration
c) successive approximation and dual slope integration
d) none
View Answer
Answer: c
Explanation: Successive approximation and dual slope integration are the most popular
techniques that are used in the integrated ADC chips.
3. The procedure of algorithm for interfacing ADC contain
a) ensuring stability of analog input
b) issuing start of conversion pulse to ADC
c) reading digital data output of ADC as equivalent digital output
d) all of the mentioned
View Answer
Answer: d
Explanation: The general algorithm for interfacing ADC contains ensuring stability of analog
input, issuing start of conversion pulse to ADC, reading end of conversion signal to mark the end
of conversion process, reading digital data output of ADC as equivalent digital output.
4. Which is the ADC among the following?
a) AD 7523
b) 74373
c) 74245
d) ICL7109
View Answer
Answer: d
Explanation: AD 7523 is a DAC(Digital to analog converter), 74373 is a latch, 74245 is
transreceiver and ICL7109 is an ADC.
5. The conversion delay in successive approximation of an ADC 0808/0809 is
a) 100 milliseconds
b) 100 microseconds
c) 50 milliseconds
d) 50 milliseconds
View Answer
Answer: b
Explanation: The conversion delay is 100microseconds which is low as compared to
otherconverters.
6. The number of inputs that can be connected at a time to an ADC that is integrated with
successive approximation is
a) 4
b) 2
c) 8
d) 16
View Answer
Answer: c
Explanation: As these converters internally have 3:8 analog multiplexer, at a time 8 different
analog inputs can be connected to the chip.
7. ADC 7109 integrated by Dual slope integration technique is used for
a) low cost option
b) slow practical applications
c) low complexity
d) all of the mentioned
View Answer
Answer: d
Explanation: Compared to other 12-bit ADCs, it is of very low cost and useful for slow practical
applications.
8. Which of the following is not one of the phase of total conversion cycle?
a) autozero phase
b) conversion phase
c) signal integrate phase
d) deintegrate phase
View Answer
Answer: b
Explanation: autozero phase, signal integrate phase and deintegrate phase are the three phases of
total conversion cycle.
9. Which of the following phase contain feedback loop in it?
a) autozero phase
b) signal integrate phase
c) deintegrate phase
d) none
View Answer
Answer: a
Explanation: A feedback loop is closed around the system to charge the autozero capacitor to
compensate for the offset voltages in the buffer amplifier, integrator and comparator.
10. In the signal integrate phase, the differential input voltage between IN LO(input low) and IN
HI(input high) pins is integrated by the internal integrator for a fixed period of
a) 256 clock cycles
b) 1024 clock cycles
c) 2048 clock cycles
d) 4096 clock cycles
View Answer
Answer: c
Explanation: The internal integrator needs 2048 clock cycles to integrate voltage difference
between input low and input high.

11. DAC (Digital to Analog Converter) finds application in

a) digitally controlled gains
b) motor speed controls
c) programmable gain amplifiers
d) all of the mentioned
View Answer
Answer: d
Explanation: DAC is used in digitally controlled gains, motor speed controls and programmable
gain amplifiers.
12. To save the DAC from negative transients the device connected between OUT1 and OUT2 of
AD 7523 is
a) p-n junction diode
b) Zener
c) FET
d) BJT (Bipolar Junction transistor)
View Answer
Answer: b
Explanation: Zener is connected between OUT1 and OUT2 pins of AD7523 to save from
negative transients.
13. An operational amplifier connected to the output of AD 7523 is used
a) to convert current output to output voltage
b) to provide additional driving capability
c) as current-to-voltage converter
d) all of the mentioned
View Answer
Answer: d
Explanation: An operational amplifier is used as a current-to-voltage converter to convert current
output to output voltage and also provides additional driving capability to the DAC.
14. The DAC 0800 has a settling time of
a) 100 milliseconds
b) 100 microseconds
c) 50 milliseconds
d) 50 microseconds
View Answer
Answer: a
Explanation: DAC 0800 has a settling time of 100 milliseconds.
15. The device that is used to obtain an accurate position control of rotating shafts in terms of
steps is
a) DC motor
b) AC motor
c) Stepper motor
d) Servo motor
View Answer
Answer: c
Explanation: Stepper motor employs rotation of its shaft in terms of steps, rather than continuous
rotation as in case of AC or DC motors.
16. The internal schematic of a typical stepper motor has
a) 1 winding
b) 2 windings
c) 3 windings
d) 4 windings
View Answer
Answer: d
Explanation: the internal schematic of a typical stepper motor has 4 windings.
17. The number of pulses required for one complete rotation of the shaft of the stepper motor is
equal to the
a) number of internal teeth on a rotor
b) number of internal teeth on a stator
c) number of internal teeth on a rotor and stator
d) number of external teeth on a stator
View Answer
Answer: a
Explanation: The number of pulses required for one complete rotation of the shaft of the stepper
motor is equal to the number of internal teeth on its rotor.
18. A simple scheme for rotating the shaft of a stepper motor is called
a) rotating scheme
b) shaft scheme
c) wave scheme
d) none
View Answer
Answer: c
Explanation: In this scheme, the windings are applied with the required voltage pulses, in a
cyclic fashion.
19. The firing angles of thyristors are controlled by
a) pulse generating circuits
b) relaxation oscillators
c) microprocessor
d) all of the mentioned
View Answer
Answer: d
Explanation: In early days, the firing angles were controlled by pulse generating circuits like
relaxation oscillators and now, they are accurately fired using a microprocessor.
20. The Isolation transformers are generally used for
a) protecting low power circuit
b) isolation
c) protecting low power circuit and isolation
d) none
View Answer
Answer: c
Explanation: Any switching component of a high power circuit may be sufficient to damage the
microprocessor system. So, to protect the low power circuit isolation transformers are used. They
are also used if isolation is necessary
21. The device that enables the microprocessor to read data from the external devices is
a) printer
b) joystick
c) display
d) reader
View Answer
Answer: b
Explanation: Since joystick is an input device, it reads data from the external devices.
22. The example of output device is
a) CRT display
b) 7-segment display
c) printer
d) all of the mentioned
View Answer
Answer: d
Explanation: The output device transfers data from microprocessor to the external devices.
23. The input and output operations are respectively similar to the operations,
a) read, read
b) write, write
c) read, write
d) write, read
View Answer
Answer: c
Explanation: The input activity is similar to read operation and the output activity is similar
towrite operation.
24. The operation, IOWR (active low) performs
a) write operation on input data
b) write operation on output data
c) read operation on input data
d) read operation on output data
View Answer
25. The latch or IC 74LS373 acts as
a) good input port
b) bad input port
c) good output port
d) bad output port
View Answer
Answer: c
Explanation: If the output port is to source large currents, the port lines must be buffered. So, the
latch is used as it acts as good output port.
26. While performing read operation, one must take care that much current should not be
a) sourced from data lines
b) sinked from data lines
c) sourced or sinked from data lines
d) sinked from address lines
View Answer
Answer: c
Explanation: More current should not be sourced or sinked from data lines while reading to
avoid loading.
27. To avoid loading during read operation, the device used is
a) latch
b) flipflop
c) buffer
d) tristate buffer
View Answer
Answer: d
Explanation: A tristate buffer is used as an input device to overcome loading.
28. The chip 74LS245 is
a) bidirectional buffer
b) 8-bit input port
c) one that has 8 buffers
d) all of the mentioned
View Answer
29. In 74LS245, if DIR is 1, then the direction is from
a) inputs to outputs
b) outputs to inputs
c) source to sink
d) sink to source
View Answer
Answer: a
Explanation: If DIR is 1, then the direction is from A(inputs) to B(outputs).

30. In memory-mapped scheme, the devices are viewed as

a) distinct I/O devices
b) memory locations
c) only input devices
d) only output devices
View Answer
Answer: b
Explanation: In memory-mapped scheme, the devices are viewed as memory locations and are
addressed likewise.

UNIT-V
1. In Asynchronous mode, the transmitter and receiver works at
a) Same clock b) Different clock
c) Both d) None

2. Block of Characters will be transmitted in

a) Synchronous mode b) Asynchronous mode
c) Both d) None

3. In Asynchronous mode, the start bit is

a) Logic high b) Tri-state
c) Logic low d) None

4. In 8251, the transmit buffer will converts data from

a) Serial to Parallel b) Parallel to Serial
c) Both d) None

5. Data transmitted in only one direction. This type of transmission is called as

a) Half-duplex b) Full duplex
c) Simplex d) All

6. In asynchronous transmission, when valid stop bit is not detected at the end of
every character, which is known as
a) Framing error b) Over run error
c) Parity error d) none

7. In 8251, all errors in status register are reset by __bit of command register
a) EH b) IR
c) RTS d) ER
8. If TxC = 19,200 Hz and the baud rate is 1200, the baud rate factor
a) 1 b) 64
c) 32 d) 16

9. In 8251, in mode register, if Bl = 1 and B o = 0, the 8251 will work in

a) Asynchronous mode with BRF= 1 b) Asynchronous mode BRF = 16
c) Asynchronous mode with BRF = 64 d) Synchronous mode

10. RS - 232C is available in

a) 7-Pin and 25 Pin connectors b) 8-Pin and 24 Pin connectors
c) 7 Pin and 23 Pin connectors d) none

11. If the data can be transmitted as the Voltage, we use

a) 20 ma current loop b) RS - 232C
c) IEEE-488 d) None

12. MC 1488 & MC 1489 art.

a) Multiplexers b) Voltage translators
c) Current translators d) none

13. If there is logic 1 at the i/p of MC 1488 line driver, it converts in

a) +8v b) +9V
c) -9V d) None

14. In 20 ma Current loop standard, 20 ma current flows when it is In

a) Mark state (1) b) Space State (0)
c) Both d) None

15. How many data lines are available in IEEE 488 (GPIB)
a) 32 b) 16
c) 64 d) 8

16. In IEEE 488 (GPIB), the device which receives data from other instruments is
called as Listener

17. If the software exists in the external hardware, to run the software we use
Emulator

18. In trouble shooting, the first step that we have to do is Check for power supply

19. For 8251, TxD is Output Pin

20. For 8251, the Pin RTS is Output Pin

21. Trouble shooting is a form of problem solving

22. USART standards for Universal synchronous asynchronous receiver

transmitter

23. 8251 has two registers

24. In the early stages of development Prototyping assists to indentify the problem

25. Data line which can transfer in only one direction is referred as Simplex

UNIT-VI

1. 8051 micro controller has how many ports

a) 3 b) 1 c) 2 d) 4

2. Which of the registers 8051 support indirect addressing

a) R6-R7 b) R0-R7 c) R0-R1 d) R0-R6

3. Which of the register of 8051 is 16 bit

a) A b) PSW c) DPTR d) SP

4. Which of the opcode is for 8 bit displacement

a) LMJP b) SJMP c) CALL d) AJMP

5. 8051 has number of register banks

a) 3 b) 1 c) 2 d) 4
6. 8051 is of -----pin package
a) 40 b) 50 c) 20 d) 30

7. ALE of 8051 stands for

a) Address latch enable b) Addition latch enable
c) Address low enable d) Addition low enable

8. Internal data memory of 8051 is of

a) 256 B b) 64 B c) 216 B d) 250 B

9. External data memory of 8051 is of

a) 34 KB b) 64 KB c) 16 KB d) 23 KB
10. Internal program memory of 8051 is of
a) 4 KB b) 64 KB c) 16 KB d) 50 KB

11. External program memory of 8051 is of

a) 34 KB b) 64 KB c) 16 KB d) 23 KB

12. Direct addressing mode is used for accessing

a) Internal memory b) External memory
c) RAM d) ROM

13. 8051 has number of user defined flags

a) 126 b) 124 c) 122 d) 128

14. 8051 has the crystal oscillator with frequency of

a) 12 MHz b) 10 MHz c) 11 MHz d) 13 MHz

15. Which port of 8051 has special functions

a) Port 3 b) Port 1 c) Port2 d) Port 4

16. Match the following:

1) TCON i) contains status information
2) SBUF ii) timer / counter control register.
3) TMOD iii) idle bit, power down bit
4) PSW iv) serial data buffer for Tx and Rx.
5) PCON v) timer/ counter modes of operation.
Ans) 1->ii, 2-> iv, 3->v, 4->i, 5->iii.

17. In 8051 an external interrupt 1 vector address is of 3H and causes of interrupt if high to
low transition on pin INT1
18. The 8051 microcontroller is of 4 pin package as an 8 processor.
19. The SP is of 8 bit wide register.
20. After reset, SP register is initialized to address7H
21. Address range of SFR Register bank is 80H-FFH
22. P3.6 of port 3 is has a function as write control signal for external data memory
23. In 8051 which interrupt has highest priority IE0
24. Number of general-purpose register of 8051 is 8
25. 8051 doesn’t have DMA controller as its inbuilt peripheral
 UNIT-VII
1. Which of the following is an external interrupt?
a) INT0(active low) b) INT2(active low) c) Timer0 interrupt d) Timer1 interrupt
Answer: a
Explanation: INT0(active low) and INT1(active low) are two external interrupt inputs provided
by 8051.

2. The interrupts, INT0(active low) and INT1(active low) are processed internally by flags
a) IE0 and IE1 b) IE0 and IF1 c) IF0 and IE1 d) IF0 and IF1
Answer: a
Explanation: The interrupts, INT0(active low) and INT1(active low) are processed internally by
the flags IE0 and IE1.

3. The flags IE0 and IE1, are automatically cleared after the control is transferred to respective
vector, if the interrupt is
a) level-sensitive b) edge-sensitive c) in serial port d) in parallel port
Answer: b
Explanation: If the interrupts are programmed as edge sensitive, the flags IE0 and IE1 are
automatically cleared after the control is transferred to respective vector.

4. If the external interrupt sources control the flags IE0 and IE1, then the interrupt programmed
is
a) level-sensitive b) edge-sensitive c) in serial port d) in parallel port
Answer: a
Explanation: If the interrupts are programmed as level sensitive, then the flags IE0 and IE1 are
controlled by external interrupt sources themselves.

5. The pulses at T0 or T1 pin are counted in

a) timer mode b) counter mode c) idle mode d) power down mode
Answer: b
Explanation: In counter mode, the pulses are counted at T0 or T1 pin.

6. In timer mode, the oscillator clock is divided by a prescalar

a) (1/8) b) (1/4) c) (1/16) d) (1/32)
Answer: d
Explanation: In timer mode, the oscillator clock is divided by a prescalar (1/32) and then given to
the timer.

7. The serial port interrupt is generated if

a) RI is set b) RI and TI are set c) either RI or TI is set d) RI and TI are reset
Answer: c
Explanation: The serial port interrupt is generated if atleast one of the two bits, RI and TI is set.

8. In serial port interrupt, after the control is transferred to the interrupt service routine, the flag
that is cleared is
a) RI b) TI c) RI and TI d) none
Answer: d
Explanation: In serial port interrupt, after the control is transferred to the interrupt service
routine, neither of the flags is cleared.

9. The atleast number of machine cycles for which the external interrupts that are programmed
level-sensitive should remain high is
a) 1 b) 2 c) 3 d) 0
Answer: b
Explanation: The external interrupts, programmed level-sensitive should remain high for atleast
2 machine cycles.

10. If the external interrupts are programmed edge sensitive, then they should remain high for
atleast
a) 0 machine cycle b) 2 machine cycles c) 1 machine cycle d) 3 machine cycles
Answer: c
Explanation: If the external interrupts are programmed edge sensitive, then they should remain
high for atleast one machine cycle and low for atleast one machine cycle, for being sensed.

11. The timer generates an interrupt, if the count value reaches to

a) 00FFH b) FF00H c) 0FFFH d) FFFFH
Answer: d
Explanation: the timer is an up-counter and generates an interrupt when the count has reached
FFFFH.

12. The external interrupt that has the lowest priority among the following is
a) TF0 b) TF1 c) IE1 d) NONE
Answer: c
Explanation: The order of given interrupts from high to low priority is TF0, IE1 and TF1.

13. Among the five interrupts generated by 8051, the lowest priority is given to the interrupt
a) IE0 b) TF1 c) TF0 d) RI
Answer: d
Explanation: the interrupt, RI=TI (serial port) is given the lowest priority among all the
interrupts.
14. Among the five interrupts generated by 8051, the highest priority is given to the interrupt
a) IE0 b) TF1 c) TF0 d) IE1
Answer: a
Explanation: the interrupt, IE0(External INT0) is given the highest priority among all the
interrupts.
15. All the interrupts are enabled using a special function register called
a) interrupt priority register b) interrupt register
c) interrupt function register d) interrupt enable register
Answer: d
Explanation: All the interrupts are enabled using a special function register called interrupt
enable register (IE) and their priorities are programmed using another special function register
called interrupt priority register(IP).

16. The number of bytes stored on the stack during one operation of PUSH or POP is
a) 1 b) 2 c) 3 d) 4
Answer: a
Explanation: As 8051 stack operations are 8-bit wide i.e. in an operation using PUSH or POP
instruction, one byte of data is stored on a stack or retrieved from the stack. For implementing
16-bit operations, two 8-bit operations are cascaded.

17. The step involved in PUSH operation is

a) increment stack by 2 and store 8-bit content to address pointed to by SP
b) decrement stack by 1 and store 16-bit content to address pointed to by SP
c) increment stack by 1 and store 8-bit content to address pointed to by SP
d) store 8-bit content to address pointed to by SP and then increment stack by 1
Answer: c
Explanation: The PUSH instruction follows two steps.
1. Increment stack by 1
2. Store 8-bit content of the 8-bit address specified in the instruction to the address pointed to by
SP.

18. The step involved in POP operation is

a) decrement stack by 2 and store 8-bit content to address pointed to by SP
b) store 16-bit content to address pointed to by SP and decrement stack by 1
c) decrement stack by 1 and store content of top of stack to address pointed to by SP
d) store content of top of stack to address pointed to by SP and then decrement stack by 1
Answer: d
Explanation: The POP instruction follows two steps.
1. Store the contents of top of stack pointed to by SP register to the 8-bit memory specified in the
instruction.
2. Decrement stack by 1.
19. The 8051 stack is
a) auto-decrement during PUSH operations b) auto-increment during POP operations
c) auto-decrement during POP operations d) auto-increment during PUSH operations
Answer: d
Explanation: The 8051 stack is opposite to that in 8085 or 8086 i.e. in 8085 it is auto-decrement
while in 8051 it is auto-increment during PUSH operations.

20. After reset, the stack pointer(SP) is initialised to the address of

a) internal ROM b) internal RAM c) external ROM d) external RAM
Answer: b
Explanation: The stack pointer(SP) is an 8-bit register and is initialized to internal RAM address
07H after reset.

21. The serial communication is

a) cheaper communication b) requires less number of conductors
c) slow process of communication d) all of the mentioned
Answer: d
Explanation: The serial communication requires less number of conductors and thus it is cheaper.
It is slow as the bits are transmitted one by one along with start, stop and parity bits.

22. The serial communication is used for

a) short distance communication b) long distance communication
c) short and long distance communication d) communication for a certain range of distance
Answer: b
Explanation: Serial communication is more popular for communication over longer distances as
it requires less number of conductors.

23. The mcs 51 architecture supports

a) serial transmission and reception b) simultaneous transmission and reception
c) transmission and reception of data using serial communication interface
d) all of the mentioned
Answer: d
Explanation: The mcs 51 architecture supports simultaneous transmission and reception of
binary data byte by byte i.e. full duplex mode of communication. It supports serial transmission
and reception of data using standard serial communication interface and baud rates.

24. The number of bits transmitted or received per second is defined as

a) transmission rate b) reception rate c) transceiver rate d) baud rate
Answer: d
Explanation: Here, baud rate can be defined as the number of bits transmitted or received per
second.

25. The task of converting the byte into serial form and transmitting it bit by bit along with start,
stop and parity bits is carried out by
a) reception unit b) serial communication unit
c) transmission unit d) all of the mentioned
Answer: c
Explanation: the serial communication unit consists of transmission unit and reception unit. The
task of converting the byte into serial form and transmitting it bit by bit along with start, stop and
parity bits is carried out by transmission unit.

UNIT VIII
1. Is the following instruction correct LDI R3,50?
a) Yes b) No c) Cant be said d) none of the mentioned
Answer: b
Explanation: If LDI Rd,k is written then the range of Rd varies from R16-R31, as R3 is less than
R16 so this instruction will generate an error.

2. Registers R0-R31 are used for what type of works?

a) they are used for arithmetic and logic instructions
b) they are used for data copy
c) they are used for calculations
d) none of the mentioned
Answer: a
Explanation: GPRs are used for implementing arithmetic and logic instructions in the controller.
They do the same work as the accumulator does in the other micro controllers and micro
processors.

3. Largest value that can be loaded in an 8 bit register is?

a) 11111111H b) FH c) FFH d) 00H
Answer: c
Explanation: The largest value that can be loaded in an 8 bit register is 11111111b or FFH.

4. The total space for the data memory available in the AVR based micro controller is?
a) FFH b) FFFH c) FFFFH d) FFFFFH
Answer: c
Explanation: The maximum value that can be loaded in the code memory of an AVR based
micro controller is FFFFH.

5. Which out of the following instructions don’t affect the flags of the status register?
a) AND b) INC c) OR d) ADD
Answer: d
Explanation: ADD command does not affect the flags of the status register. It just adds the
contents of the two registers together.

6. What is the difference between the two given instructions?

LDI R16,0×34 and LDI R16,$34
a) One copies the hexadecimal value to R16 and the other copies the decimal value to the R16
register
b) One is for command, other is for data
c) One is for assignment, other is for operations
d) Both the commands are the same
Answer: d
Explanation: Both the above commands are the same. They both are used for assigning the
hexadecimal values to the registers.

7. Which out of the following is not a directive?

a) .EQU b) .DEVICE c) .ORG d) .LDI
Answer: d
Explanation: .EQU, .DEVICE, .ORG all are the directives to the assembler whereas LDI is a
command.
8. Is an assembly language a high level language?
a) Yes b) No c) Cant be said d) none of the mentioned
Answer: b
Explanation: High Level Languages are the languages that are written in the common english, so
that even a common man can understand it easily like C,C++, whereas assembly language is a
middle level language between the high level and the machine level.

9. A 14 bit program counter can execute a maximum of _________ memory locations?

a) 4K b) 8K c) 16K d) 64K
Answer: c
Explanation: A program counter of an AVR is 14 bit long which means it has 2^14 bytes of
memory or 16K bytes of memory.

10. When AVR wakes up, then the value of PC becomes?

a) 00H b) 000H c) 0000H d) 00000H
Answer: d
Explanation: When an AVR wakes up, then the PC starts at the memory location 00000H.

SUBJECTIVE QUESTIONS
UNIT I
1.a) What is a microprocessor. What are the basic functional blocks of a microprocessor.
Explain.
b) What do you mean by 8-bit and 16-bit processors. Explain the difference between 8085
and 8086.
c) a) Discuss the following interface signals of 8086 in minimum mode.
a) Address/data bus
b) Status signals
 c) Control signals
2.a) What is a machine cycle? Explain the basic 8086 system timing with a neat
timing.
b) What is a flag? Show the bit positions of various flags in 8086 flag register.
c) Explain briefly the architecture of 8086.
3. a) What do you mean by pipelined architecture.
b) Describe the function of 8086 instruction queue. How does the queue speed up
processing.
c) Draw the pin diagram of 8086 processors and describe the function of each.
4. a) Explain the concept of segmented memory. What are its advantages.
b) Discuss the minimum mode control signals of 8086.
c) Explain the write cycle operation of the microprocessor with a neat timing diagram in
maximum mode.

UNIT-II

1. a) Discuss various addressing modes with examples.

b) Explain difference between intra segment and inter segment branching.
c) Explain I/O addressing modes of 8086.
2. a) Explain briefly the addressing modes for control transfer instructions.
b) Explain indirect program memory addressing.
c) What is a procedure? Write the differences between procedure and macro.
3. a) Define Assembler directives?
b) What is the use of DUP directive? Explain with examples.
c) Explain the following assembler directives
a. ENDb.PTR c. SEGMENT d. LABEL
e. ORG
4. a) Explain the following instructions of 8086.
a. LDS/LES b. XCHG c. POP d.DAA
b) Write a program to find the smaller of the two 16-bit numbers.
c) Write a program to multiply two 16-bit numbers and store the answer in memory
location 2000H onwards.
UNIT-III

1. a) Draw the block diagram of 8255 and explain each block.

b) Draw the three modes of operations
c) What is BSR mode of operation. How is it useful in controlling the interrupt initiated data
transfer for mode1 and mode2.
2. a) Interface 16-bit 8255 with 8086 .The address of portA is F0H.
b) Write BSR control word to set bit3 of portC and alsowrite control word to reset bit 3 of
port C.Introduce 1msec delay between set and reset of bit 3 of portC.
 c) Explain the control word format of 8255 in I/O and BSR mode.
3. a) Interface of 4X4 keyboard with 8086 using 8255 and write an ALP for detecting the key
closure and return key code in AL.The debouncing period for a key is 10ms.Use software
key debouncing technique. DEBOUNCE is an available 1ms delay routine.
b) Draw the circuit diagram to interface DAC to the micro controller.
c) Write the pin diagram of DAC 0800.
4. a) Explain the construction of stepper motor in brief.
b) Write short notes on EEPROMs.
c) Explain the static ram interfacing.

UNIT-IV
1.a) What is the difference between 8259 and 8259A.
b) Explain the architecture of 8259PIC with a neat block diagram.
c) Explain the pin diagram of 8259 PIC.
2. a) Explain interrupt structure of 8259.
b) List out the advantages of using 8259.
c) What is the Vector Table? Draw and explain the interrupt vector table of 8086.
3. a) Explain the cascaded mode operation of 8259 with a neat block diagram.
b) Write about the operational command word of 8259.
c) Explain the functions of following signals of 8257.
a. HLDA b.AEN c.MARK d.MEMR
4.a) Explain the interfacing of 8257 with 8086.
b) Draw the interface circuits for data conversion from TTL to RS232C and RS232C to
TTL.
c) Explain indetail about prototyping and troubleshooting method.

UNIT-V
1. a) List out the serial communication standards with examples
b) Distinguish b/w Asynchronous and Synchronous data transfer schemes
c) Explain the interfacing of 8251 with 8086

2. a) List out the specifications of RS 232

b) Write a short note on trouble shooting
c) Discuss the prototyping using In-circuit Emulator

3. a) Explain with neat diagram the working of 8251 USART

 b) Write short notes on IEEE488 standard
c) What do you mean by trouble shooting? How it is done

4. a) Draw the formats of Synchronous and Asynchronous communication

b) Explain 3 errors that occur in asynchronous serial transmission
c) Draw the interface circuits of TTL-RS 232 and RS232-TTL

UNIT-VI
1. a) List out the features of 8051Microcontroller
b) Draw and explain the architecture of 8051
c) Describe the input/output configuration of 8051Microcontroller

2. a) Give the memory organization of 8051Microcontroller

b) List out the addressing modes supported by 8051Microcontroller
c) Explain how 8051 differentiates external and internal program memory

3 a) Explain the basic differences between a microprocessor and a microcontroller

b) Write an 8051 program to find where Y=x2+5 and x is between 0 to 5
c) Give the functions of following signals
1. ALE 2. PSEN 3. INT0/INT1 4. EA 5. RXD/TXD

4. a) Explain the working of 8051 oscillator and clock

b) Discuss the advantages of Microcontrollers over Microprocessors
c) What is the purpose of SP in 8051? Explain its operation with an example

UNIT-VII
1. a) How many timers 8051 has?
b) Explain the format of TMOD register.
c) What are the characteristics and various steps involved in the mode 1 for Timer 0.
2. a) Indicate which mode and which timer have been selected for each of the
following i) MOV TMOD, # 01 H ii) MOV TMOD, #12 H.
b) Draw a flow chart for the key board interfacing with 8051.
c) Explain the interfacing of ADC0804 with 8051.
3. a) Explain the interrupt structure of 8051 microcontroller Explain how interrupts are
prioritized.
b) Explain how an 8051 microcontroller can be interfaced with external ROM
 c) List the timer features that are programmable.
4. a) List the timer features that are programmaeble in a timer as a free-running
counter.
b) Explain the format of SCON register
c) Explain the format of IE & IP registers

UNIT-VIII
1. a) Draw and Explain the standard AVR architecture
b) Explain about register organization in AVR controller
c) What are the various steps in SRAM interfacing? Interface two 8K X8 RAM
chips, two 8K X8 ROM with 8086. The starting address of the mapping must be
FFFF H.
2.a) Explain the salient features of AVR RISC Controller with reference to its architecture
b) Discuss the interrupt of RISC controller
c) Interface Program memory of 16K X 8 EPROM to 8051 and give its memory
map. The address of memory map should start from 0000H.
3.a) Explain UART of AVR
b) Explain memory organization in AVR
c) Explain the instruction formats of AVR controller

4. a) Draw the memory map of the AVR controller when operated in the various modes.
b)Explain timer operation in AVR with neat circuit diagram
c) Explain about I/O memory and I/O port interfacing.