Ramesh Maddara

ramesh.babu.maddara@gmail.com

ICs History and Current Trends

1. Who invented the First IC?

Jack Kilby of Texas Instruments invented the first integrated
circuit (IC) in 1958. He demonstrated the concept by integrating
multiple components onto a single piece of semiconductor
material. This invention marked the beginning of modern
electronics.
Later, Robert Noyce of Fairchild Semiconductor improved the
design by introducing the planar process, which made ICs more
practical and scalable. Both Kilby and Noyce are credited with
pioneering the integrated circuit.

2. How did the JK flip-flop get its name?

The JK Flip-Flop is named after Jack Kilby, the electrical engineer
who invented the integrated circuit. Kilby designed this versatile
flip-flop during his tenure at Texas Instruments in the 1950s. It is a
modification of the SR flip-flop, eliminating the indeterminate
state and adding toggling functionality.

3. Who is the father of IC?

The title of "Father of the Integrated Circuit (IC)" is often
attributed to Jack Kilby, who invented the first working integrated
circuit at Texas Instruments in 1958. His groundbreaking work
earned him the Nobel Prize in Physics in 2000.

However, Robert Noyce also played a crucial role in the

development of the IC. He independently created a monolithic
 Ramesh Maddara
ramesh.babu.maddara@gmail.com

integrated circuit at Fairchild Semiconductor in 1959, using the

planar process, which made ICs more practical and scalable.

Both Kilby and Noyce are celebrated as pioneers of the integrated

circuit.

4. What do you know about 8085 µP?

The 8085 was designed for general-purpose computing and was
essential to the development of early computers. It was built on
NMOS technology. It was designed by Intel in 1976 and it was
discontinued in the year 2000.

Here are some of the key features of the 8085 microprocessor:

Architecture: The 8085 is a single-chip, 8-bit CPU with a 16-bit

address bus. It can address up to 64 KB of memory.

Power supply: The 8085 uses a +5 V power supply.

Package type: 40-pin DIP package.

Technology node: 3µm NMOS Technology.

No. of Transistors: Approximately 6500 transistors were used.

No. of logic gates: Approximately 2500 gates estimated in terms

of basic NOT gate.

Clock speed: The first commercial version of the 8085 µP runs at

a maximum frequency of 3 MHz, and later versions run at 5 MHz
and 6 MHz.

ALU: The 8085 has an 8-bit Arithmetic Logic Unit (ALU) that can
perform basic arithmetic and logic operations.

Registers: The 8085 has programmable, control and status

registers, and an instruction decoder.
 Ramesh Maddara
ramesh.babu.maddara@gmail.com

Addressing modes: The 8085 has direct and indirect addressing

modes. It is a way of specifying the data for an instruction, called
addressing modes.

Interrupts:

 Maskable interrupts: The 8085 interrupts RST7.5 (edge

trigger), RST6.5, and RST5.5 are maskable by SIM instruction.
But, the interrupt INTR is disabled by DI instruction.
 Unmaskable: The 8085 has only one un-maskable interrupt
called TRAP.
 Vectored interrupts: There are four hardware interrupts, TRAP,
RST5.5, RST6.5, and RST7.5 are vectored interrupts. And there
are eight software interrupts, RST0, RST1, RST2, RST3, RST4,
RST5, RST6, and RST7 are also vectored interrupts.
 Non-vectored interrupts: INTR is the only non-vectored
interrupt because it doesn't have a fixed address. The
interrupt handler provides the address of the interrupt service
routine (ISR) of the external device and is sent over the data
bus on receipt of interrupt acknowledgment (INTA).
 All interrupts except TRAP are enabled by the EI instruction
and disabled by the DI instruction.

Serial Ports: The 8085 has two serial data ports (SID and SOD)
which are controlled by software.
 Ramesh Maddara
ramesh.babu.maddara@gmail.com

5. What could be the average propagation delay of the gates

used in the Intel 8085 microprocessor?

The Intel 8085 microprocessor is a vintage microprocessor

introduced in the late 1970s. Gate technology has evolved
significantly since then, and modern microprocessors use much
smaller and faster gates in advanced semiconductor technology
nodes.

In the Intel 8085, which was based on older NMOS (N-channel

Metal-Oxide-Semiconductor) technology, the gate delays were
relatively longer compared to contemporary microprocessors. The
propagation delay of gates in the 8085 microprocessor could be
in the range of tens of nanoseconds (ns). Let's make an estimation
based on the available data we have.

The clock frequency of the 8085 microprocessor is 3MHz and the

1
period of the clock is us or 0.333us or 333ns.
3
Assuming approximately 20 levels of gates between the two FFs
for timing critical paths (setup time is assumed one gate delay).
Then the approximate average propagation delay of the gate is
333
tpd = ns ≈ 16ns
20

So, we can guess the gate delays may be in the range of 10 to 30

nanoseconds. The average propagation delay of the gate is
around 20 ns.

Note: Keep in mind that this is a rough estimate, and the actual
propagation delays for different gates within the Intel 8085
microprocessor would vary.
 Ramesh Maddara
ramesh.babu.maddara@gmail.com

6. What could be the average propagation delay of the gates

used in the modern digital design, say 3nm technology
node?
In modern digital designs, such as those using the 3nm technology
node, the average propagation delay of logic gates is extremely
small due to the advanced scaling of transistors. Typically, the
propagation delay for gates in such advanced nodes can range
from a few picoseconds (ps) to tens of picoseconds, depending on
factors like:

Gate Type: Simple gates, like inverters, have lower delays

compared to complex gates like NAND or XOR.

Load Capacitance: Higher load capacitance increases delay.

Operating Voltage: Lower supply voltages in modern nodes can

slightly increase delay.

Process Variations: Variations in manufacturing can affect the

delay.

For example, in a 3nm node, an inverter might have a propagation

delay in the range of 5-20 ps, depending on the specific design
and operating conditions. And the average delay of the inverter
gate can be around 10ps.

7. How are gate delays estimated or modelled in VLSI?

A gate delay (or propagation delay) is modelled by the following
equation.

tpd = R C

Where:

R = effective resistance of the gate

C = sum of gate loads and interconnect capacitance

 Ramesh Maddara
ramesh.babu.maddara@gmail.com

8. Explain the Evolution of x86 family of Intel

microprocessors.
What is x86?

The term x86 refers to a family of instruction set architectures

(ISAs) based on the original Intel 8086 microprocessor, introduced
in 1978. Over time, the x86 architecture has evolved through
multiple generations, adding performance, complexity, and
capabilities — while maintaining backward compatibility.

Evolution of Intel x86 Microprocessors

i. 8086 and 8088 (1978–1979):

 8086: First 16-bit processor, 20-bit address bus → could

address 1MB of memory
 8088: Same internal architecture but with an 8-bit external
bus (used in IBM PC)

The birth of the x86 architecture.

ii. 80186 (1982)

 The Intel 80186, introduced in 1982, is an enhanced version

of the 8086 microprocessor.
 It was primarily designed for embedded systems rather than
personal computers.

iii. 80286 (1982)

 Introduced protected mode (enabled multitasking, memory

protection)
 Still supported real mode for backward compatibility
 Used in IBM PC/AT
 Ramesh Maddara
ramesh.babu.maddara@gmail.com

iv. 80386 (1985)

 First 32-bit x86 processor

 Introduced virtual memory, paging, and hardware-level
multitasking
 Enabled advanced OS features (e.g., Windows NT, UNIX
variants)

v. 80486 (1989)

 Integrated floating-point unit (FPU) on-chip

 Introduced instruction pipelining → improved performance
 Started to resemble a modern CPU

vi. Pentium Series (1993–2000s)

 Pentium (P5): Superscalar architecture (dual pipelines)

 Pentium Pro (P6): Out-of-order execution, branch prediction
 Pentium II/III: MMX, SSE instructions; improved cache and
packaging

vii. Pentium 4 (NetBurst, 2000)

 Very high clock speeds (up to 3.8 GHz)

 Long instruction pipeline → performance didn’t scale well
 Eventually hit a power/heat wall

viii. Core Architecture (2006–Present)

 Core Duo → Core 2 Duo → Core i3/i5/i7/i9

 Shift from clock speed to performance-per-watt
 Multi-core CPUs became standard
 Introduction of Hyper-Threading, Turbo Boost, and deep
power management.
 Ramesh Maddara
ramesh.babu.maddara@gmail.com

9. What is the thermal design power (TDP) of Intel Core

i3/i5/i7 processors?
The Thermal Design Power (TDP), which represents the maximum
amount of heat a processor generates under typical workloads,
varies across Intel's i3, i5, and i7 processors depending on the
specific model and generation. Here are some general ranges:

i. Intel Core i3:

- TDP typically ranges from 15W to 35W for modern i3

processors, designed for entry-level performance and energy
efficiency.

ii. Intel Core i5:

- TDP ranges from 15W to 65W, depending on whether the

processor is for laptops (lower TDP) or desktops (higher TDP).

iii. Intel Core i7:

- TDP ranges from 15W to 125W, with high-performance

models consuming more power due to additional cores and
higher clock speeds.

These values can vary significantly based on the processor's

generation, architecture, and intended use.
 Ramesh Maddara
ramesh.babu.maddara@gmail.com

10. What is the thermal design power (TDP) of Intel Xeon

server processor chips?
The Thermal Design Power (TDP) of Intel Xeon server processors
varies significantly across different generations and models,
reflecting their intended use cases and performance capabilities.
Here's an overview:

TDP Range: Approximately 125W to 385W.

Examples:
Xeon Platinum 8593Q: 64 cores, 3.9 GHz max turbo, 2.2 GHz base, 320 MB cache, 385W TDP.
Xeon Gold 6558Q: 32 cores, 4.1 GHz max turbo, 3.2 GHz base, 60 MB cache, 350W TDP.
Xeon Silver 4510: 12 cores, 4.1 GHz max turbo, 2.4 GHz base, 30 MB cache, 150W TDP.
Xeon Bronze 3508U: 8 cores, 2.2 GHz base, 22.5 MB cache, 125W TDP.

11. What is the thermal design power (TDP) of the Snapdragon

chip?
The Thermal Design Power (TDP) of Qualcomm Snapdragon chips
varies across different models and configurations. Here's a TDP
overview of Snapdragon mobile chips.

In mobile SoCs (System on Chips), TDP is not always officially

published by Qualcomm, but we can estimate based on power
envelopes and measured power consumption under typical loads.

The general Range for Mobile Snapdragon SoCs:

TDP typically ranges from 3W to 6W for flagship smartphone
chips.

Lower-tier and midrange chips might stay under 2W to 4W under

sustained use.
 Ramesh Maddara
ramesh.babu.maddara@gmail.com

12. What are the current trends in VLSI?

The Very Large Scale Integration (VLSI) is evolving rapidly, driven
by advancements in technology and the growing demand for
high-performance, energy-efficient systems. Here are some of the
current trends shaping the VLSI industry:

i. AI-Driven VLSI Design:

 Artificial Intelligence is being integrated into VLSI design

processes to optimize chip architectures and streamline
workflows.

ii. 3D ICs and Advanced Packaging:

 The adoption of 3D Integrated Circuits (ICs), which stack chips

vertically, is revolutionizing VLSI by enabling higher transistor
densities and improved performance.

iii. Chiplets:

 Modular chip designs, known as chiplets, are gaining

popularity for their scalability and cost-effectiveness.

iv. Neuromorphic Computing:

 VLSI is exploring neuromorphic architectures, which mimic

the human brain, for applications in AI and machine
learning.

v. Power Optimization:

 Techniques to reduce power consumption are becoming

critical, especially for IoT and mobile devices.
 Ramesh Maddara
ramesh.babu.maddara@gmail.com

vi. Security-First Design:

 With increasing cybersecurity concerns, VLSI designs are

incorporating robust security features.

vii. Advanced Manufacturing Technologies:

 Smaller nodes like 3nm and 2nm are pushing the boundaries
of transistor scaling.

These trends highlight the dynamic nature of VLSI and its

pivotal role in shaping the future of electronics.

13. What are the key emerging areas for design verification
engineers?
Key Emerging Areas for Design Verification Engineers.

i. Formal Verification & Property Checking

 Shift-left approach: catch bugs earlier, during RTL

development.
 Tools: JasperGold (Cadence), VC Formal (Synopsys)
 Skills: SystemVerilog Assertions (SVA), PSL, formal property
writing

High impact in safety-critical systems (automotive, medical,

aerospace)

ii. Verification for AI/ML and Accelerators

 Neural Processing Units (NPUs), Tensor cores, and custom ML

accelerators
 Need for verifying dataflow architectures, precision handling
(e.g., FP16, INT8), and scheduling logic

Knowledge of AI/ML architectures + data movement patterns is

a big plus.
 Ramesh Maddara
ramesh.babu.maddara@gmail.com

iii. Cloud-Based and Distributed Verification

 Shift from on-prem tools to cloud infrastructure (AWS, Azure)

 Enables massive regression capacity, parallel test runs

Instead of running simulations and regressions on local servers

or workstations, verification tasks (like compiling, running
testbenches, regressions, or formal analysis) are offloaded to
cloud infrastructure, such as AWS, Azure, or private datacenters
- often using distributed job execution across hundreds or
thousands of cores.

iv. Intelligent Verification using ML

Using machine learning for:

 Coverage analysis
 Test generation
 Bug triage
 Tools are starting to include ML-based optimizations

Growing area with high potential for automation

V. Portable Stimulus Standard (PSS)

 One test → multiple platforms (block-level, SoC-level, post-

silicon)
 Supports scenario-based verification, reusability

Learning PSS from Accellera + tools like Breker can be a

competitive edge.

vi. SoC-Level Verification & Emulation

 Includes UVM testbenches, performance models, protocol

checking
 Use of emulators (e.g., Synopsys ZeBu, Cadence Palladium)
and FPGA prototyping

Helps to bridge pre-silicon and post-silicon debug

 Ramesh Maddara
ramesh.babu.maddara@gmail.com

vii. Hardware-Software Co-Verification

 Testing the RTL along with embedded firmware or drivers

 Required in chips where hardware and software are tightly
integrated (e.g., RISC-V SoCs, automotive MCUs)

Skills in C, embedded systems, and co-simulation frameworks

like Veloce, Synopsys HAPS.

viii. Security & Trust Verification

 Verifying secure boot, crypto hardware, and side-channel

protections
 Focused on hardware Trojans, timing leaks, and IP-level
security
Knowledge of hardware security primitives (AES, SHA, TRNGs) is
in demand

ix. Low-Power Design and Power-Aware Verification

 Verification of power intent using UPF (Unified Power

Format)
 Required for chips with multiple power domains, DVFS, or
aggressive power gating

Tools: Synopsys VC LP, Cadence CPF/UPF tools

x. Verification of High-Speed Protocols

 PCIe Gen5/6, DDR5/6, CXL, USB4, Ethernet 800G

 Complex PHY and controller logic require deep protocol
knowledge

Verification engineers with protocol expertise are highly

sought-after.

================= THE END ================