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Industrial standards projects
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Indicus Technology
E-1203/1209, Titanium City Center, Near Sachin Tower,
100ftAnandnagar Road, Satellite, Ahmedabad.
M: +91 97256 32717, O: 079 40027955 ,
E : info@indicustechnology.com,
W : www.indicustechnology.com
MODULE 1 MODULE 2 MODULE 7 MODULE 8
Introduction to VLSI Digital Electronics System Verilog System Verilog Assertions
* what is VLSI ? * Digital number system * Introduction
* Introduction
* Introduction * System Verilog Data types
* Logic Gates * Immediate assertion
* Arrays In SV
* VLSI Design Flow * Logic Minimization * Simple assertion
* Task & Function In SV
* Scope * Combinational Circuit * Sequence composition
* Interface
* Opportunities * Sequential Circuit * ABV
* OOPS & Advance OOPs Concept
* Finite State Machine * Randomization & macros * Assertion Coverage
* Memories * Threads, Mailbox, Semaphore, Events
* System Verilog TB Environment
* Function Coverage
MODULE 3 MODULE 4 MODULE 9 MODULE 10
UNIX Basic Verilog HDL UVM Methodology Python Scripts
* Introduction * Introduction * Introduction
* Introduction
* Verilog Data Types & Operators * UVM Factory * Variable Types
* Handling directory Operation from
* Verilog Assignment & construct * UVM phases * Operators
Command Prompt
* Verilog System Task * UVM Reporting Mechanism * number, string and list
* Handling files Operation from
* Combinational & Sequential design * TLM & configuration * If else and loops
Command Prompt
* UVM Sequence * tuple and dictionary
* Handling File Editor Application (vi, * Synchronous & Asynchronous design
* UVM TB Environments & Callbacks * Function
vim , gvim) * Task & Function
* UVM hack and tricks, report server * File I/O Operation
* Self Checking TB
* UVM events, barrier and heartbeats
* Code Coverage
MODULE 5 MODULE 6 MODULE 11 MODULE 12
FPGA, ASIC, SOC STA Basic Mini Projects Industrial Standard
* Introduction * Introduction * Verilog based mini project Project
* What is FPGA ? * Delay calculation * System Verilog based mini project * Specification
* What is ASIC ? * Circuit maximum Operating frequency * UVM based mini project * Design Architecture
* What is SOC ? calculation * RTL Design using verilog HDL
* Comparison Between FPGA, ASIC, * Skew and jitter * RTL Verification using system
SOC * clock domain and variation verilog/UVM
* Clock Network Distribution * AXI4/ AXI3/ AHB/ APB/ ASB/ Bridge
* SPI/ I2C/ UART
* And many more......
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