CAPACITOR

By Bargunan Ponnusamy
CAPACITOR

- Bargunan Ponnusamy
 CAPACITOR
A capacitor is a passive electronic component that stores and releases
electrical energy in the form of an electric field. It plays a crucial role in
managing voltage, smoothing signals, filtering noise, and stabilizing
power in circuits.

Purpose of Capacitor
Capacitors are versatile and are used for various functions, such as:

How it works?
A capacitor stores energy between two conductive plates separated by
an insulating material called the dielectric. When a voltage is applied
across the plates, an electric field builds up and charge accumulates.

The key relationship is: Q=C×V

Capacitors oppose changes in voltage—a property that makes them

ideal for filtering and stabilization.

- Bargunan Ponnusamy
TYPES OF CAPACITORS / TECHNOLOGIES

Type Characteristics Use Case

Decoupling, general
Ceramic Capacitor Small, cheap, low ESR
use

High capacitance,
Electrolytic Capacitor Power filtering
polarized

Stable, compact, Space-constrained,

Tantalum Capacitor
polarized low-ESR needs

Film Capacitor High precision, reliable Audio, high-frequency

Backup power, energy

Supercapacitor Very high capacitance
storage

Key Specifications
1. Capacitance (in Farads): Indicates how much charge it can store.
Common values: pF, nF, μF
2. Voltage Rating (V): Maximum voltage it can handle. Always choose at
least 1.5× the operating voltage.
3. Type & Dielectric: Choose based on frequency response, stability, and
tolerance needs.
4. Tolerance: Indicates variation from the nominal value (e.g., ±10%,
±20%).
5. ESR (Equivalent Series Resistance): Important in power applications
and high-speed switching circuits.

- Bargunan Ponnusamy
HOW TO CHOOSE A CAPACITOR?

- Bargunan Ponnusamy
 HOW TO CHOOSE A CAPACITOR?
1. Define the Application Purpose:
Is the capacitor used for decoupling, filtering, energy storage, timing,
coupling, or noise suppression?

2. Determine Capacitance Value

Common Calculations:
For Decoupling: Use standard 0.01µF to 0.1µF near IC power pins.
For Power Filtering:

For Timing (RC Circuits):

For AC Coupling:

Pro Tip: Always select higher capacitance than minimum to allow for
tolerances and derating.

3. Select Voltage Rating

Choose a voltage rating at least 2× your operating voltage for safety
margin.
For ceramic capacitors, account for DC bias derating (effective
capacitance drops at higher applied voltages).

4. Choose Dielectric Type

Choose a voltage rating at least 2× your operating voltage for safety
margin.
For ceramic capacitors, account for DC bias derating (effective
capacitance drops at higher applied voltages).
NP0 (C0G) | X7R | Y5V/Z5U | Electrolytic | Tantalum | Film

- Bargunan Ponnusamy
 HOW TO CHOOSE A CAPACITOR?
5. Check ESR and Ripple Current
Low ESR is essential for switching regulators.
Check manufacturer’s ripple current rating to avoid overheating.
For Power Circuits: Use ceramic or low-ESR electrolytic capacitors to
minimize ripple voltage.

6. Consider Physical Size and Mounting

Low ESR is essential for switching regulators.
Check manufacturer’s ripple current rating to avoid overheating.
For Power Circuits: Use ceramic or low-ESR electrolytic capacitors to
minimize ripple voltage.

Package Type Use Case

SMD (MLCC) Compact, automated assembly

Through-Hole
High current, mechanical stability

Supercapacitor
Large energy storage, low-voltage

7. Consider Temperature and Aging

Check the temperature rating (usually -40°C to +125°C).
Class II/III ceramics (X7R, Y5V) age over time (~1% per decade).
Use NP0/ C0G for stability-critical circuits.

8. Check Frequency Behavior

Self-Resonant Frequency (SRF): Above SRF, capacitor behaves
inductively.
For high-speed circuits (MHz+), use multiple parallel capacitors (0.1µF,
1µF, 10µF) to cover wide frequency ranges.

- Bargunan Ponnusamy
 CERAMIC CAPACITORS
CLASS-I CERAMICS:

Type Material Voltage Range Capacitance Temperature Tolerance

Range Coefficient

C0G/NP0 Titanium Dioxide 16V – 3kV 1pF – 47nF ±30 ppm/°C ±1% to ±5%

U2J Neodymium Titanate 16V – 500V 1.5pF – 1nF ±120 ppm/°C ±5%

P3K Mixed Titanates 25V – 500V 2.2pF – 560pF ±250 ppm/°C ±10%

C0G/NP0 Characteristics:
Linear capacitance vs voltage
Stable across temperature
Excellent for timing circuits
High Q factor (>1000)

Applications:
Oscillator circuits
Filter networks
Sample and hold circuits
RF coupling/bypass

- Bargunan Ponnusamy
 CERAMIC CAPACITORS
CLASS-II CERAMICS:

Type Material Voltage Capacitance Temperature DC Bias Effect

X7R Barium 6.3V – 2kV 100pF – 100μF ±15% (-55°C to +125°C) -15% to -56%

X5R BaTiO₃ 4V – 50V 100pF – 47μF ±15% (-55°C to +85°C) -10% to -40%

Y5V High-K 6.3V – 50V 1nF – 10μF +22/-82% (-30°C to +85°C) -20% to -80%
Material

X7R Performance:
Capacitance loss at rated voltage: 15-35%
Aging rate: 2.5%/time decade
Dissipation factor: 2.5% max
Insulation resistance: >10GΩ or 100GΩ-μF

Voltage Coefficient:
0805 10μF 6.3V: -56% at rated voltage
0603 1μF 16V: -35% at rated voltage
1206 22μF 6.3V: -65% at rated voltage

- Bargunan Ponnusamy
 ELECTROLYTIC CAPACITORS
Aluminum Electrolytic

Series Electrolyte Voltage Capacitance ESR @ 100kHz Ripple Current

Standard Liquid 6.3V – 450V 1μF – 47mF 0.01 – 10Ω 0.1 – 5A

Low ESR Liquid 6.3V – 100V 10μF – 10mF 0.003 – 0.5Ω 1 – 10A

Polymer Solid 2.5V – 35V 2.2μF – 1.5mF 0.003 – 0.1Ω 2 – 15A

Aluminum Construction:
Anode: Etched aluminum foil
Dielectric: Aluminum oxide (Al2O3)
Cathode: Electrolyte + aluminum foil
Separator: Paper spacer

Performance Characteristics:
Capacitance tolerance: ±20% standard
Leakage current: 0.01CV or 3μA (whichever greater)
Operating temperature: -40°C to +105°C
Life expectancy: 2000-10000 hours @ 85°C

Failure Mechanisms:
Electrolyte evaporation (main failure mode)
Seal degradation
Corrosion of terminals
Oxide layer breakdown

- Bargunan Ponnusamy
 ELECTROLYTIC CAPACITORS
Tantalum Electrolytic

Type Construction Voltage Capacitance ESR @ 100kHz Failure Rate

0.1 – 1% per 1000

Solid MnO₂ Sintered 2.5V – 50V 0.1μF – 1mF 0.01 – 1Ω
hours

0.01 – 0.1% per

Polymer Sintered 2.5V – 35V 1μF – 1.5mF 0.005 – 0.5Ω
1000 hours

0.001% per 1000

Wet Slug Foil 6V – 125V 1μF – 22mF 0.1 – 50Ω
hours

Tantalum Advantages:
Stable capacitance vs temperature
Low leakage current
High capacitance density
No electrolyte evaporation (solid)

Tantalum Disadvantages:
Sensitivity to voltage transients
Higher cost than aluminum
Potential for ignition failure
Limited voltage range

- Bargunan Ponnusamy
 FILM CAPACITORS
PolyPropylene (PP)

Parameter Value Units Notes

Dielectric Constant 22 - Measured at 1kHz, 20°C

Loss Factor 2 - Measured at 1kHz, 20°C

Breakdown Voltage 650 V/μm DC

Temperature Coefficient -200 ppm/°C Negative coefficient

Moisture Absorption <0.02 % ASTM D570 Standard

PP Applications:
Snubber circuits
High-frequency switching
Audio crossovers

Polyester (PET)

Parameter Value Units Notes

Dielectric Constant 33 - Measured at 1kHz, 20°C

Loss Factor 5 - Measured at 1kHz, 20°C

Breakdown Voltage 580 V/μm DC

Temperature Coefficient 400 ppm/°C Positive coefficient

Moisture Absorption 4 % ASTM D570 Standard

PET Characteristics:
Higher dielectric constant than PP
Better temperature stability than
ceramic Class II
Good mechanical properties
Cost effective for general purpose

- Bargunan Ponnusamy
 SMD PACKAGES
CERAMIC SMD PACKAGES

Dimensions
Package Voltage Capacitance Power Rating
(L×W×H)
1005 0.4 × 0.2 × 0.2 mm 4V 100nF 1/32W

201 0.6 × 0.3 × 0.3 mm 25V 220nF 1/20W

402 1.0 × 0.5 × 0.5 mm 50V 1μF 1/16W

603 1.6 × 0.8 × 0.8 mm 100V 10μF 1/10W

805 2.0 × 1.25 × 1.25 mm 200V 47μF 1/8W

1206 3.2 × 1.6 × 1.6 mm 500V 100μF 1/4W

1210 3.2 × 2.5 × 2.5 mm 500V 220μF 1/2W

Package Selection Criteria:

Voltage rating vs dielectric thickness
Capacitance achievable vs volume
ESL vs package size (smaller = lower ESL)
Mechanical stress vs size
Cost vs performance requirements

ELECTROLYTIC SMD

(D × H)
Package Voltage Capacitance ESR (Min)
[mm]

Size A 3.2 × 1.6 50V 10μF 4Ω

Size B 3.2 × 2.8 50V 22μF 2Ω

Size C 6.3 × 5.8 50V 470μF 0.3Ω

Size D 7.7 × 4.3 35V 1000μF 0.15Ω

- Bargunan Ponnusamy
 THROUGH-HOLE PACKAGES
RADIAL LEAD SPACING

Lead Spacing Capacitance Voltage Applications

2.5mm 1pF – 100nF 50V – 1kV Signal Coupling

5.0mm 100nF – 10μF 16V – 450V Power Filtering

7.5mm 1μF – 100μF 16V – 400V Bulk Storage

10.0mm 10μF – 47mF 16V – 450V Power Supplies

Axial Vs. Radial Packages

Axial Advantages:
Lower inductance
Better for high frequency
Easier automated insertion
Better heat dissipation

Radial Advantages:
Higher capacitance density
Lower board area
Standard footprints
Cost effective

- Bargunan Ponnusamy
 PACKAGE-SPECIFIC DERATING
Temperature Derating by Package

Package Size Thermal Power Power Derating Factor

Resistance Rating

402 300°C/W 0.063W 1.6 mW/°C

603 200°C/W 0.1W 2.0 mW/°C

805 160°C/W 0.125W 2.5 mW/°C

1206 120°C/W 0.25W 4.2 mW/°C

Voltage Derating Guidelines

Ceramic Capacitors:
Class I (C0G): No derating required
Class II (X7R): 50% derating recommended
Class II (Y5V): 75% derating recommended

Electrolytic Capacitors:
Aluminum: 80% voltage derating
Tantalum: 50% voltage derating
Polymer: 90% voltage derating

- Bargunan Ponnusamy
 DECOUPLING APPLICATIONS
Power Supply Decoupling Strategy

Function Capacitor Range Placement ESR

Bulk Aluminum Electrolytic 100 – 1000μF PSU Output < 0.1Ω

Intermediate Ceramic X7R 1 – 47μF Per IC Group <0.01Ω

Local Ceramic C0G/X7R 10 – 100nF Per Pin <0.001Ω

Ceramic Capacitors:
Multiple capacitor values for frequency
coverage
10:1 to 100:1 ratio between adjacent values
Minimum three capacitor network
recommended
Consider impedance vs frequency response

Digital IC Decoupling

Microprocessor Decoupling:
Core supply: 10μF + 100nF per supply pin
I/O supply: 1μF + 10nF per supply pin
PLL supply: 1μF + 100nF + 10nF
Analog supply: 10μF + 1μF + 100nF + 10nF

FPGA Decoupling Network:

VCC: 470μF bulk + 10μF per bank + 100nF per pin
VCCINT: 220μF bulk + 47μF intermediate + 100nF local
VCCIO: 100μF bulk + 10μF per bank + 100nF per pin
VCCAUX: 47μF bulk + 1μF + 100nF + 10nF

- Bargunan Ponnusamy
 FILTERING APPLICATIONS
RC Low-Pass Filters

Cutoff Frequency R Value C Value Application

1 Hz 1.6 MΩ 100 nF DC Measurement

10 Hz 160 kΩ 100 nF Sensor Filtering

100 Hz 16 kΩ 100 nF Audio Filtering

1 kHz 1.6 kΩ 100 nF Anti-Aliasing

10 kHz 160 Ω 100 nF Switching Noise

Filter Design Considerations:

Source impedance affects frequency response
Capacitor tolerance impacts cutoff accuracy
Temperature coefficient affects stability
Leakage current creates DC offset

LC Filters

Pi-Filter Configuration:
Input capacitor: 10-100μF electrolytic
Inductor: 10-100μH ferrite core
Output capacitor: 10-100μF electrolytic
Ripple attenuation: 40-60dB

T-Filter Configuration:
Series inductors: L1 = L2 = L/2
Shunt capacitor: C
Better common-mode rejection
Higher component count

- Bargunan Ponnusamy
 COUPLING & BLOCKING APPLICATIONS
AC Coupling
Audio Coupling:
Frequency response: 20Hz-20kHz
Coupling capacitor: 1-10μF film
Input impedance consideration
DC blocking requirement

RF Coupling:
Frequency range: 1MHz-6GHz
Coupling capacitor: 1-100nF ceramic
Low ESL requirement
Temperature stability

DC Blocking

Application Frequency Capacitor Type Capacitance

Audio Amplifier 20 Hz – 20 kHz Film / Electrolytic 1 – 47 μF

RF Amplifier 1 MHz – 1 GHz Ceramic C0G 1 – 100 nF

Video Amplifier DC – 10 MHz Ceramic X7R 100 nF – 1 μF

Digital Logic 1 kHz – 100 MHz Ceramic X7R 10 – 100 nF

- Bargunan Ponnusamy
 ENERGY STORAGE APPLICATIONS
Flash Photography
Requirements:
Energy: 1-10 Joules
Voltage: 300-400V
Discharge time: 1-10ms
Capacitor type: Film or electrolytic

Calculation Example:
Energy = ½CV²
For 5J at 350V: C = 2E/(V²) = 81μF
Film capacitor preferred for low ESR

Backup Power

Requirements:
Hold-up time: 10ms-10s
Voltage droop: <10%
Capacitor type: Supercapacitor or electrolytic

Design Considerations:
ESR limits discharge current
Leakage current affects hold-up time
Temperature affects capacitance
Voltage rating must exceed peak voltage

- Bargunan Ponnusamy
 CERAMIC CAPACITOR FAILURE
MECHANICAL STRESS FAILURES
Flex Cracking:
Cause: PCB flexing during handling/operation
Failure mode: Hairline cracks in ceramic
Prevention: Proper PCB design, keep-out zones
Detection: Insulation resistance measurement

Thermal Shock Failures:

Temperature cycling: -55°C to +125°C
Coefficient of expansion mismatch
Solder joint stress
Package size dependency

Prevention Methods:
Flexible terminations
Smaller package size
Proper PCB thickness
Controlled heating profiles

ELECTRICAL OVERSTRESS

Voltage Breakdown:
Mechanism: Dielectric breakdown
Typical voltage: 2-3× rated voltage
Failure mode: Short circuit
Recovery: Usually not recoverable

Surge Current Damage:

Mechanism: I²R heating of terminations
Critical current: >1A for 0603 package
Failure mode: Open circuit
Prevention: Current limiting

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 FILM CAPACITOR FAILURE
METALLIZATION MIGRATION
Self-Healing Mechanism:
Localized breakdown creates arc
Metal evaporates around fault
Capacitance loss: <1% per event
Cumulative effect over time

Degradation Factors:
Applied voltage stress
Temperature elevation
Humidity exposure
AC voltage frequency

DIELECTRIC ABSORPTION

Mechanism:
Dielectric polarization effects
Time-dependent recovery
Affects precision applications
Material dependent property

Typical Values:
Polypropylene: 0.02%
Polyester: 0.2%
Polycarbonate: 0.1%
Polystyrene: 0.01%

- Bargunan Ponnusamy
 EQUIVALENT SERIES RESISTANCE (ESR)
ESR SOURCES AND MECHANISMS
Dielectric Losses:
Dielectric loss factor (tan δ)
Frequency dependent
Temperature dependent
Material specific property

Conductor Losses:
Electrode resistance
Termination resistance
Lead resistance
Skin effect at high frequency

ESR Frequency Dependence:

Low frequency: Dominated by dielectric losses
High frequency: Dominated by conductor losses
Transition frequency: Material and construction
dependent

ESR BY CAPACITOR TYPE

Capacitor Type Capacitance ESR @ 100kHz ESR @ 1MHz ESR @ 10MHz

Ceramic C0G 1 nF 0.1 Ω 0.05 Ω 0.02 Ω

Ceramic X7R 1 μF 0.01 Ω 0.005 Ω 0.002 Ω

Aluminum 100 μF 0.1 Ω 0.2 Ω 0.5 Ω

Tantalum 10 μF 0.05 Ω 0.08 Ω 0.15 Ω

Film PP 1 μF 0.002 Ω 0.001 Ω 0.0005 Ω

ESR Impact on Applications:

Power loss: P = I²ESR
Voltage ripple: Vr = Ir × ESR
Self-heating: ΔT = P × Rth
Efficiency reduction in switching circuits

- Bargunan Ponnusamy
 EQUIVALENT SERIES RESISTANCE (ESR)
ESR MEASUREMENT TECHNIQUES
LCR Meter Method:
Test signal: 1V RMS maximum
Accuracy: ±2% typical
Temperature: 25°C standard

Impedance Analyzer Method:

Frequency range: 40Hz to 110MHz
Dynamic range: 100dB
Accuracy: ±1% impedance, ±3° phase
Automated test capability

- Bargunan Ponnusamy
 EQUIVALENT SERIES INDUCTANACE (ESL)
ESL SOURCES
Package Inductance:
Lead length and geometry
Package construction
Termination design
Via inductance in PCB

Typical ESL Values:

0402 ceramic: 0.5nH
0603 ceramic: 1.0nH
0805 ceramic: 1.5nH
1206 ceramic: 2.0nH
Radial electrolytic: 5-15nH
Axial electrolytic: 10-30nH

SELF-RESONANT FREQUENCY
Resonance Equation:
fr = 1/(2π√(LC))
Below fr: Capacitive behavior
Above fr: Inductive behavior
Impedance minimum at fr
Typical Self-Resonant Frequencies:

Self-Resonant
Capacitor Type Capacitor Value Package
Frequency (SRF)

Ceramic 100 pF 603 500 MHz

Ceramic 1 nF 603 160 MHz

Ceramic 10 nF 603 50 MHz

Ceramic 100 nF 603 16 MHz

Ceramic 1 μF 603 5 MHz

- Bargunan Ponnusamy
 EQUIVALENT SERIES INDUCTANACE (ESL)
MULTIPLE RESONANCE EFFECTS
Anti-Resonance Phenomenon:
Series combination of different value capacitors
Impedance peak between individual SRFs
Degrades decoupling effectiveness
Mitigation: Proper value selection

Parallel Resonance:
Multiple capacitors of similar value
Resonance frequency splitting
Better decoupling performance

SELF-RESONANT FREQUENCY

- Bargunan Ponnusamy
 IMPEDANCE VS FREQUENCY BEHAVIOR
IMPEDANCE REGIONS
Capacitive Region (f < fr):
Z = √(R² + (1/2πfC)²)
Dominated by capacitive reactance
Impedance decreases with frequency
Phase approaches -90°

Resistive Region (f ≈ fr):

Z ≈ ESR
Minimum impedance point
Phase approaches 0°
Optimal decoupling frequency

Inductive Region (f > fr):

Z = √(R² + (2πfL)²)
Dominated by inductive reactance
Impedance increases with frequency
Phase approaches +90°

- Bargunan Ponnusamy
 IMPEDANCE VS FREQUENCY BEHAVIOR
TEMPERATURE EFFECTS ON IMPEDANCE
Ceramic Capacitors:
C0G: Minimal temperature coefficient
X7R: -15% to +15% over temperature
Y5V: +22% to -82% over temperature

Electrolytic Capacitors:
Capacitance: Decreases at low temperature
ESR: Increases significantly at low temperature
Useful life: Halves every 10°C increase

DC BIAS EFFECTS
Ceramic Class II Behavior:
Capacitance loss with applied DC voltage
Non-linear relationship
Worse at higher dielectric constants

DC Bias Test Data (X7R 1μF 25V):

Applied
CAP (%)
Voltage

0V 100%

5V 85%

10V 65%

15V 45%

20V 35%

25V 25%

- Bargunan Ponnusamy
 PARASITIC EFFECTS IN CIRCUITS
PCB PARASITICSTS ON IMPEDANCE
Via Inductance:
Typical value: 1-2nH per via
Length dependent
Diameter dependent
Multiple vias reduce inductance
Trace Inductance:
Microstrip: ~1nH/mm
Stripline: ~0.8nH/mm
Ground plane spacing dependent
Width dependent

COMPONENT PARASITICS
Resistor Parasitic Capacitance:
Chip resistors: 0.05-0.5pF
Creates low-pass filter with capacitor
Affects high-frequency response
Layout dependent

DC Bias Test Data (X7R 1μF 25V):

Winding capacitance: 1-50pF
Self-resonant frequency limitation
Q factor degradation
Shielding effects

- Bargunan Ponnusamy
 CAPACITOR SELECTION -
DATASHEET INTERPRETATION

KEY SPECIFICATIONS
Electrical Parameters:
Nominal capacitance and tolerance
Rated voltage (DC and AC)
Temperature coefficient/stability
Dissipation factor/ESR
Insulation resistance
Self-resonant frequency

Environmental Ratings:
Operating temperature range
Humidity resistance
Vibration/shock resistance
Flammability rating

Physical Specifications:
Package dimensions and tolerances
Termination finish and solderability
Marking and orientation
Tape and reel specifications

UNDERSTANDING TOLERANCE SPECIFICATIONS

Capacitance Tolerance Codes:

B: ±0.1pF (C < 10pF)
C: ±0.25pF (C < 10pF)
D: ±0.5pF (C < 10pF)
F: ±1%
G: ±2%
H: ±3% Temperature Coefficient Codes:
J: ±5% NP0/C0G: ±30ppm/°C
K: ±10% X7R: ±15% (-55°C to +125°C)
M: ±20% X5R: ±15% (-55°C to +85°C)
Z: +80/-20% (Y5V) Y5V: +22/-82% (-30°C to +85°C)

- Bargunan Ponnusamy
 CAPACITOR SELECTION -
DATASHEET INTERPRETATION

VOLTAGE RATING INTERPRETATION

DC Voltage Rating
Maximum continuous DC voltage
At maximum rated temperature
Includes safety margin
No derating for most ceramics

AC Voltage Rating:
RMS voltage for AC applications
Frequency dependent
Self-heating limitations
Power dissipation limits
Short duration overvoltage capability
Normally 1.5-2× DC rating
Duration: microseconds to milliseconds
Energy limited applications

- Bargunan Ponnusamy
 CAPACITOR SELECTION -
APPLICATION-SPECIFIC SELECTION CRITERIA

POWER SUPPLY APPLICATIONS

Bulk Capacitors:
Primary requirement: High capacitance
Secondary: Low ESR for ripple current
Aluminum electrolytic preferred
Ripple current rating critical

Selection Checklist:
Capacitance: 2-5× calculated minimum
Voltage rating: 25% derating minimum
ESR: <50mΩ for switching supplies
Ripple current: 2× calculated RMS
Operating temperature: -40°C to +105°C

- Bargunan Ponnusamy
 CAPACITOR SELECTION -
APPLICATION-SPECIFIC SELECTION CRITERIA

SIGNAL PROCESSING APPLICATIONS

Coupling Capacitors:
Low distortion requirement
Stable over temperature
Low dielectric absorption
Film capacitors preferred

Critical Parameters:
Capacitance stability: ±5% max
Temperature coefficient: <200ppm/° C
Dielectric absorption: <0.1%
Voltage coefficient: <100ppm/V
Frequency response: Flat to 100×signal frequency

- Bargunan Ponnusamy
 CAPACITOR SELECTION -
APPLICATION-SPECIFIC SELECTION CRITERIA

RF/MICROWAVE APPLICATIONS

Bypass Capacitors:
Low ESL requirement
Broadband impedance control
Multiple values in parallel
Ceramic C0G preferred

Design Requirements:
ESL: <1nH for >100MHz applications
Q factor: >200 @ 1MHz
Temperature stability: ±30ppm/°C
Package size: Minimize for lower ESL

- Bargunan Ponnusamy
 CAPACITOR IN POWER :
POWER DISTRIBUTION NETWORK (PDN) DESIGN

PDN IMPEDANCE REQUIREMENTS

Target Impedance Calculation:

Ztarget = Vripple / Itransient
Example: 5% ripple on 3.3V, 1A transient
Ztarget = (0.05×3.3V)/1A = 165mΩ

Frequency-Dependent Requirements:
DC to 1kHz: Bulk capacitors (electrolytic)
1kHz to 100kHz: Intermediate capacitors (ceramic)
100kHz to 10MHz: Local bypass capacitors
10MHz: PCB capacitance and design

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 CAPACITOR IN POWER :
POWER DISTRIBUTION NETWORK (PDN) DESIGN

MULTI-STAGE FILTERING STRATEGY

Stage 1 - Bulk Filtering:

Aluminum electrolytic: 100-1000μF
Location: Power supply output
Function: Energy storage, low-frequency filtering
ESR target: <100mΩ

Stage 2 - Intermediate Filtering:

Ceramic X7R: 1-47μF
Location: Power distribution points
Function: Medium frequency decoupling
ESR target: <10mΩ

Stage 3 - Local Bypass:

Ceramic C0G/X7R: 10-100nF
Location: IC power pins
Function: High-frequency bypass
ESR target: <1mΩ

- Bargunan Ponnusamy
 CAPACITOR IN POWER :
SWITCHING POWER SUPPLY CAPACITOR DESIGN

INPUT FILTER DESIGN

Requirements:
Input ripple current handling
EMI filtering
Holdup time during dropout
Inrush current limiting

Capacitor Selection:
Primary: Low ESR electrolytic
Secondary: High-frequency ceramic
Ripple current: √2 × Iout × D
Where D = duty cycle

Design Example - 12V to 3.3V, 5A Converter:

Switching frequency: 500kHz
Duty cycle: 3.3V/12V = 27.5%
Input ripple current: √2 × 5A × 0.275 = 1.94A RMS
Required capacitance: 220μF minimum
ESR requirement: <25mΩ for <100mV ripple

- Bargunan Ponnusamy
 CAPACITOR IN POWER :
SWITCHING POWER SUPPLY CAPACITOR DESIGN

OUTPUT FILTER DESIGN

Critical Parameters:
Output voltage ripple
Load transient response
ESR contribution to ripple
Capacitance contribution to ripple

Ripple Components:
ESR ripple: Vr_esr = Ir × ESR
Capacitive ripple: Vr_cap = Ir/(8×f×C)
Total ripple: √(Vr_esr² + Vr_cap²)

Optimization Strategy:
Balance ESR and capacitance contributions
Multiple parallel capacitors
Different technologies for frequency coverage
Minimize loop inductance

- Bargunan Ponnusamy
 CAPACITOR IN POWER :
LINEAR REGULATOR APPLICATIONS

INPUT CAPACITORS

Function:
Provide instantaneous current during load transients
Reduce input impedance
Improve PSRR at higher frequencies
Prevent oscillation

Typical Requirements:
LDO input: 1-10μF ceramic + 10-100μF electrolytic
Switching pre-regulator: 100-1000μF electrolytic
ESR: <100mΩ for stability
Placement: <10mm from regulator input

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 CAPACITOR IN POWER :
LINEAR REGULATOR APPLICATIONS

OUTPUT CAPACITORS

Stability Requirements:
Compensation for regulator loop
ESR zero for phase margin
Load transient response
Output noise filtering

ESR Requirements for Stability:

Most LDOs require minimum ESR
Typical range: 10mΩ to 1Ω
Too low ESR can cause oscillation
Series resistance may be added

Transient Response:
ΔVout = (ESR × ΔIload) + (ΔIload × Δt/C)
First term: Immediate response
Second term: Capacitive charging
Minimize both for best performance

- Bargunan Ponnusamy
CAPACITOR IN POWER :
DIGITAL IC POWER DISTRIBUTION

MICROPROCESSOR POWER DESIGN

Multiple Supply Requirements:
Core voltage: 0.8V-1.2V, high current
I/O voltage: 1.8V-3.3V, moderate current
PLL voltage: Clean, low noise
Analog voltage: Ultra-low noise

Decoupling Strategy per Supply:

Core: 470μF + 47μF + 10×100nF + 10×10nF
I/O: 100μF + 10μF + 4×100nF + 4×10nF
PLL: 47μF + 4.7μF + 470nF + 47nF + 4.7nF
Analog: 22μF + 2.2μF + 220nF + 22nF + 2.2nF

FPGA POWER DISTRIBUTION

Power Rail Classification:
VCCINT: Core logic supply
VCCIO: I/O bank supplies
VCCAUX: Auxiliary circuits
VCCO: Output driver supplies

Bank-Based Decoupling:
Each I/O bank: 10μF + 1μF + 100nF
Core supply: 22μF per 100 logic elements
PLL supplies: Separate LC filter + decoupling
Configuration supply: 47μF + 4.7μF + 470nF

- Bargunan Ponnusamy
CAPACITOR LAYOUT - PCB FUNDAMENTALS
PLACEMENT PRIORITY RULES
Priority 1 - Critical Bypass:
CPU/FPGA power pins: <5mm trace length
High-speed digital: <3mm trace length
RF circuits: <1mm trace length
Analog precision: Direct connection preferred

Priority 2 - Power Distribution:

Switching regulator output: <10mm
Linear regulator output: <15mm
Power connector filtering: <20mm
Bulk storage: <50mm acceptable

Priority 3 - Signal Conditioning:

Coupling capacitors: Near signal source
Filter capacitors: At circuit input
Timing capacitors: Near oscillator
Snubber capacitors: Across switching element

- Bargunan Ponnusamy
CAP - PCB DESIGN FUNDAMENTALS
LOOP MINIMIZATION TECHNIQUES
Current Loop Analysis:
High-frequency current path identification
Minimize loop area = minimize inductance
Power and ground connection optimization
Via placement strategy

Via Inductance Reduction:

Multiple parallel vias: L_total = L_single/N
Via diameter: Larger reduces inductance
Via length: Shorter reduces inductance
Typical values: 0.5-2nH per via

Trace Inductance:
Microstrip inductance ≈ 1nH/mm
Stripline inductance ≈ 0.8nH/mm
Wide traces reduce inductance
Ground proximity reduces inductance

- Bargunan Ponnusamy
CAP- HIGH-SPEED DIGITAL LAYOUT
POWER DELIVERY NETWORK LAYOUT
Plane-Based Design:
Dedicated power and ground planes
Multiple power planes for different voltages
Solid reference planes for signals
Controlled impedance for power distribution

Decoupling Capacitor Placement:

Symmetric placement around IC
Shortest possible connections
Multiple capacitor values
Avoid placement under IC package

CLOCK CIRCUIT CONSIDERATIONS

Crystal Oscillator Layout:
Load capacitors: <5mm from crystal
Ground guard rings around crystal
Separate analog ground region
Shield from digital switching

PLL Power Supply:

Dedicated LDO regulator
LC input filter: 10μH + 47μF
Multiple bypass capacitors: 10μF + 1μF + 100nF + 10nF
Separate ground region

- Bargunan Ponnusamy
CAP IN ANALOG- ACTIVE FILTER DESIGN
SALLEN-KEY TOPOLOGY
Component Matching:
Capacitor ratio accuracy: ±1%
Temperature tracking: <10ppm/°C difference
Frequency response: Flat within passband
Q factor stability: ±5% maximum

Low-Pass Filter Design:

Corner frequency: fc = 1/(2π√(R1R2C1C2))
Q factor: Dependent on component ratios
Gain: Set by feedback resistor ratio
Phase response: -180° at high frequency

MULTIPLE FEEDBACK TOPOLOGY

Bandwidth Considerations:
Op-amp GBW: >100× filter frequency
Capacitor selection affects stability
Temperature coefficient matching
Aging characteristics

High-Q Filter Challenges:

Component tolerance sensitivity
Temperature drift effects
Op-amp offset voltage impact
Parasitic effects at high frequency

- Bargunan Ponnusamy
CAP IN ANALOG- OSCILLATOR CIRCUITS
CRYSTAL OSCILLATOR DESIGN
Load Capacitance:
Crystal specification: CL = 12pF typical
PCB parasitic capacitance: 2-5pF
Required external capacitance: CL - Cparasitic
Capacitor matching: ±5% for frequency accuracy

Frequency Pulling:
Load capacitance variation: ±1pF
Frequency change: ±50ppm typical
Temperature coefficient: Crystal + capacitor
Aging rate: <±5ppm/year

VOLTAGE-CONTROLLED OSCILLATORS
Varactor Tuning:
Tuning voltage range: 0-5V typical
Capacitance variation: 10:1 ratio
Tuning sensitivity: MHz/V
Linearity: Deviation from ideal

Coupling Networks:
AC coupling: High-pass characteristic
Buffer amplifier isolation
Load impedance effects
Phase noise considerations

- Bargunan Ponnusamy
POWER SUPPLY DESIGN CASE STUDIES
BUCK CONVERTER DESIGN
Specifications:
Output voltage: 3.3V ±3%
Output current: 0-10A
Switching frequency: 500kHz
Efficiency target: >90%

Input Capacitor Selection:

RMS ripple current: √(Iout² × D × (1-D))
Where D = Vout/Vin = 3.3/12 = 0.275
Irms = √(10² × 0.275 × 0.725) = 4.46A
Selected: 220μF low-ESR electrolytic, Irms = 5A

Output Capacitor Design:

Ripple current: ΔIL/2 = (Vout×(1-D))/(2×L×fsw)
For L = 2.2μH: ΔIL = 2.75A
Ripple current in capacitor: 2.75A/2 = 1.38A
ESR requirement: <10mΩ for <50mV ripple
Selected: 470μF + 47μF ceramic parallel

- Bargunan Ponnusamy
POWER SUPPLY DESIGN CASE STUDIES
FLYBACK CONVERTER DESIGN
Specifications:
Input voltage: 85-265VAC
Output voltage: 12V, 2A
Isolation: 3kVAC
Regulation: ±5%

Primary Side Capacitor:

Bulk capacitance: C = 2×Pout/(η×Vmin²×2×fline)
C = (2×24W)/(0.8×108²×2×60Hz) = 43μF
Selected: 47μF, 400V electrolytic

Secondary Side Filter:

Output ripple at 2×fline = 120Hz
Required capacitance: C = Iout/(2×fripple×Vripple)
For 1% ripple: C = 2A/(2×120Hz×0.12V) = 69μF
Selected: 220μF, 25V low-ESR electrolytic

- Bargunan Ponnusamy
EX: SWITCH-MODE PWR SUPPLY DECOUPLING

SYSTEM REQUIREMENTS
Switching Frequency: 500kHz Output Current: 5A Voltage Ripple:
<50mV Input Voltage: 12V Output Voltage: 3.3V

CAPACITOR SELECTION PROCESS

Bulk Capacitance Calculation:
ΔI = 5A (worst case)
Δt = 1/(2×500kHz) = 1μs
C = ΔI×Δt/ΔV = 5×1μs/50mV = 100μF
ESR Requirement:
Ripple current: 2.5A RMS
Voltage ripple from ESR: <25mV
Maximum ESR: 25mV/2.5A = 10mΩ

Selected Components:
Bulk: 220μF aluminum electrolytic, ESR = 8mΩ
High-frequency: 47μF ceramic X7R, ESR = 2mΩ
Local: 1μF ceramic X7R, ESR = 5mΩ

PERFORMANCE VERIFICATION
Measured Results:
Output ripple: 35mV (meets requirement)
Transient response: 100mV overshoot
Efficiency: 92% (ESR losses = 0.5%)
Temperature rise: 15°C above ambient

- Bargunan Ponnusamy
SIGNAL PROCESSING IMPLEMENTATIONS
AUDIO AMPLIFIER DESIGN
Preamplifier Stage:
Input coupling: 1μF film cap
Feedback network: 100pF C0G
P.S bypass: 47μF + 1μF + 100nF
Output coupling: 10μF film cap

Critical Requirements:
THD+N: <0.01% @ 1kHz
Frequency: 20Hz-20kHz ±0.1dB
Input impedance: >10kΩ
Output impedance: <100Ω

Component Selection Rationale:

Film capacitors: Low distortion, stable
C0G ceramic: Precise frequency response
Electrolytic: Cost-effective bulk storage
Layout: Star grounding, short signal paths

- Bargunan Ponnusamy