TG: @Chalnaayaaar

Semiconductor Electronics Test (NEET Pattern)

Important Instructions
This test contains 57 questions. Each question carries 4 marks. For each correct response the
candidate will get 4 marks. For each incorrect response, one mark will be deducted from the total
scores. The maximum marks are 228.

1. On increasing the temperature the specific resistance of a semiconductor :–

(1) increases
(2) decreases
(3) does not change
(4) first decreases and then increases

2. Electric conduction in a semiconductor takes place due to :–

(1) electrons only
(2) holes only
(3) both electrons and holes
(4) neither electrons nor holes

3. Which of the following energy band diagram shows the n-type semiconductor :–

(1)

(2)

©  Digital [1]

 TG: @Chalnaayaaar

Semiconductor Electronics (NEET Pattern)

(3)

(4)

4. Let np and ne be the numbers of holes and conduction electrons in an extrinsic semiconductor.
(1) np > ne
(2) np = ne
(3) np < ne
(4) np  ne

5. Which statement is correct for p-type semiconductor

(1) the number of electrons in conduction band is more than the number of holes in valence band
at room temperature
(2) the number of holes in valence band is more than the number of electrons in conduction
band at room temperature
(3) there are no holes and electrons at room temperature
(4) number of holes and electrons is equal in valence and conduction band

6. When we convert pure semiconductor into n-type the number of hole :–

(1) Increases
(2) Decreases
(3) Remains constant
(4) None

7. Two wires P and Q made up of different materials have same resistance at room temperature.
When heated, resistance of P increases and that of Q decreases. We conclude that:–
(1) P and Q both are conductors but because of being made of different materials it happens so.
(2) P is n-type semiconductor and Q is p-type semiconductor.
(3) P is semiconductor and Q is conductor.
(4) P is conductor and Q is semiconductor.

 Digital [2]

 TG: @Chalnaayaaar

Semiconductor Electronics (NEET Pattern)

8. In an intrinsic semiconductor, number of electrons and holes at room temperature are :–

(1) equal
(2) zero
(3) unequal
(4) infinity

9. In semiconductor, at room temperature :–

(1) valence band are partially empty and conduction band are partially filled
(2) valence band are fully filled and conduction band are partially empty
(3) valence band are fully filled
(4) conduction band are fully empty

10. The probability of electrons to be found in the conduction band of an intrinsic semiconductor at
a finite temperature :–
(1) decreases exponentially with increasing band gap.
(2) increases exponentially with increasing band gap.
(3) decrease with increasing temperature.
(4) is independent of the temperature and the band gap.

11. A conducting wire of Copper and Germanium are cooled from room temperature to temperature
80K, then their resistance will :–
(1) increase
(2) decrease
(3) copper's increase and Germanium's decrease
(4) copper's decrease and Germanium's increase

12. Choose the false statement from the following :-

(1) the resistivity of a semiconductor increases with increase in temperature.
(2) substances with energy gap of the order of 10 eV are insulators.
(3) in conductors the valence and conduction bands may over lap.
(4) the conductivity of a semiconductor increases with increases in temperature.

13. Carbon, Silicon and Germanium atoms have four valence electrons each. Their valence and
conduction bonds are separated by energy band gaps represented by (Eg)C , (Eg)Si and (Eg)Ge
respectively. Which one of the following relationships is true in their case :–
(1) (Eg)C < (Eg)Ge
(2) (Eg)C > (Eg)Si
(3) (Eg)C = (Eg)Si
(4) (Eg)C < (Eg)Si

 Digital [3]

 TG: @Chalnaayaaar

Semiconductor Electronics (NEET Pattern)

14. In semiconducting material the mobilities of electrons and holes are µe and µh respectively.
Which of the following is true :–
(1) µe > µh
(2) µe < µh
(3) µe = µh
(4) µe < 0; µh > 0

15. Region which have no free electrons and holes in a p-n junction is :–
(1) p - region
(2) n - region
(3) junction
(4) depletion region

16. In a P–N Junction diode not connected to any circuit

(1) potential is the same every where.
(2) the P - type side is at a higher potential than the N - type side.
(3) there is an electric field at the junction directed from the N - type side to the P - type side.
(4) there is an electric field at the junction directed from the P - type side to the N - type side.

17. The majority current in a p-n junction is :–

(1) from the n-side to the p-side
(2) from the p-side to the n-side
(3) from the n-side to the p-side if the junction is forward-biased and in the opposite direction if
it is reverse biased
(4) from the p-side to the n-side if the junction is forward-biased and in the opposite direction if
it is reverse biased

18. A 2 V battery forward biases a diode however there is a drop of 0.5 V across the diode which is
independent of current. Also a current greater then 10 mA produces large joule loss and damages
diode. If diode is to be operated at 5 mA, the series resistance to be put is :–
2V

(1) 3 k
(2) 300 k
(3) 300 
(4) 200 k

 Digital [4]

 TG: @Chalnaayaaar

Semiconductor Electronics (NEET Pattern)

19. Which of the following diode is reverse biased :–

(1)

(2)

(3)

(4)

20. Find VAB :–

30V 10
A
10 10
B
(1) 10 V
(2) 20 V
(3) 30 V
(4) none

21. Current I in the circuit will be :–

20
30

20 5V

5
(1) A
40
5
(2) A
50
5
(3) A
10
5
(4) A
20

 Digital [5]

 TG: @Chalnaayaaar

Semiconductor Electronics (NEET Pattern)

22. In a unbias p-n junction :-

(1) high potential is at n side and low potential is at p side.
(2) high potential is at p side and low potential is at n side.
(3) p and n both are at same potential.
(4) undetermined.

23. On increasing the reverse bias to a large value in p-n junction diode then value of current
(1) remains fixed
(2) increases slowly
(3) decrease slowly
(4) suddenly increase

24. Reverse bias applied to a junction diode :–

(1) lowers the potential barrier.
(2) raises the potential barrier.
(3) increases the majority carrier current.
(4) increases the minority carrier current.

25. Correct statement for diode is :–

(1) in full wave rectifier both diodes work alternatively.
(2) in full wave rectifier both diodes work simultaneously.
(3) efficiency of full wave rectifier and half wave rectifier is same.
(4) full wave rectifier in bidirectional.

26. The width of depletion region in a p-n junction diode

(1) increases when reverse bias is applied.
(2) increases when a forward bias is applied.
(3) decreases when a reverse bias is applied.
(4) remains the same irrespective of the bias voltage.

27. For the given circuit shown in fig, to act as full wave rectifier :– a.c. input should be connected
across ................. and ..................... the d.c. output would appear across ................ and .....................
A

B D

C
(1) A, C, B, D
(2) B, D, A, C
(3) A, B, C, D
(4) C, A, D, B

 Digital [6]

 TG: @Chalnaayaaar

Semiconductor Electronics (NEET Pattern)

28. Forbidden energy gap of Ge is 0.75 eV, maximum wave length of incident radiation of photon for
producing electron - hole pair in germanium semiconductor is :–
(1) 4200 Å
(2) 16500 Å
(3) 4700 Å
(4) 4000 Å

29. In the circuit given the current through the zener diode is :-

R1 500
15V
1500 R2 VZ = 10V

(1) 10 mA
(2) 6.67 mA
(3) 5 mA
(4) 3.33 mA

30. In p-n junction photocell electromotive force due to monochromatic light is proportional to
(1) p-n potential barrier
(2) intensity of light
(3) frequency of light
(4) p-n applied voltage

31. Zener dode is used for :–

(1) rectification
(2) stabilization
(3) amplification
(4) producing oscillations in an oscillator

32. A transistor is used in the common emitter mode as an amplifier then :–

(A) the base emitter junction is forward baised.
(B) the base emitter junction is reverse baised.
(C) the input signal is connected in series with the voltage applied to bias the base emitter
junction.
(D) the input signal is connected in series with the voltage applied to bias the base collector
junction.
(1) A, B
(2) A, D
(3) A, C
(4) only C

 Digital [7]

 TG: @Chalnaayaaar

Semiconductor Electronics (NEET Pattern)

33. In transistor symbols, the arrows shows the direction of :-

(1) current in the emitter
(2) electron current in the emitter
(3) holes current in the collector
(4) electron current in the collector

34. The region of transistor in which extra impurity is doped to obtain a large number of majority
carrier is called as :–
(1) emitter
(2) base
(3) collector
(4) any one of these depending upon the transistor

35. The current gain  of a transistor is 50. The input resistance of the transistor, when used in the
common emitter configuration, is 1 k. The peak value of the collector a.c. current for an
alternating peak input voltage 0.01 V is :–
(1) 100 µA
(2) 250 µA
(3) 500 µA
(4) 800 µA

36. The input resistance of a silicon transistor is 1 k. If base current is changed by 100 µA, it causes
the change in collector current by 2 mA. This transistor is used as a CE amplifier with a load
resistance of 5 k. What is the ac voltage gain of amplifier ?
(1) 10
(2) 100
(3) 500
(4) 200

37. In the following common emitter circuit if  = 100, VCE = 7 V, VBE = negligible, RC = 2 k then IB
is :-
IB IC
RB RC
C
15V
B
E

(1) 0.01 mA
(2) 0.04 mA
(3) 0.02 mA
(4) 0.03 mA

 Digital [8]

 TG: @Chalnaayaaar

Semiconductor Electronics (NEET Pattern)

38. What is the voltage gain in a common emitter amplifier where input resistance is 3  and load
resistance is 24  and current gain  = 6 ?
(1) 2.2
(2) 1.2
(3) 4.8
(4) 48

39. In a n-p-n transistor circuit, the collector current is 10 mA. If 90% of the electrons emitted reach
the collector then the emitter current (IE) and base current (IB) are given by :–
(1) IE = 1 mA; IB = 11 mA
(2) IE = 11 mA ; IB = 1 mA
(3) IE = –1 mA; IB = 9 mA
(4) IE = 9 mA ; IB = –1 mA

IC I
40. In the study of transistor as amplifier if  = and  = C where IC, IB, and IE are the collector,
IE IB
base and emitter current, then :–

(1)  =
1+

(2)  =
1−
1+
(3)  =

1−
(4)  =


41. In the CB mode of a transistor, when the collector voltage is changed by 0.5 volt, the collector
current changes by 0.05 mA. the output resistance will be
(1) 10 k
(2) 20 k
(3) 5 k
(4) 2.5 k

42. In the case of constants  and  of a transistor :–

(1)  = 
(2)  < 1 ;  > 1
(3)  = 1
(4)  > 1 ;  < 1

 Digital [9]

 TG: @Chalnaayaaar

Semiconductor Electronics (NEET Pattern)

43. Consider an n–p–n transistor amplifier in common–emitter configuration. The current gain of
the transistor is 100. If the collector current changes by 1 mA, what will be the change in emitter
current ?
(1) 1·1 mA
(2) 1·01 mA
(3) 0·01 mA
(4) 10 mA

44. The output of the given logic gate is 1 when inputs A, B and C are such that :–
A Y
B
C

(1) A = 1, B = 0, C = 1
(2) A = 1, B = 1, C = 0
(3) A = B = C = 0
(4) A = B = C = 1

45. Which of the following Boolean expression is not correct :–

(1) A.B = A + B
(2) A + B = A . B
(3) A.B = A.B
(4) 1 + 1 = 1

46. The truth table shown below is for which of the following gates :–
A B Y
1 1 1
0 1 0
1 0 0
0 0 1
(1) XNOR
(2) AND
(3) XOR
(4) NOR

47. The NOR gate is logically equivalent to an OR gate followed by :–

(1) an inverter
(2) a NOR gate
(3) a NAND gate
(4) All of above

 Digital [10]

 TG: @Chalnaayaaar

Semiconductor Electronics (NEET Pattern)

48. To get an output 1, the input ABC should be :–

A
B Y
C

(1) 101
(2) 100
(3) 110
(4) 010

49. The circuit shown here is logically equivalent to :–

A Y
B
(1) OR gate
(2) AND gate
(3) NOT gate
(4) NAND gate

50. A two-input NAND gate is followed by a single-input NOR gate. This logic circuit will function as :-
(1) an AND gate
(2) an OR gate
(3) a NOT gate
(4) a NOR gate

51. The logic symbols shown here are logically equivalent to :–

A Y A Y
B B
(a) (b)
(1) (a) AND and (b) OR gate
(2) (a) NOR and (b) NAND gate
(3) (a) OR and (b) AND gate
(4) (a) NAND and (b) NOR gate

52. The combination of the gates shown will produce

A

(1) OR gate
(2) AND gate
(3) NOR gate
(4) NAND gate

 Digital [11]

 TG: @Chalnaayaaar

Semiconductor Electronics (NEET Pattern)

53. The combination of the gates shown will produce

A

B
(1) AND gate
(2) NAND gate
(3) NOR gate
(4) XOR gate

54. The truth table for the following combination of gates is :-

A Y

B
A B Y
0 0 0
(1) 0 1 0
1 0 1
1 1 1
A B Y
0 0 0
(2) 0 1 0
1 0 0
1 1 1
A B Y
0 0 1
(3) 0 1 1
1 0 1
1 1 0
A B Y
0 0 0
(4) 0 1 1
1 0 1
1 1 0

55. In the Boolean algebra A.B equals :–

(1) A + B
(2) A + B
(3) A . B
(4) A . B

 Digital [12]

 TG: @Chalnaayaaar

Semiconductor Electronics (NEET Pattern)

56. How many NOR gates are required to form NAND gate :–
(1) 1
(2) 3
(3) 2
(4) 4

57. Out of the following, universal gate is :–

(1) NOT
(2) OR
(3) AND
(4) NAND

 Digital [13]

 TG: @Chalnaayaaar

Semiconductor Electronics (NEET Pattern)

Answer Key
Question 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Answer 2 3 2 4 2 2 4 1 1 1 4 1 2 1 4
Question 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Answer 3 2 3 3 1 2 1 4 2 1 1 2 2 4 2
Question 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
Answer 2 3 1 1 3 2 2 4 2 2 1 4 2 4 4
Question 46 47 48 49 50 51 52 53 54 55 56 57
Answer 1 4 1 1 1 4 3 4 1 2 4 4

SOLUTIONS
1. (2)

2. (3)

3. (2)

4. (4)

5. (2)

6. (2)

7. (4)

8. (1)

9. (1)

10. (1)
Eg
−
n = AT e
3/2 2kT

11. (4)

12. (1)

13. (2)

14. (1)

15. (4)

16. (3)

 Digital [14]

 TG: @Chalnaayaaar

Semiconductor Electronics (NEET Pattern)

17. (2)

18. (3)
When P-N junction is operated at 5mA
(2 – 0.5) = 5 × 10–3 × R
R = 300 

19. (3)

20. (1)
P-N junction in forward bias
VAB = IR'
10R 10R
30V 30V
A
10R 10R  VAB 5R
B
 30 
=   5R = 10V
 15R 

21. (2)

20 20
30 30

20 5V 20 5V

5
I= A
50

22. (1)

23. (4)

24. (2)

25. (1)

26. (1)

27. (2)

 Digital [15]

 TG: @Chalnaayaaar

Semiconductor Electronics (NEET Pattern)

28. (2)
12400 12400
(In Å)    16500 Å
Eg (ineV) 0.75
So max = 16500Å

29. (4)

I
R1 500
15V I2
I1
1500 R2 VZ = 10V

10 = I2R2 = I2 × 1500
I2 = 6.67 mA
V = IR1 + VZ
15 = I × 500 + 10
5
I= = 10mA
500
I = I 1 + I2
I2 = I – I1 = (10 – 6.67)mA = 3.33mA

30. (2)

31. (2)

32. (3)

33. (1)

34. (1)

35. (3)
Vi 0.01
Peak input current (IB) = = A = 0.01mA
R i 103
Peak output current (IC) = IB = 50 × 0.01 = 500µA

36. (2)
Given that Ri = 1k, R0 = 5 k
IB = 100mA, IC = 2mA
I 2mA
= C = = 20
IB 100A
R0 5k
AV =  = 20  = 100
Ri 1k

 Digital [16]

 TG: @Chalnaayaaar

Semiconductor Electronics (NEET Pattern)

37. (2)
VCC = VCE + ICRC
V − VCE (15 − 7)V
IC = CC = = 4mA
RC 2k
IC I 4mA
=  IB = C = = 0.04mA
IB  100

38. (4)
RL 24
Voltage gain =  = 6 = 48 V
R in 3

39. (2)
For a transistor, IE = IB + IC ....(i)
90 9
Given that, IC = IE = IE
100 10
Since IC = 10 mA, we have
10
IE = 10 × mA = 11.1 mA
9
 IB = IE – IC = (11.1 – 10)mA (Using (i))
= 1.1 mA

40. (2)

41. (1)
Given that
V0 = 0.5V
I0 = 0.05mA
V 0.5V
R0 = 0 = = 10k
I0 0.05mA
42. (4)

43. (2)
IC 1mA
=  IB = = 0.01mA
IB 100
IE = IB + IC = 0.01 + 1 = 1.01mA

44. (4)

45. (4)

46. (1)

 Digital [17]

 TG: @Chalnaayaaar

Semiconductor Electronics (NEET Pattern)

47. (4)

48. (1)

49. (1)

50. (1)

51. (4)

52. (3)

53. (4)

A
B
Y

A
B

Y = AB + AB
= A  B = XOR gate

54. (1)
A
A Y

B AB
Y = A + AB = A(1+B)
=A

55. (2)

56. (4)

57. (4)

 Digital [18]

 TG: @Chalnaayaaar

Semiconductor Electronics NEET PYQs (NEET Pattern)

1. A transistor-oscillator using a resonant circuit with an inductor L (of negligible resistance) and
a capacitor C in series produce oscillations of frequency f. If L is doubled and C is changed to 4C,
the frequency will be: -
f
(1)
4
(2) 8f
f
(3)
2 2
f
(4)
2
AIPMT 2006 (+4 /–1)
2. The following figure shows a AND logic gate circuit with two inputs A and B and the output C.
The voltage waveforms of C will be –
A Logic gate
C
B circuit

A t
1

B t
(1)

(2)
(3)

(4)
AIPMT 2006 (+4 /–1)
3. In the energy band diagram of a material shown below, the open circles and filled circles denote
holes and electrons respectively. The material is :-
EC
Eg

EV

 Digital [1]

 TG: @Chalnaayaaar

Semiconductor Electronics NEET PYQs

(1) an n-type semiconductor

(2) a p-type semiconductor
(3) an insulator
(4) a metal
AIPMT 2007 (+4 /–1)

4. A common emitter amplifier has a voltage gain of 50, an input impedance of 100  and an output
impedance of 200 . The power gain of the amplifier is: -
(1) 100
(2) 500
(3) 1000
(4) 1250
AIPMT 2007 (+4 /–1)

5. In the following circuit, the output Y for all possible inputs A and B is expressed by the truth
table: -
A
Y
B
A B Y
0 0 0
(1) 0 1 1
1 0
2 1
2
1 1 1
A B Y
0 0 0
(2) 0 1 0
1 0
2 0
1 1 1
A B Y
0 0 1
(3) 0 1 1
1 0
2 1
1 1 0
A B Y
0 0 1
(4) 0 1 0
1 0
2 0
1 1 0
AIPMT 2007 (+4 /–1)

6. A p–n photodiode is made of a material with a band gap of 2.0 eV. The minimum frequency of
the radiation that can be absorbed by the material is nearly: -
(1) 1 × 1014 Hz
(2) 20 × 1014 Hz
(3) 10 × 1014 Hz
(4) 5 × 1014 Hz
AIPMT 2008 (+4 /–1)

 Digital [2]

 TG: @Chalnaayaaar

Semiconductor Electronics NEET PYQs

7. The voltage gain of an amplifier with 9% negative feedback is 10. The voltage gain without
feedback will be: -
(1) 1.25
(2) 100
(3) 90
(4) 10
AIPMT 2008 (+4 /–1)

NOR NAND NOT

8. The circuit is equivalent to: -

(1) NOR gate

(2) OR gate
(3) AND gate
(4) NAND gate
AIPMT 2008 (+4 /–1)

9. A p-n photodiode is fabricated from a semiconductor with a band gap of 2.5 eV. It can detect a
signal of wavelength: -
(1) 4000 Å
(2) 6000 Å
(3) 4000 nm
(4) 6000 nm
AIPMT 2009 (+4 /–1)

10. The symbolic representation of four logic gates are given below: -
A
(i) (ii)
B
A
(iii) (iv)
B
The logic symbols for OR, NOT and NAND gates are respectively: -
(1) (i), (iii), (iv)
(2) (iii), (iv), (ii)
(3) (iv), (i), (iii)
(4) (iv), (ii), (i)
AIPMT 2009 (+4 /–1)

11. The device that can act as a complete electronic circuit is: -
(1) Zener diode
(2) Junctions diode
(3) Integrated circuit
(4) Junction transistor
AIPMT 2010 (+4 /–1)

 Digital [3]

 TG: @Chalnaayaaar

Semiconductor Electronics NEET PYQs

12. Which one of the following statement is false?

(1) The resistance of intrinsic semiconductor decreases with increase of temperature.
(2) Pure Si doped with trivalent impurities gives a p-type semiconductor.
(3) Majority carriers in a n-type semiconductor are holes.
(4) Minority carriers in a p-type semiconductor are electrons.
AIPMT 2010 (+4 /–1)
13. To get an output Y = 1 in given circuit which of the following input will be correct:
A
B Y
C
A B C
(1) 1 1 0
(2) 0 1 0
(3) 1 0 0
(4) 1 0 1
AIPMT 2010 (+4 /–1)
14. A zener diode, having breakdown voltage equal to 15 V, is used in a voltage regulator circuit
shown in figure. The current through the zener diode is :-
+ 250

20V 15V 1k

–
(1) 5 mA
(2) 10 mA
(3) 15 mA
(4) 20 mA
AIPMT 2011 (+4 /–1)
15. In the following figure, the diodes which are forward biased, are :-
+10V
+5V R R
(a) (b)
–10V

(c) (d)
–12V R
R

–5V
–5V
(1) (a), (b) and (d)
(2) (c) only
(3) (a) and (c)
(4) (b) and (d)
AIPMT 2011 (+4 /–1)

 Digital [4]

 TG: @Chalnaayaaar

Semiconductor Electronics NEET PYQs

16. Pure Si at 500 K has equal number of electron (ne) and hole (nh) concentrations to 1.5 × 1016 m–3.
Doping by indium increases nh to 4.5 × 1022 m–3. The doped semiconductor is of: -
(1) p-type having electron concentrations ne = 5 × 109 m–3
(2) n-type with electron concentration ne = 5 × 1022 m–3
(3) P-type with electron concentration ne = 2.5 × 1010 m–3
(4) n-type with electron concentration ne =2.5 × 1023 m–3
AIPMT 2011 (+4 /–1)

17. A transistor is operated in common emitter configuration at VC = 2 V such that a change in the
base current from 100 µA to 300 µA produces a change in the collector current from 10 mA to
20 mA. The current gain is :-
(1) 50
(2) 75
(3) 100
(4) 25
AIPMT 2011 (+4 /–1)

18. In forward biasing of the p–n junction: -

(1) The positive terminal of the battery is connected to p–side and the depletion region becomes
thick.
(2) The positive terminal of the battery is connected to n-side and the depletion region becomes
thin.
(3) The positive terminal of the battery is connected to n-side and the depletion region becomes
thick.
(4) The positive terminal of the battery is connected to p-side and the depletion region becomes
thin.
AIPMT 2011 (+4 /–1)

19. If a small amount of antimony is added to germanium crystal:

(1) it becomes a p-type semiconductor
(2) the antimony becomes an acceptor atom
(3) there will be more free electrons than holes in the semiconductor
(4) its resistance is increased
AIPMT 2011 (+4 /–1)

20. Symbolic representation of four logic gates are shown as: -

(i) (ii) (iii) (iv)

Pick out which ones are for AND, NAND and NOT gates, respectively: -
(1) (ii), (iii) and (iv)
(2) (iii), (ii) and (i)
(3) (iii), (ii) and (iv)
(4) (ii), (iv) and (iii)
AIPMT 2011 (+4 /–1)

 Digital [5]

 TG: @Chalnaayaaar

Semiconductor Electronics NEET PYQs

21. In a CE transistor amplifier, the audio signal voltage across the collector resistance of
2 k is 2 V. If the base resistance is 1k and the current amplification of the transistor is 100,
the input signal voltage is: -
(1) 1 mV
(2) 10 mV
(3) 0.1 V
(4) 1.0 V
AIPMT 2012 (+4 /–1)

22. C and Si both have same lattice structure, having 4 bonding electrons in each. However, C is
insulator where as Si is intrinsic semiconductor. This is because: -
(1) The four bonding electrons in the case of C lie in the second orbit, whereas in the case of Si
they lie in the third.
(2) The four bonding electrons in the case of C lie in the third orbit, whereas for Si they lie in the
fourth orbit.
(3) In case of C the valence band is not completely filled at absolute zero temperature.
(4) In case of C the conduction band is partly filled even at absolute zero temperature
AIPMT 2012 (+4 /–1)

23. Transfer characteristics [(output voltage (V0) vs input voltage (Vi)] for a base biased transistor
in CE configuration is as shown in the figure. For using transistor as a switch, it is used.
V0 I II III
I

Vi
(1) in region II
(2) in region I
(3) in region III
(4) both in region (I) & (III)
AIPMT 2012 (+4 /–1)

24. The input resistance of a silicon transistor is 100 . Base current is changed by 40 µA which
results in a change in collector current by 2 mA. This transistor is used as a common emitter
amplifier with a load resistance of 4 k. The voltage gain of the amplifier is: -
(1) 4000
(2) 1000
(3) 2000
(4) 3000
AIPMT 2012 (+4 /–1)

 Digital [6]

 TG: @Chalnaayaaar

Semiconductor Electronics NEET PYQs

25. The figure shown a logic circuit two inputs A and B and the output C. The voltage wave forms
across A, B and C are as given. The logic circuit gate is: -

C
O t1 t2 t3 t4 t5 t6
(1) AND gate
(2) NAND gate
(3) OR gate
(4) NOR gate
AIPMT 2012 (+4 /–1)

26. In a common emitter (CE) amplifier having a voltage gain G, the transistor used has
transconductance 0.03 mho and current gain 25. If the above transistor is replaced with another
one with transconductance 0.02 mho and current gain 20, the voltage gain will be :
5
(1) G
4
2
(2) G
3
(3) 1.5G
1
(4) G
3
NEET-UG 2013 (+4 /–1)

27. In a n-type semiconductor, which of the following statement is true: -

(1) Holes are majority carriers and trivalent atoms are dopants.
(2) Electrons are majority carriers and trivalent atoms are dopants.
(3) Electron are minority carriers and pentavalent atoms are dopants.
(4) Holes are minority carriers and pentavalent atoms are dopants.
NEET-UG 2013 (+4 /–1)

28. The output (X) of the logic circuit shown in figure will be: -
A
B X

(1) X = A + B
(2) X = A.B
(3) X = A.B
(4) X = A.B
NEET-UG 2013 (+4 /–1)

 Digital [7]

 TG: @Chalnaayaaar

Semiconductor Electronics NEET PYQs

29. The given graph represents V - I characteristic for a semiconductor device.

I
A
V
B

Which of the following statement is correct?

(1) It is V - I characteristic for solar cell where, point A represents open circuit voltage and point
B short circuit current.
(2) It is a for a solar cell and point A and B represent open circuit voltage and current,
respectively.
(3) It is for a photodiode and points A and B represent open circuit voltage and current,
respectively.
(4) It is for a LED and points A and B represent open circuit voltage and short circuit current,
respectively.
NEET-UG 2014 (+4 /–1)
30. The barrier potential of a p-n junction depends on:
(a) type of semiconductor material
(b) amount of doping
(c) temperature
Which one of the following is correct?
(1) (a) and (b) only
(2) (b) only
(3) (b) and (c) only
(4) (a), (b) and (c)
NEET-UG 2014 (+4 /–1)

31. Which logic gate is represented by the following combination of logic gates?
Y1
A
Y
B
Y2
(1) NAND
(2) AND
(3) NOR
(4) OR
AIPMT-2015 (+4 /–1)

32. If in a p-n junction, a square input signal of 10 V is applied as shown,

+5V

RL

–5V
then the output across RL will be: -

 Digital [8]

 TG: @Chalnaayaaar

Semiconductor Electronics NEET PYQs

10V
(1)

(2)
–5V
5V
(3)

(4)
–10V
AIPMT-2015 (+4 /–1)

33. In the given figure, a diode D is connected to an external resistance R =100  and an e.m.f
of 3.5 V. If the barrier potential developed across the diode is 0.5 V, the current in the
circuit will be: -
D 100

3.5V
(1) 35 mA
(2) 30 mA
(3) 40 mA
(4) 20 mA
AIPMT-2015 (+4 /–1)

 
34. The input signal given to a CE amplifier having a voltage gain of 150 is Vi = 2 cos  15t +  . The
 3
corresponding output signal will be -
 4 
(1) 300 cos  15t + 
 3 
 
(2) 300 cos  15t + 
 3
 2 
(3) 75 cos  15t + 
 3 
 5 
(4) 2 cos  15t + 
 6 
AIPMT-2015 (+4 /–1)

 Digital [9]

 TG: @Chalnaayaaar

Semiconductor Electronics NEET PYQs

35. Consider the junction diode as ideal. The value of current flowing through AB is: -
A 1k B
+4V –6V
(1) 0A
(2) 10–2 A
(3) 10–1 A
(4) 10–3 A
NEET-I 2016 (+4 /–1)

36. A npn transistor is connected in common emitter configuration in a given amplifier. A load
resistance of 800  is connected in the collector circuit and the voltage drop across it is 0.8 V. If
the current amplification factor is 0.96 and the input resistance of the circuit is 192, the voltage
gain and the power gain of the amplifier will respectively be :
(1) 4, 3.84
(2) 3.69, 3.84
(3) 4, 4
(4) 4, 3.69
NEET-I 2016 (+4 /–1)

37. To get output 1 for the following circuit, the correct choice for the input is
A
B
C Y
(1) A = 0, B = 1, C = 0
(2) A = 1, B = 0, C = 0
(3) A = 1, B = 1, C = 0
(4) A = 1, B = 0, C = 1
NEET-I 2016 (+4 /–1)

38. For CE transistor amplifier, the audio signal voltage across the collector resistance of 2 k
is 4 V. If the current amplification factor of the transistor is 100 and the base resistance is 1 k,
then the input signal voltage is: -
(1) 30 mV
(2) 15 mV
(3) 10 mV
(4) 20 mV
NEET-II 2016 (+4 /–1)

39. The given circuit has two ideal diodes connected as shown in the figure below. The current
flowing through the resistance R1 will be: -

 Digital [10]

 TG: @Chalnaayaaar

Semiconductor Electronics NEET PYQs

2

R1 D1 D2
10V R2 R3
3 2

(1) 1.43 A
(2) 3.13 A
(3) 2.5 A
(4) 10.0 A
NEET-II 2016 (+4 /–1)

40. What is the output Y in the following circuit, when all the three inputs A,B,C are first 0 and
then 1?
A
P
B Q Y
C
(1) 1,0
(2) 1,1
(3) 0,1
(4) 0.0
NEET-II 2016 (+4 /–1)

41. In a common emitter transistor amplifier the audio signal voltage across the collector is 3V. The
resistance of collector is 3 k. If current gain is 100 and the base resistance is 2 k, the voltage
and power gain of the amplifier is: -
(1) 15 and 200
(2) 150 and 15000
(3) 20 and 2000
(4) 200 and 1000
NEET(UG) 2017 (+4 /–1)

42. The given electrical network is equivalent to: -

A Y
B
(1) OR gate
(2) NOR gate
(3) NOT gate
(4) AND gate
NEET(UG) 2017 (+4 /–1)

 Digital [11]

 TG: @Chalnaayaaar

Semiconductor Electronics NEET PYQs

43. Which one of the following represents forward bias diode?

R –3V
(1) –4V
R
(2) –2V +2V

R
(3) 3V 5V

R
(4) 0V –2V

NEET(UG) 2017 (+4 /–1)

44. In the combination of the following gates the output Y can be written in terms of inputs
A and B as :-
A
B Y

(1) A . B
(2) A . B + A . B
(3) A . B + A.B
(4) A + B
NEET(UG) 2018 (+4 /–1)

45. In the circuit shown in the figure, the input voltage Vi is 20 V, VBE = 0 and VCE = 0. The values of
IB, IC and  are given by: -
20V

RC 4k
RB C
Vi
B
500k E

(1) IB = 40 A, IC = 10 mA,  = 250

(2) IB = 25 A, IC = 5 mA,  = 200
(3) IB = 20 A, IC = 5 mA,  = 250
(4) IB = 40 A, IC = 5 mA,  = 125
NEET(UG) 2018 (+4 /–1)

 Digital [12]

 TG: @Chalnaayaaar

Semiconductor Electronics NEET PYQs

46. In a p-n junction diode, change in temperature due to heating: -

(1) affects only reverse resistance
(2) affects only forward resistance
(3) does not affect resistance of p-n junction
(4) affects the overall V – I characteristics of p-n junction
NEET(UG) 2018 (+4 /–1)

47. The correct Boolean operation represented by the circuit diagram drawn is :
+6V

O R

A 1
LED (Y)

R
O
B 1

(1) AND
(2) OR
(3) NAND
(4) NOR
NEET(UG) 2019 (+4 /–1)

48. For a p-type semiconductor which of the following statements is true?

(1) Electrons are the majority carriers and trivalent atoms are the dopants.
(2) Holes are the majority carriers and trivalent atoms are the dopants.
(3) Holes are the majority carriers and pentavalent atoms are the dopants.
(4) Electrons are the majority carriers and pentavalent atoms are the dopants.
NEET(UG) 2019 (+4 /–1)

49. An LED is constructed from a p-n junction diode using GaAsP. The energy gap is 1.9 eV. The
wavelength of the light emitted will be equal to :-
(1) 10.4 × 10–26 m
(2) 654 nm
(3) 654 Å
(4) 654 × 10–11 m
NEET(UG) 2019 (Odisha) (+4 /–1)

 Digital [13]

 TG: @Chalnaayaaar

Semiconductor Electronics NEET PYQs

50. The circuit diagram shown here corresponds to the logic gate,
+6V

O R
A
1
O
B
1
LED (Y)

(1) NOR
(2) AND
(3) OR
(4) NAND
NEET(UG) 2019 (Odisha) (+4 /–1)

 Digital [14]

 TG: @Chalnaayaaar

Semiconductor Electronics NEET PYQs

Answer Key
Question 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Answer 3 1 2 4 1 4 2 1 1 4 3 3 4 1 3
Question 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Answer 1 1 4 4 4 2 1 4 3 3 2 4 2,4 1 4
Question 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
Answer 2 3 2 1 2 1 4 4 3 1 2 2 4 2 4
Question 46 47 48 49 50
Answer 4 3 2 2 1

SOLUTIONS
1. (3)
1
We knows that oscillating frequency (f ) =
2 LC
1 1
Now, f ' = =
2 (2L)(4C) 2 8LC
f' 1 f
=  f'=
f 2 2 2 2

2. (1)
3. (2)
4. (4)
R 
Voltage gain =   out 
 R in 
50  100
= = 25
200
Power gain = (Voltage gain)
= (25)(50) = 1250
5. (1)
6. (4)
E 2  1.6  10−19
E = h   = = −34
= 5  1014 Hz
h 6.62  10
7. (2)
A
Af =
1 + A '
A
10 =
 9 
1 + A 
 100 
10 + 0.9A = A
A = 100

 Digital [15]

 TG: @Chalnaayaaar

Semiconductor Electronics NEET PYQs

8. (1)

9. (1)
To detect a signal
hc hc
 Eg       4960Å
 Eg

10. (4)
------------

11. (3)
------------

12. (3)
------------

13. (4)
------------

14. (1)
5V
+ I 250 I2
I1
20V 1k 15V

–
5
Here I = A = 20 mA
250
15
I2 = A = 15 mA
1  103
So, I1 = I – I2 = 5 mA

15. (3)
------------

16. (1)
We know (ni)2 = ne × nh
(1.5 × 1016)2 = ne × (4.5 × 1022)
ne = 5 × 109 m–3

 Digital [16]

 TG: @Chalnaayaaar

Semiconductor Electronics NEET PYQs

17. (1)
IC (20 − 10)  10−3
= = = 50
IB (300 − 100) 10−6

18. (4)
------------

19. (4)
------------

20. (4)
------------

21. (2)
V0 R
AV = = 0
Vi Ri
2V 2k
 = 100 
Vi 1k
Vi = 10mV

22. (1)
------------

23. (4)
------------

24. (3)
Iout R out (2mA)(4k)
Vgain = = = 2k
IinR in (40A)(100)

25. (3)
------------

26. (2)
Iout
gm =
Vin
Iout R L
Vgain =
Vin
Vgain = gmRL

 Digital [17]

 TG: @Chalnaayaaar

Semiconductor Electronics NEET PYQs

Vgain  g mR L
gm = Transconductance
G 0.03
Now =
V2 0.02
2
V2 = G
3
27. (4)
------------
28. (2, 4)
------------
29. (1)
------------
30. (4)
------------
31. (2)
y1 = A,y 2 = B,
y = y1 + y2 = A + B (using De-morgan's theorem)
y=A·B
Hence this logic gate represents AND gate.
32. (3)
This is the circuit where P-N junction is acting as a Half-wave rectifier so the output will be
5V

33. (2)
Potential difference on R = 3.5 – 0.5 = 3.0 volt
V 3
Current in circuit i = = = 30mA
R 100
34. (1)
 
Input signal v in = 2cos  15t + 
 3
Voltage Gain = 150
CE amplifier gives phase difference of p between input and output signals
V
A v = 0 so V0 = AV Vin
Vin
  
So V0 = 150  2cos  15t + +  
 3 
 4 
V0 = 300cos  15t +
 3 

 Digital [18]

 TG: @Chalnaayaaar

Semiconductor Electronics NEET PYQs

35. (2)
Since diode is in forward bias
V 4 − (–6) 10
i= = 3
= 3 = 10−2 A
R 1  10 10

36. (1)
RL 800
AV =  = 0.96  =4
R in 192
AP =  × AV = 0.96 × 4 = 3.84

37. (4)
---------

38. (4)
V0 R 4 2  103
AV = =  0  = 100 
Vi Ri Vi 103
 Vi = 20 mV

39. (3)
Current will not flow through D1 as it is reverse biased. Current will flow through cell,
R1, D2 and R3.
10
 i = = 2.5 A
2+2
40. (1)
A AB
P
B Q
C
For A = B = C = 0 ; y = 1
For A = B = C = 1 ; y = 0

41. (2)
RC 3k
AV =  = 100  = 150
RB 2k
Power gain AV  100 × 150 = 15000

42. (2)
NOR NOR NOT
A
B y1 y2 y
y1 = A + B
y 2 = y1 + y1 = y1 = A + B = A + B
y = y2 = A + B NOR GATE

 Digital [19]

 TG: @Chalnaayaaar

Semiconductor Electronics NEET PYQs

43. (4)
R
V1 V2
In forward bias V1 > V2
 only
0V –2V
is in forward bias

44. (2)
A
A
B

45. (4)
Vi = IBRB + VBE
 20 = IB × (500 × 103) + 0
20
 IB = = 40µA
500  103
 VCC = ICRC + VCE
 20 = IC × (4 × 103) + 0
 IC = 5 × 10–3 = 5 mA
IC 5  10−3
 = = = 125
IB 40  10−6

46. (4)
Due is heating, number of electrons hold pairs will increase that affects the overall V – I
characteristics of p-n junction

47. (3)
A B Y
0 0 1
0 1 1
1 2 0 2 1
1 1 0
 It is a NAND Gate

48. (2)
For P type
Holes are majority & trivalent atoms are the dopants.

 Digital [20]

 TG: @Chalnaayaaar

Semiconductor Electronics NEET PYQs

49. (2)
1240nm
= = 652.6nm 654nm
1.9

50. (1)
A B Y
0 0 1
0 1 0
1 0
2 0
1 1 0

 Digital [21]