Microprocessor

Unit 3 : Memory Management

3.1 Complete Address Translation

In real mode, The 80386 forms the physical address by moving the segment selector (which is
part of the logical address) left by 4 bits (multiplying by 16) and then adding the offset to it.
In protected mode, the processor converts logical addresses (addresses used by programs)
into physical addresses (actual locations in memory) in two steps:
Segment Translation: The segment selector shows where the segment starts. This starting
address is added to the 32-bit offset to get the linear address.
Page Translation: If paging is enabled, the linear address is converted into the physical address
using page tables, it depends on whether paging is turned on. If paging is not enabled, the
linear address is directly used as the physical address.

3.2 Segment Translation in 80386

In the 80386 protected mode, segment translation is the process of converting a logical
address into a linear address. A logical address consists of two parts:
Segment Selector (16-bit)
Offset (32-bit effective address)

The translation involves the following steps:

1. Segment Selector to Descriptor:
The segment selector is used to locate the segment descriptor in either the Global Descriptor
Table (GDT) or Local Descriptor Table (LDT). It contains:
Index (points to the descriptor)
TI bit (to choose GDT or LDT)
RPL (Privilege Level)
2. Descriptor to Base Address:
The segment descriptor contains:
32-bit Base Address
Segment Limit
Access Rights and Flags
The CPU extracts the base address of the segment from the descriptor.
3. Forming the Linear Address:
The base address from the descriptor is added to the 32-bit offset to generate the 32-bit linear
address
If paging is disabled, the linear address becomes the physical address. If paging is enabled, this
linear address undergoes a second step (paging translation) to become the physical address.
3.3 Paging Translation
In protected mode, the 80386 processor supports paging as an optional second stage of
address translation. It converts a linear address into a physical address using a two-level
paging mechanism.
Steps in Paging Translation:
Linear Address Structure (32-bit):
The 32-bit linear address is divided into three fields:
Dir: Index into the Page Directory
Page: Index into the Page Table
Offset: Offset within the 4KB physical page

Page Directory Access:

The CR3 register holds the Page Directory Base Address.
Using the Dir field, the CPU locates the Page Table Address from the page directory entry.

Page Table Access:

The Page field indexes into the selected Page Table to fetch the Page Frame Base Address.

Forming the Physical Address:

The Page Frame Base Address is added to the 12-bit Offset to produce the final Physical
Address.

Page Tables : Paging is a memory management method in 80386 used to divide the linear
address space into small pages (each 4 KB).
Instead of storing entire programs in one segment, paging breaks memory into equal-sized
blocks for efficient access and protection.
PDE (Page Directory Entry) Descriptor : A PDE is one entry in the Page Directory. Each PDE
points to a Page Table.
Contains:
Base address of the Page Table
Flags like:
P (Present): 1 if page table is in memory
R/W (Read/Write): access rights
U/S (User/Supervisor): user mode or kernel
PTE (Page Table Entry) Descriptor : A PTE is one entry in a Page Table. Each PTE points to a
physical memory page (4 KB).
Contains:
Base address of a 4 KB physical memory page
Flags similar to PDE:
P (Present): 1 if page is in memory
R/W: Read or write permission
U/S: User or system level
3.4 Logical address
A logical address is the address generated by the CPU during program execution.
It consists of:
Segment Selector (16-bit)
Offset (32-bit)
In protected mode, it is represented as:
Logical Address = Segment Selector : Offset
This address needs to be translated before accessing memory.

3.5 Linear Address

A linear address is the intermediate address obtained after segment translation.
It is calculated as:
Linear Address = Segment Base Address + Offset
If paging is disabled, the linear address is directly used as the physical address. If paging is
enabled, it is further translated.

3.6 Physical Address

The physical address is the actual address in the RAM (main memory) where data/instructions
are stored.
If paging is enabled:
Physical Address = Page Frame Base + Offset
This is the final address sent to the memory unit to fetch/store data.

3.7 Descriptor Table Instructions in 80386

1. LGDT – Load Global Descriptor Table Register
Full Form: Load Global Descriptor Table
Syntax: LGDT mem
Description: Loads the base address and limit of the Global Descriptor Table (GDT) from
memory into the GDTR register.
2. SGDT – Store Global Descriptor Table Register
Full Form: Store Global Descriptor Table
Syntax: SGDT mem
Description: Stores the current contents of the GDTR register into the specified memory
location.
3. LLDT – Load Local Descriptor Table Register
Full Form: Load Local Descriptor Table
Syntax: LLDT reg/mem16
Description: Loads a segment selector into the LDTR (Local Descriptor Table Register).
4. SLDT – Store Local Descriptor Table Register
Full Form: Store Local Descriptor Table
Syntax: SLDT reg/mem16
Description: Stores the current selector from the LDTR into memory or a register.
5. LIDT – Load Interrupt Descriptor Table Register
Full Form: Load Interrupt Descriptor Table
Syntax: LIDT mem
 Description: Loads the base and limit of the Interrupt Descriptor Table (IDT) into the IDTR
register.
6. SIDT – Store Interrupt Descriptor Table Register
Full Form: Store Interrupt Descriptor Table
Syntax: SIDT mem
Description: Stores the contents of the IDTR register to memory.

3.8 Segment Descriptors : System and Non-System Descriptors

In Protected Mode, the 80386 microprocessor uses segment descriptors to define the
properties of memory segments

1. System Descriptors :
These descriptors are used by the Operating System to manage special system functions like
task switching, interrupt handling, and segmentation.
The S bit = 0 in the descriptor indicates a system descriptor.
Types :
LDT Descriptor (Local Descriptor Table)
Points to the base and limit of the LDT.
Allows each task to have its own private segment descriptors.
Stored in GDT and loaded using the LLDT instruction.
TSS Descriptor (Task State Segment)
Defines a special segment that stores task context (registers, stack pointers, etc.).
Enables hardware task switching.
TSS is essential for multitasking environments.
Accessed using LTR (Load Task Register) and JMP/CALL Task instructions.
Gate Descriptors
Used to control transfer of control between segments, especially across different privilege
levels. Gates include:
Call Gate: Allows controlled access to higher privilege procedures.
Interrupt Gate: Used in IDT to handle hardware interrupts.
Trap Gate: Similar to interrupt gate but doesn't disable interrupts.
Task Gate: Points to a TSS for task switching via interrupts.

2. Non-System Descriptors
These are the code and data segments used by application programs.
The S bit = 1 indicates a non-system descriptor.
Types :
Code Segment Descriptor
Stores program instructions (executable code).
Accessed by the CS (Code Segment) register.
Can be marked readable or conforming (for privilege level transitions).
Data Segment Descriptor
Stores variables, constants, and stack.
Accessed via DS, ES, SS, FS, GS registers.
Can be marked readable/writable.
May grow upwards or downwards (like stack segments).
3.9 GDTR
The GDTR (Global Descriptor Table Register) is a special register in the 80386 microprocessor
used to manage memory segmentation in protected mode.
GDTR holds the base address and limit of the Global Descriptor Table (GDT), which contains
segment descriptors used to define code, data, and system segments globally across tasks.

Contents of GDTR:
Field Size Description
Base 32 bits Points to the starting address of GDT
Limit 16 bits Specifies the size (length) of GDT in bytes minus one
GDTR itself is not part of memory; it's an internal CPU register.
It is loaded using the LGDT instruction and stored using SGDT.

3.10 LDTR
The LDTR (Local Descriptor Table Register) is a special register in the 80386 microprocessor
that holds information about the Local Descriptor Table (LDT), which provides task-specific
segment descriptors.
LDTR points to the LDT, which stores the code, data, and stack segments for a specific task.
Contents of LDTR:
LDTR itself holds a selector that points to an LDT descriptor located in the Global Descriptor
Table (GDT). This descriptor provides:

Field Size Description

Base 32 bits Base address of the LDT in memory
Limit 16 bits Size of the LDT in bytes minus one
Flags -- Access rights and segment type info

3.11 IDTR
 The IDTR (Interrupt Descriptor Table Register) is a special 80386 CPU register that holds the
base address and limit of the Interrupt Descriptor Table (IDT). The IDT is used for handling
interrupts and exceptions.
IDTR tells the processor where the IDT is, which holds the addresses of routines that handle
hardware and software interrupts.
Contents of IDTR:
Field Size Description
Base 32 bits Starting address of the Interrupt Descriptor Table
Limit 16 bits Size of the IDT in bytes minus one

IDTR is loaded using the LIDT instruction and stored using the SIDT instruction.
The IDT can contain up to 256 entries (0 to 255 interrupt vectors).

3.12 Difference Between GDTR,LDTR and IDTR

GDTR (Global Descriptor LDTR (Local Descriptor IDTR (Interrupt Descriptor
Point
Table Register) Table Register) Table Register)
Holds the base and limit Holds the base and Holds the base and limit for
Purpose
for the GDT. limit for the LDT. the IDT.
Global segments in Local segments for Interrupt handling
Used By
memory. specific tasks. routines.
Refers to the Local
Descriptor Refers to the Global Refers to the Interrupt
Descriptor Table
Table Descriptor Table (GDT). Descriptor Table (IDT).
(LDT).
All processes in the Specific to a particular Used for interrupt handling
Accessed By
system. process or task. by the CPU.
Managed by the Managed by the
Managed by the operating
Control operating system operating system per
system globally.
globally. task.
Size 8 bytes (base + limit). 8 bytes (base + limit). 8 bytes (base + limit).
Used for global memory Provides protection Used for interrupt
Protection
protection. for local memory. protection.
Limits the size of the Limits the size of the Limits the size of the
Limit
global address space. local address space. interrupt table.

3.13 General Format Of Descriptor

 Base: This is where the segment starts in memory. It helps the 80386 processor know where
the segment is located in the memory space (which can be up to 4GB).
Limit: This tells how big the segment is. The 80386 combines two parts of the limit to form a
20-bit value. It can interpret this value in two ways:
If the Granularity bit (G) is 0: The limit is in bytes, and the segment can be up to 1MB
(1,048,576 bytes).
If the Granularity bit (G) is 1: The limit is in 4KB units, and the segment can be up to 4GB
(4,294,967,296 bytes).
Granularity bit: This bit tells how the limit should be read:
0 means the limit is in bytes (small units).
1 means the limit is in 4KB chunks (larger units).
Reserved (0): This bit is reserved by Intel, meaning you can't use it or change it. It's there for
future processors.
AVL/U (User Bit): This bit is ignored by the processor. It’s for the operating system or users to
use for their own purposes.
Access Rights Byte:
P (Present Bit): This bit tells if the segment is loaded in memory. If it’s 0, trying to access this
segment will cause an error.
DPL (Descriptor Privilege Level): This tells how "important" or "privileged" a segment is. A
higher DPL means higher privileges (more control).
S (System Bit): If this bit is 1, it means the segment is either a code or data segment. If it's 0,
it’s a system segment.
Type: This defines what kind of segment it is (like data, code, or system).
A (Accessed Bit): The processor automatically sets this bit whenever the segment is accessed.
It helps track when the segment has been used.

3.14 General Selector Format

In 80386, a selector is a 16-bit value used to choose a segment from memory. It tells the CPU
which segment to use.
The selector is divided into 3 parts:

Index (13 bits) –

This is the biggest part (bits 3 to 15).
It gives the entry number in the descriptor table.
The descriptor tells where the segment starts and other details.

TI (Table Indicator - 1 bit) –

Bit 2 of the selector.
Tells which table to use:
0 = GDT (Global Descriptor Table)
1 = LDT (Local Descriptor Table)

RPL (Requestor’s Privilege Level - 2 bits) –

Bits 0 and 1.
Shows the privilege level (0 = highest, 3 = lowest).
Used for protection and access control.
3.15 Explain GDT,LDT and IDT
1. GDT (Global Descriptor Table)
GDT is used to define all global segments.
It is common for all programs in the system.
Each entry in GDT is a segment descriptor – it gives the base address, limit, and access rights
of a segment.
Example segments in GDT: Code, Data, Stack, Video memory, etc.
GDT is always used when TI bit = 0 in the selector.

2. LDT (Local Descriptor Table)

LDT is used for per-process segment definitions.
Each program (task) can have its own LDT.
It allows multi-tasking, where each task has a different memory view.
LDT also has segment descriptors like GDT.
LDT is used when TI bit = 1 in the selector.

3. IDT (Interrupt Descriptor Table)

IDT is used to handle interrupts and exceptions.
Each entry in IDT is an interrupt descriptor.
It gives the address of the Interrupt Service Routine (ISR).
IDT is used when an interrupt or exception occurs.
Example: Divide by zero, page fault, keyboard interrupt, etc.