CIC

Verification--Calibre

4-1
CIC

Verification--Calibre
‡ Concept
‡ Design Rule check
‡ Layout vs. Schematic
‡ Parasitic Extraction using XCalibre

4-2
CIC

Verification--Calibre
‡ Concept
‡ Design Rule check
‡ Layout vs. Schematic
‡ Parasitic Extraction using XCalibre

4-3
CIC
Design Flows
Netlist

Simulation

Automated Layout Full Custom Editing

Completed Layout

Layout Verification

4-4
CIC
The Need of Layout Verification
‡ Functional Design verification is only for designer
‡ Physical design must meet process rules for manufacture
reliability
‡ Even commercial placement & route tool can introduce
error
‡ Converting layout database to foundry acceptable format
may introduce error
‡ The performance of design after layout need to be verified

4-5
CIC

Basic of Layout Verification

‡ Layout verification is process dependent
Need a database for describing process information
‡ Input for layout verification
Layout database - GDS2 format (CIF , Cadence )
Netlist information (For LVS / backannotated LPE)
Process specified information
‡ Layout Verification
Incremental vs Full chip
Hierarchical vs Flatten
Online vs Offline

4-6
CIC

Commercial Verification Tools

‡ Cadence
¾Dracula,
¾Assura,
¾DIVA(online)
‡ Synopsys
¾ Hercules, Start RC
‡ Mentor
¾ Calibre, XCalibre

4-7
CIC

Layout Verification
‡ DRC(Design Rule Check):
z checks physical layout data against fabrication-specific rules
‡ ERC(Electrical Rule Check):
z checks for electrical violations
‡ LVS(Layout Versus Schematic):
z checks the connectivity of a physical layout design to its related schematic
‡ LPE(Layout Parasitic Extraction):
z extracts the parasitic effect resulted from the interconnection of layout design

4-8
CIC

Verification--Calibre
‡Concept
‡Design Rule check
‡Layout vs. Schematic
‡Parasitic Extraction using XCalibre

4-9
CIC

Layout Formats for Calibre

‡ This layout database can be in several formats, the
most common being:
z ASCII - American Standard Code for Information
Interchange
z GDS - Gerber Data Stream
z CIF - CalTech Intermediate Format

4 - 10
CIC

What is a SVRF ?
‡ Stand Verification Rule Format (SVRF)
file – rule file (or called command file)
z Used by calibre
z A language standard that controls tool functionality
‡ The rule file has two main elements.
zOperations
zSpecification statements

4 - 11
CIC Examples of SVRF Rule File
Statements
‡ Layer Statements
layer PWELL 1
layer OXIDE 2
layer RES 3
layer POLY 4
‡ Derived Layers
gate = poly and oxide
sd = oxide not poly
‡ Connect Statements
connect metal1 poly nsd psd by contact
connect metal2 metal1 by via
‡ RuleChecks
min_poly_width {internal poly < 1.25}
min_metal1_space {external metal1 < 2.0}
‡ Device Statements
device mn ngate poly nsd nsd pwell [0]

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CIC

Required DRC Specification Statements

‡ Layout System
The input layout database type: GDSII, CIF, BINARY, or ASCII.
Layout System GDSII
‡ Layout Path
The pathname of the layout database
Layout Path “/user/proj/layout/design.gds”
‡ Layout Primary
The name of the top-level cell or subcircuit to check.
Layout Primary top_cell_name
‡ DRC Results Database
The pathname of the output results database for DRC. Can also
specify the database type (ASCII, BINARY, or GDSII).
DRC Results Database “/user/proj/layout/sample.db”

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CIC

Calibre DRC Output Files and Formats

Calibre DRC creates two output files:
‡ DRC Results Database
‡ ASCII (default)
z Used for: Calibre RVE
‡ Binary
z Used for: 3rd party tools
‡ GDSII
z Used for: Changing the database using Calibre; input for other editors
Example syntax:
DRC RESULTS DATABASE results.db ASCII
‡ DRC Summary Report (optional)
‡ ASCII
Example syntax:
DRC SUMMARY REPORT summary_report HIER

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CIC

Invoking and Running Flat Calibre DRC

‡ Invoke Calibre DRC from a command shell.
calibre -drc <rule_file>
calibre -drc /project/technology/cmos.rules

‡ Enter calibre with no arguments to display help:

calibre { -drc [ -writedatabase ] [ -mergedatabase ]
| | -drc -hier [ -turbo [ <number_of_processors> ] ]
-mergedatabase ]} [ -64 ] <rule_file_name>

‡ Arguments:
‡ writedatabase: Translates GDSII layout database to binary polygon format.
‡ mergedatabase: Directs GDSII reader to merge geometries on a per-cell,
per-layer basis as the stream is read into memory.
‡ rule_file_name: The pathname to the rule file.

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CIC
Running Calibre DRC(1)

virtuoso link
virtuoso Calibre

4 - 16
CIC
Using Calibre DRC (2)
Calibre DRC rule file

run Calibre DRC 料

(output)
錄

run Hierarchical Flat

layout file(GDSII) Import

layout view 若
layout Database 行
layout file

check layout
(check area)

4 - 17
CIC

Using Calibre -- DRC (3)

DRC Result format

layout_cell_name.drc.result
setup -> option更

run DRC立 RVE

DRC Report
layout_cell_name.drc.summary
run DRC
report

run DRC summary report

4 - 18
 CIC
Using Calibre -- DRC (4)
setup -> select checks

Show rule file裡 rule file裡

rule click groups click
rule不 check group
rule不 check

rule

4 - 19
CIC
Using Calibre -- DRC (5)
Run Calibre DRC option
64bit server 行
不

Transcript 錄Run DRC 若 利

行 利 Transcript -> Save as
log file

Run DRC 行Calibre DRC check

行 RVE

4 - 20
CIC

Calibre RVE
Click 立 Layout Tool (
Virtuoso Layout Editor) show error
edge

Show DRC DRC rule

Error

click eroor error

show Layout Tool
checktext rule

4 - 21
CIC

Using RVE to Locate Discrepancy

3. Highlight error Error display in report

2. Read Checktext 1. Select error 4. Error highlighted in layout

4 - 22
CIC

Calibre DRC Report & Debug

error更 run DRC

Error RVE no error
summary report Rule-Check
Result Statistics欄 rule

4 - 23
CIC

2-Layer Spacing Example (1)

Example Rule
PO.O.1 { @ Poly endcap >= 0.3um
ENC OD POLY < 0.3 ABUT < 90
SINGULAR}

Extension too
small

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CIC

2-Layer Spacing Example (2)

CO.E.1 { @ Active olap contact < 0.14, also floating contacts
ENC CO_DIFF OD < 0.14 SINGULAR ABUT <90 OUTSIDE ALSO REGION
}

Enclosure
Violation

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CIC

2-Layer Spacing Example (3)

4.20D.ad {@ Minimum Metal1 overlap contac is 0um, no contact outside Metal1
E = NOT CONT ME1
E NOT (BLSP OR BLSP1)
}

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CIC

2-Layer Spacing Example (4)

4.20D.bc {@ metal enclose contact at end-of-line or outer corner is 0.08
x = ENC [CONT] ME1 < 0.08 ABUT<90 OPPOSITE // co edge with metal enc < 0.08
E = INT x < 0.24 ABUT==90 INTERSECTING ONLY REGION
E NOT ((SRAM OR BLSP1) OR DP1)
}

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CIC

Between Layer Spacing Example (5)

4.20B.a {@ Minimum space between ME1 regions is 0.24um
where MET1 width < 10um
E = EXT ME1 < 0.24 ABUT>0<90 REGION
E NOT (BLDP OR BLSP1)
}

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CIC

Layer Width Example(1)

4.20A {@ Minimum width of ME1 region is 0.24um
E = INT ME1 < 0.24 ABUT>0<90 SINGULAR REGION
E NOT (BLDP OR BLSP1)
}

4 - 29
CIC
Introduction to Antenna
Problems
„ Antenna checks limit damage to gate oxide during mask fabrication due to
excessive charge collected on polysilicon and/or metal interconnect.
„ A simple antenna check would read like this: “The ratio of the polysilicon
area+metal1 on same net to the total area of the gates formed by the
polysilicon polygons on the net must be less than 50.”

Poly
Metal

4 - 30
CIC

Antenna Check Example

„ Reduce the length of any of the metal or poly layers that
are included in the antenna check rule.

VARIABLE CAR_PO_ME 400 //Cumulative Antenna Ratio

ANT.me6_ca {@ Poly+ME1+ME2+ME3+ME4+ME5+ME6 area / gate area >= 400 unless connected to diode
x = NET AREA RATIO me6_gate_ca DIODE ==0
y = NET AREA RATIO PO1 x >0
z = NET AREA RATIO ME1 y >0
u = NET AREA RATIO ME2 z >0
l = NET AREA RATIO ME3 u >0
m = NET AREA RATIO ME4 l >0
n = NET AREA RATIO ME5 m >0
o = NET AREA RATIO ME6 n >0
ornet (ornet (ornet (ornet (ornet (ornet y z) u) l ) m) n) o
}

4 - 31
CIC

Antenna Errors Highlighted

„ Using RVE, antenna violations may be shown in the layout:
Net in violation of an antenna RuleCheck
involving Poly and Metal1

4 - 32
CIC

RuleCheck Selection
‡ By default, Calibre DRC selects and executes all RuleChecks.
‡ Control which rules Calibre DRC executes with:
DRC Select Check rule_name
‡ Calibre DRC uses only the rules you name with this statement, otherwise all
rules are run.
‡ Use DRC Select Check when you want to run only one or a few of the rules.

DRC Unselect Check rule_name

‡ Calibre DRC does not select the rules you name with this and does not use them,
but it selects and runs all the other rules.
‡ Use DRC Unselect Check when you want to run all the rules except one or a few.

‡ Warning: Remove these from the Rule file after completion!

Example:
//DRC UNSELECT CHECK METOP_20KA
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CIC

Rule Check Grouping

‡Form RuleCheck groups with:
Group name rule_check1… rule_checkN
‡Enables you to group a series of RuleChecks together
under one name.
‡Use of the “?” wildcard matches zero or more characters.
‡Very useful in combination with DRC (Un)Select Check

4 - 34
CIC

Rule Check Grouping Example

GROUP METOP_8KA 4.31?_8KA GROUP METOP_20KA 4.31?_20KA
// //
m6x = SIZE ME6 BY -0.2 // width <= 0.4 are deleted 4.31A_20KA {@ Minimum width of ME6 region is 1.2um
m6y = SIZE m6x BY -4.79 // width < 10 are deleted INT ME6 < 1.2 ABUT>0<90 SINGULAR REGION }
BMET6a = SIZE m6y BY 4.99 4.31B.a_20KA {@ Minimum space between two ME6 regions is 1.0um
BMET6 = ME6 COIN INSIDE EDGE BMET6a // BMET6: MET6 width EXT ME6 < 1.0 ABUT>0<90 REGION }
>= 10 4.31B.b_20KA {@ Minimum space between MET6(width>=10um) regions is
1.5um
4.31A_8KA {@ Minimum width of ME6 region is 0.44um x = EXT BMET6 ME6 < 1.5 REGION
INT ME6 < 0.44 ABUT>0<90 SINGULAR REGION } x NOT IND }
4.31B.a_8KA {@ Minimum space between two ME6 regions is 0.44um 4.31C.ad_20KA {@ Minimum ME6 overlap VI5 is 0.4um, no VI5 outside ME6
EXT ME6 < 0.44 ABUT>0<90 REGION } ENC VI5 ME6 < 0.4 ABUT<90 OUTSIDE ALSO REGION }
4.31B.b_8KA {@ Minimum space between MET6(width>=10um) regions 4.31C.bc_20KA {@ metal6 enclose Via5 at end-of-line or outer corner is 0.4
is 0.60um x = ENC [VI5] ME6 < 0.40 ABUT<90 OPPOSITE // via edge with metal
EXT BMET6 ME6 < 0.60 REGION } enc < 0.4
4.31C.ad_8KA {@ Minimum ME6 overlap VI5 is 0um, no VI5 outside INT x < 0.28 ABUT==90 INTERSECTING ONLY REGION}
ME6 4.31D_20KA {@ Minimum ME6 Area 9.0 sq. um.
NOT VI5 ME6 } AREA ME6 < 9.0}
4.31C.bc_8KA {@ ME6 enclose Via5 at end-of-line or outer corner is 0.12 4.31H_20KA {@ The minimum overlap of IND block to inductor layer is 10um
x = ENC [VI5] ME6 < 0.12 ABUT<90 OPPOSITE // via edge with @ Only Inductor ME6 is allowed in IND
metal enc < 0.12 IND_MET = ME6 AND LSYMBOL
INT x < 0.28 ABUT==90 INTERSECTING ONLY REGION CONN_M6 = ME6 NOT LSYMBOL
} X = ENC IND_MET IND < 10 ABUT<90 SINGULAR OVERLAP
4.31D_8KA {@ Minimum ME6 Area 0.4624 sq. um2 OUTSIDE ALSO REGION
AREA ME6 < 0.4624 } X NOT INTERACT CONN_M6
((ME6 AND IND) INTERACT LSYMBOL) NOT LSYMBOL}

4 - 35
CIC

Layout Window Selection

‡ Selector unselecta reas of the layout for DRC using:
Layout Window x1 y1 x2 y2… xN yN
‡ Enables you to specify a simple closed polygon window for DRC checking.
‡ Window vertex coordinates are with respect to the top cell.
‡ Polygons within or crossing the window border get processed.
‡ May be specified multiple times.
‡ Numeric variables may be passed as arguments.
‡ Specifying only two pairs of non-collinear coordinates isinterpreted as a
rectangle.
Layout Windel x1 y1 x2 y2… xN yN
‡ Enables you to exclude a simple closed polygon window from DRC checking;
similar to Layout Window in all other respects.

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CIC

Layout Window Selection

Example:

兩
DRC

4 - 37
CIC

Cell Exclusion
‡ Calibre normally checks every cell.
‡ To exclude alignmentmarkers, trademarks, and so on, use:
Exclude Cell cell_name
‡ Calibre will process no objects from any placement of the
excluded cell, including all hierarchical instances.
‡ Cell names can include wildcard characters: Not supported for
binary and ASCII input database formats.

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CIC

Maximum Results Reporting

‡ To control the total number of results generated per RuleCheck, use:
DRC Maximum Results max | ALL
‡ Specifying ALL means thatev ery result( error) for each RuleCheck gets
reported and sent to the DRC Results Database; use this setting for GDS
database manipulation.
‡ The default is 1000 results per RuleCheck, after which a warning is
issued and results output is suspended.
‡ If the default value is excessive, choose a smaller number.
‡ Avoid using ALL or numbers greater than 1000 for everyday use; the
output becomes too great to manage efficiently.

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CIC

Hierarchical Calibre DRC

Calibre DRC-H:
‡ Minimizes redundant processing
‡ Stores, analyzes, and processes data once per cell instead of once for
every flat placement of the cell
‡ Uses design database hierarchy to reduce processing time,
memory usage, and DRC result counts
‡ Uses the same Rule file as flat Calibre DRC
‡ Produces a DRC results database in same format as flat
Calibre DRC
‡ Imposes NO design restrictions

4 - 40
CIC

Hierarchical Error Suppression

‡ Flat DRC verification reports every instance of an error:
‡ One error in a cell reported once for each instance of cell
‡ Calibre DRC-H reports the error only once
Report only one error

Cell A Cell B Cell C

Top-Cell

4 - 41
CIC

When to Use Calibre DRC-H

‡ The greater the repetition or design re-use in a layout, the
greater benefit you will get from Calibre DRC-H.
‡ Memory design
‡ Gate arrays
‡ System-on-chip
‡ Standard cell
‡ Datapath
‡ General profile of a chip that can take advantage of
hierarchical processing:
“Uses process of 0.35 or below, and has one million or more
transistors.”

4 - 42
CIC

Running Calibre DRC-H

‡ Full syntax:
calibre {-drc -hier
[[-mergedatabase][-writedatabase]|
[-turbo [ no_of_cpus][-mergedatabase]]
[-64]]} rule_file_name
‡ Typical syntax for Calibre DRC-H (single cpu):
calibre -drc -hier rule_file_name
‡ Typical syntax for Calibre DRC-H (multiple cpu):
calibre -drc -hier -turbo rule_file_name

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CIC

Hierarchical Summary Report

‡ You can enhance the summary report with:
DRC Summary Report file_name HIER
‡ Directs Calibre DRC-H to create an extra section in the DRC summary
report file that lists non-empty RuleCheck statistics by layout database
cell.

4 - 44
CIC

Calibre DRC Transcript

‡Layer statistics (flat)

‡Layer statistics (hierarchical)

4 - 45
CIC

Verification--Calibre
‡Concept
‡Design Rule check
‡Layout Versus Schematic
‡Parasitic Extraction using XCalibre

4 - 46
CIC
Layout Versus Schematic
Design View
z Composer

Layout View
zVirtuoso
zLaker
Schematic HDL
Compilation Compilation
Connectivity Device
Extraction Extraction Comparison
Source Netlist
Phase

Layout Netlist
Verification
Results

4 - 47
CIC

Layout vs. Schematic Check

‡ 路
‡ LVS ERC
‡ 行LVS DRC
‡ Tape-out LVS Error-free
‡ LVS TEXT label
‡ 更 LVS

4 - 48
CIC
Process Flow for Calibre LVS
Completed Completed
Rule File
Source Layout

Netlist
CALIBRE LVS extraction

Extracted
Report File LVS Results
Netlist
Data Base

Determine Errors Locate Errors Using Correct Layout

form Report RVE & Layout Tool Errors

4 - 49
CIC

Additional Statements Required for Calibre LVS

‡ Layout specification statements

‡ LAYOUT SYSTEM CIF | GDSII | ASCII | BINARY | CNET | SPICE
‡ LAYOUT PATH pathname // “/user/x/mydesign.gds”
‡ LAYOUT PRIMARY cellname // topcell
‡ Source specification statements
‡ SOURCE SYSTEM CNET | SPICE
‡ SOURCE PATH pathname // “/user/x/mydesign.spi”
‡ SOURCE PRIMARY cellname
‡ Results database specification statements
‡ MASK SVDB DIRECTORY directoryname QUERY
‡ Report file specification statement
‡ LVS REPORT filename // “lvs.rpt”

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CIC

The Calibre LVS Results Database

‡Standard Verification DataBase Directory (RVE)
‡ layout_primary.phdb - persistent hierarchical database
‡ layout_primary.dv - discrepancy viewer file
‡ layout_primary.xdb - cross reference information file

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CIC

The Calibre LVS Report File

‡ LVS generates the report in ASCII format
‡ Report is readable either with an ASCII editor or with
Calibre RVE
‡ Report lists discrepancies on a cell-by-cell basis
‡ Report summarizes LVS execution time, memory
allocation and other run statistics
‡ LVS generates the report if Calibre executes to
completion
‡ User specifies report filename with a Rule file
statement

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CIC

Reading the LVS Transcript

‡ Appears in the shell where you invoked Calibre LVS
‡ Identifies:
‡ Individual phases of LVS execution:
z Compilation of the Rule file
z Translation and transformation of the source and layout cells
z Generation of the output files
‡ Execution statistics (like Calibre DRC)
‡ Connectivity extraction errors
‡ Warnings
z Texting problems
z Stamping errors
‡ Provides clues if LVS terminates before completion

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CIC

Invoking Calibre LVS

calibre [ -lvs ] [ -hier [ -automatch ]
[ -hcell cell_correspondence_file_name ]
[ -turbo [ no_of_cpus ] ] ]
[ -spice spice_file_name ]
rule_file_name

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CIC
Using Calibre LVS in a Flat
Configuration
‡Flattens the layout database; operates on resulting
flattened structure (same as Calibre DRC)
‡ Is most useful for layout with little repetition of
structure or with few levels of cell hierarchy
‡ Creates same type of Standard Verification Database
as Calibre LVS-H
‡ MASK SVDB DIRECTORY filename QUERY
z generates files for query server (RVE)
‡MASK SVDB DIRECTORY filename NOFLAT
z supresses SVDB generation for a flat run

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CIC
Invoking Calibre LVS in a Flat
Configuration
‡Example: calibre -lvs rule_file
RULE FILE
LAYOUT SYSTEM GDSII
LAYOUT PATH “/user/training/mydesign.gds”
LAYOUT PRIMARY lab5

SOURCE SYSTEM SPICE

SOURCE PATH “/user/training/mydesign.spi”
SOURCE PRIMARY lab5
MASK SVDB DIRECTORY svdb QUERY
//MASK RESULTS DATABASE lab5.db
LVS REPORT “lvs.rpt”

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CIC

Using Calibre LVS in a Hierarchical Configuration

‡Preserves hierarchical structure of design database

‡Reduces:
‡Processing time
‡Host memory usage
‡Discrepancy counts
‡Requires LVS-H license

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CIC

Choosing When to Use LVS Hierarchically

‡Beneficial for designs with repeated cells or re-used

logic
‡Memory designs
‡Gate arrays
‡Standard cells
‡System-on-chip
‡Data path
‡Beneficial for designs with the following chip profile:
‡Process geometry < 0.35
‡Transistor count > 1 million

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CIC
Invoking Calibre LVS-H in a
Comparison Configuration
‡Both layout and source are SPICE
‡ Example: calibre -lvs -hier -auto rule_file
RULE FILE
LAYOUT SYSTEM SPICE
LAYOUT PATH “/user/training/layout.spi”
LAYOUT PRIMARY lab5
SOURCE SYSTEM SPICE
SOURCE PATH “/user/training/circuit.spi”
SOURCE PRIMARY lab5
MASK SVDB DIRECTORY svdb QUERY
LVS REPORT “lvs.rpt”

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 CIC

Invoking Calibre LVS-H in an Extraction Configuration

‡ Requires the layout database format to be GDSII or CIF

‡ Requires the name of the output SPICE file on the
command line
‡ Use without the -lvs switch for a two-step LVS flow
Step 1: Circuit Extraction
Step 2: Circuit Comparison
Example:
calibre -spice layout.spi rule_file_A // extraction
calibre -lvs -hier -auto rule_file_B // comparison
‡ Use with the -lvs switch for a one-step LVS flow
Example (circuit extraction and comparison):
calibre -lvs -spice layout.spi -hier -auto rule_file_A

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 CIC

Using the -auto Switch to Specify Cell Correspondence

‡ Hierarchical analysis requires the identification of

corresponding cells between the source and layout
‡ LVS-H automatically matches cells in the source and layout
with the same name when invoked with the
-auto switch
Cell names are case insensitive
Top-level cells always correspond, regardless of names
‡ LVS-H expands unmatched cells to the next hierarchical
correspondence level nearer the top level

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 CIC

Using the -hcell Switch to Specify Cell Correspondence

‡ Enables correspondence when cell names differ between

source and layout
‡ All cells must correspond between source and layout for
you to take full advantage of LVS-H
‡ LVS-H flattens unmatched cells and promotes them up the
hierarchy (toward the top level)
‡ Requires the name of the cell correspondence file on the
command line
Example:
calibre -lvs -hier -hcell cell_file rule_file
‡ You may specify the -hcell switch in conjunction with the -
auto switch

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CIC
Creating the Hcell Correspondence
File
‡ Create the file with an ASCII editor
‡ Insert one cell per line in the form:
layout_name source_name
‡ Including the top-level cell is not necessary
‡ Specifying 1-to-n or n-to-1 correspondence is permissible
‡ Enter comments by starting a line with “//”
‡ Do not use trailing comments
‡ LVS-H treats cell names as case insensitive
‡ LVS-H issues a warning for cell names not found

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CIC
Example Hcell Correspondence
File RULE FILE
// HCELL FILE
// PROJECT NAME: mydesign
// LAYOUT CELL SOURCE CELL
a1220 NAND2_1
a1230 MUX2
a1240 NOR2_1
a1310 A1310
a1620 A1620
a1720 A1720
a2311 A2311
lab5 top_cell

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CIC

Calibre GUI vs Command Line

‡Calibre Graphical User Interface (GUI)
‡Invoke DRC/LVS/RVE from Calibre Invocation Palette
‡Can save run settings for future use
‡RVE & the DRC report can automatically open after the
run is complete
‡Command Line
‡Type in command at Unix prompt
‡Use VI or another text editor to the edit rule file
‡RVE & the DRC report do not automatically appear
after the run is complete and both still have to be invoked
from the command line.

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CIC
Using Calibre -- LVS (1)

virtuoso link virtuoso

Calibre 令

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 CIC
Using Calibre -- LVS (2)
Calibre LVS rule file view
rule file

run Calibre LVS 料

(output) data base
錄

LVS check Hierarchical Flat

Layout Source
netlist vs. netlist GDSII file
vs. source netlist

Layout file format GDS II

file layout database import
Calibre layout netlist
layout_cell_name.lay.net

setup -> option更

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CIC
Using Calibre -- LVS (3)

Source file format netlist Schematic

viewer import 利 Import source
netlist device model name layout不
match 行
Calibre source netlist
layout_cell_name.src.net

Run Cell
(Automatch) Hcell Table兩
不

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 CIC
Using Calibre -- LVS (4)

LVS report
layout_cell_name.lvs.report
run LVS report

立SVDB database run LVS

RVE來 error

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 CIC
Using Calibre -- LVS (5)
Run Calibre LVS option
64bit server 行
不

Transcript 錄Run LVS 若

利 行 利 Transcript
-> Save as log file

Run LVS 行Calibre LVS check

行 RVE

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CIC

Using Calibre -- LVS (6)

report
LVS check REV
Design Match

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CIC

Open Circuits
‡ An open circuit occurs when continuity is not maintained over the entire
length of a layout net
‡ Simple example:

Intended layout Actual layout

‡ During execution, Calibre extracts layout connectivity and forms it into a
layout netlist
‡ In above layout example, Calibre LVS would detect two nets
‡ During comparison with the source netlist, Calibre would find a difference
between the number of nets:
number of layout nets > number of source nets
‡ Intended layout Actual layout

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CIC

Identifying Open Circuits

‡ The following layout has an open circuit:

‡ You must do three tasks to verify this layout problem:

1. Set up and invoke Calibre LVS-H
2. Identify that an open exists by reading the LVS Report file
3. Locate the open in the layout by using the Calibre RVE utility

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CIC

Open Circuits Example (1)

說 layout 16 nets source

15 layout open

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CIC

Open Circuits Example (2)

利 RVE click error net Layout

Viewer (Virtuoso) error
highlight

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CIC

Short Circuits
‡ A short circuit occurs when two nets that should beisolated
from each other are connected together
‡ Simple example:

Intended layout Actual layout

‡ In this example, Calibre would detect one net instead of two
‡ During comparison with the source netlist, Calibre would
find a difference between the number of nets:
number of layout nets < number of source nets

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Identifying Short Circuits

‡ The following layout has a short circuit:

‡ You must do three tasks to verify this layout problem:

1. Set up and invoke Calibre LVS-H
2. Identify that a short exists by reading the LVS Report file
3. Locate the short in the layout by using the Calibre RVE utility

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CIC

Short Circuits Example (1)

說 layout 14 nets source

15 layout Short

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CIC

Short Circuits Example (2)

Source netlist

net 連 Cell
路
Layout netlist

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Short Circuits Example (3)

Cell
路

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Combined Short and Open Circuit

‡ One layout error can cause both a short and an open circuit
‡ Simple example:

Intended layout Actual layout

‡ In this example, Calibre would see the same number of nets in both the
layout and the source:
number of layout nets = number of source nets
‡ Invoke LVS-H as before
‡ Intended layout Actual layout

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CIC

Combined Short and Open Example (1)

net 列

Open Short net

數 不

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Combined Short and Open Example (2)

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Combined Short and Open Example (3)

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Pin Swapping
‡ Occurs when the pin connection order of a primitive is different between
source and layout netlists
‡ Is allowable when pins of a device or gate primitive are designated as
logically equivalent
‡ Facilitates routing
‡ Pin Swapping example:
A
B
C

E F

Pins A, B and C are swappable gate pins.

Pins E and F are swappable device pins.

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CIC
Avoiding False Pin Swap
Discrepancies in LVS
‡Use the Rule File to designate swappable pins:
‡Add pin names to a <pin-swap> list in a DEVICE
statement
‡List pins on a single layer in a DEVICE statement
‡Add the LVS RECOGNIZE GATES specification
‡Note that pins swappable by default include:
‡Device pins with identical names
‡Source and Drain pins of MOS regular transistors
‡Capacitor pins, unless Rule file contains the specification:
LVS ALL CAPACITOR PINS SWAPPABLE NO
‡Resistor pins

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Verification--Calibre
‡Concept
‡Design Rule check
‡Layout vs. Schematic
‡Parasitic Extraction using XCalibre

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PEX
‡ 料 路 便 行post-layout
路
‡
‡ LPE SPICE DSPF(Detailed Standard
Parasitic Format) RSPF(Reduced Standard Parasitic
Format)(for HPRE only)
‡ Command file Extraction 度

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CIC
Post-Layout Simulation(1)
• The netlist of SPICE/CDL format that includes
parasitic element can be obtained after the
Dracula LPE/PRE. It can be used for post
simulation by circuit simulator, such as
SPICE or TimeMill,PowerMill and PathMill.
• Add simulation control and input stimulus for
final simulation (Post-layout simulation)

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CIC
Post-Layout Simulation(2)
• Post-layout simulation, 路
interconnect parasitics 度
• Signal Coupling Post-layout
simulation 來
• Power/Ground bounce 度
extracting power/ground line parasitics 來

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CIC

Process Flow for Calibre PEX

Spice netlist Completed
Rule File
(optional) Layout

CALIBRE PEX

Extracted
Report File
Netlist

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What are Parasites?

‡ Parasitics are resistance and capacitance not intentionally design into a chip,
but are consequences of the layout
‡ xCalibre/Calibre XRC extract calaulates resistance and capacitance values
for nets modeled as interconnect layers. These consist of:
‡ Conduction layers carrying current on their own layer
‡ Conduction layers carrying current on their between layer
‡ Nets are made from interconnect layer providing electrical current paths
between pins of devices.

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Type of Parasites
‡ Capacitance:
‡A change developed between conductors which opposes
changes in voltage
‡ Resistance:
‡A restriction to flow of current through a conductor
‡ Inductance :
‡A change developed in the magnetic field around a
conductor which opposes change in current

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Parasitics Capacitance
metal
‡Intrinsic

Substrate

‡Coupled
metal metal

metal

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Parasites Resistance
‡Conductor path (squares)

‡Interconnect (contact/via )

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Model Parasites
‡ Lumped Capacitance

C total
‡ Distributed Resistance/Capacitance

Intrinsic or
coupled
‡ Distributed Resistance/Coupled Capacitance

coupled

Intrinsic

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Correct Intentional Device Extraction

‡ Transistor, Resistance, Capacitance, Inductors, Varactors
‡ User-Defined Device
‡ Parameter Extraction
‡ W, L, AS, AD, PD, PS,NRS,NRD
‡ User Defined Parameter
‡ Device Reduction
‡ User Defined Parameter Reduction
‡ Accurately extract intentional devices in the circuit

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General Rule File Requirement

‡ Required input/output specifications
‡ Layout Path, Layout Primary, Layout System
‡ Source Path, Source Primary, Source System
‡ Layer, Layer Directory
‡ Variable
‡ PEX option statements
‡ PEX Back annotation Distributed/Lumped/Simple
‡ PEX Netlist Distributed/Lumped/Simple
‡ PEX Report Distributed/Lumped
‡ PEX FDB or PEX FDB Global
‡ Standard connectivity, device and parasites extraction statements
‡ Rule file statements
‡ Mask SVDB DIRECTORY dir_name [xCalibre|XRC][QUERY]
‡ PEX FDB Global ALL EXCLUDE LAYOUT VDD VSS
‡ Capacitance Order/Unit Capacitance.. etc

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Running Calibre PEX(1)

virtuoso link
virtuoso Calibre

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Running Calibre PEX(2)

Calibre PEX rule file view
rule file

run Calibre PEX 料

(output) data base
錄

PEX check Hierarchical Flat

layout file(GDSII) Import

layout view 若
layout Database 行
layout file

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Running Calibre PEX(3)

Source file format netlist Schematic
viewer import 利 Import source
netlist device model name layout不
match 行
Calibre source netlist
layout_cell_name.src.net
setup -> option更

Run Cell
(Automatch) Hcell Table兩
不

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Running Calibre PEX(4)

Device Name Report

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Running Calibre PEX(5)

Lumped Capacitance

立SVDB 料
( RVE讀 ) RVE

SVDB
料 錄

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References
• H.B. Bakoglu “Circuits, Interconnections, and packaging for VLSI”
• John P. Uyemura, “Introduction to VLSI circuits and systems”
• M. Michael Vai, “VLSI design”
• Y. Taur, and T. H. Ning “Fundamentals of Modern VLSI Devices”
• R. L. Geiger, P. E. Allen, and N. R. Strader: “VLSI Design Techniques for
Analog and Digital Circuits”
• “CCL TECHNICAL JOURNAL”(42 )pp.10~24
• Foundry Design Documents
• “RF CMOS IC Design Flow” training manual of CIC, 2002
• “Using Calibre Student Workbook” training manual of Mentor, 2003
• “xCalibre/Calibre XRC training” training manual of Mentor, 2003

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