M50FW040

4 Mbit (512Kb x8, Uniform Block)

3V Supply Firmware Hub Flash Memory

FEATURES SUMMARY
■ SUPPLY VOLTAGE Figure 1. Packages
– VCC = 3V to 3.6V for Program, Erase and
Read Operations
– VPP = 12V for Fast Erase (optional)
■ TWO INTERFACES
– Firmware Hub (FWH) Interface for
embedded operation with PC Chipsets.
– Address/Address Multiplexed (A/A Mux)
Interface for programming equipment PLCC32 (K)
compatibility.
■ FIRMWARE HUB (FWH) HARDWARE
INTERFACE MODE
– 5 Signal Communication Interface
supporting Read and Write Operations
– Hardware Write Protect Pins for Block
Protection
– Register Based Read and Write
Protection
– 5 Additional General Purpose Inputs for
platform design flexibility
TSOP32 (NB)
– Synchronized with 33MHz PCI clock
8 x 14mm
■ PROGRAMMING TIME: 10µs typical
■ 8 UNIFORM 64 Kbyte MEMORY BLOCKS
■ PROGRAM/ERASE CONTROLLER
– Embedded Byte Program and Block
Erase algorithms
– Status Register Bits
■ PROGRAM and ERASE SUSPEND
– Read other Blocks during Program/Erase
Suspend
– Program other Blocks during Erase
Suspend TSOP40 (N)
■ FOR USE in PC BIOS APPLICATIONS 10 x 20mm

■ ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: 2Ch

November 2004 1/41

M50FW040

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Logic Diagram (FWH Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 1. Signal Names (FWH Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Logic Diagram (A/A Mux Interface). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Signal Names (A/A Mux Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. PLCC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. TSOP32 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 6. TSOP40 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Firmware Hub (FWH) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Input/Output Communications (FWH0-FWH3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Input Communication Frame (FWH4).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Identification Inputs (ID0-ID3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
General Purpose Inputs (FGPI0-FGPI4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Interface Configuration (IC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Interface Reset (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
CPU Reset (INIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Clock (CLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Top Block Lock (TBL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Reserved for Future Use (RFU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Address/Address Multiplexed (A/A Mux) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 10
Address Inputs (A0-A10). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Row/Column Address Select (RC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Supply Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
VPP Optional Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Firmware Hub (FWH) Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bus Abort. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

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Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Address/Address Multiplexed (A/A Mux) Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4. FWH Bus Read Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. FWH Bus Read Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 5. FWH Bus Write Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 8. FWH Bus Write Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Read Memory Array Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Read Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Clear Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 6. Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 7. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Program Status (Bit 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
VPP Status (Bit 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Block Protection Status (Bit 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Reserved (Bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 8. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

FIRMWARE HUB (FWH) INTERFACE CONFIGURATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . 19

Lock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Write Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Read Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Lock Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Firmware Hub (FWH) General Purpose Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Manufacturer Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Device Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Firmware Hub (FWH) General Purpose Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Manufacturer Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

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Device Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 9. Firmware Hub Register Configuration Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 10. Lock Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 11. General Purpose Inputs Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

PROGRAM AND ERASE TIMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 12. Program and Erase Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 13. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 14. Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 15. FWH Interface AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 16. A/A Mux Interface AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 9. FWH Interface AC Testing Input Output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 10.A/A Mux Interface AC Testing Input Output Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 17. Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 18. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 11.FWH Interface Clock Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 19. FWH Interface Clock Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 12.FWH Interface AC Signal Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 20. FWH Interface AC Signal Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 13.Reset AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 21. Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 14.A/A Mux Interface Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 22. A/A Mux Interface Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 15.A/A Mux Interface Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 23. A/A Mux Interface Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 16.PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Outline . . . . . . . . 31
Table 24. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Mechanical Data 32
Figure 17.TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Outline . . . . . . . . . . 33
Table 25. TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Mechanical Data. . . 33
Figure 18.TSOP40 – 40 lead Plastic Thin Small Outline, 10x20 mm, Package Outline . . . . . . . . . 34
Table 26. TSOP40 – 40 lead Plastic Thin Small Outline, 10x20 mm, Package Mechanical Data. . 34

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 27. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

FLOWCHARTS AND PSEUDO CODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 19.Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 20.Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 37
Figure 21.Erase Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

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Figure 22.Erase Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . 39

REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 28. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

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SUMMARY DESCRIPTION
The M50FW040 is a 4 Mbit (512Kb x8) non-vola- and any error conditions identified. The command
tile memory that can be read, erased and repro- set required to control the memory is consistent
grammed. These operations can be performed with JEDEC standards.
using a single low voltage (3.0 to 3.6V) supply. For Two different bus interfaces are supported by the
fast erasing in production lines an optional 12V memory. The primary interface, the Firmware Hub
power supply can be used to reduce the erasing (or FWH) Interface, uses Intel’s proprietary FWH
time. protocol. This has been designed to remove the
The memory is divided into blocks that can be need for the ISA bus in current PC Chipsets; the
erased independently so it is possible to preserve M50FW040 acts as the PC BIOS on the Low Pin
valid data while old data is erased. Blocks can be Count bus for these PC Chipsets.
protected individually to prevent accidental Pro- The secondary interface, the Address/Address
gram or Erase commands from modifying the Multiplexed (or A/A Mux) Interface, is designed to
memory. Program and Erase commands are writ- be compatible with current Flash Programmers for
ten to the Command Interface of the memory. An production line programming prior to fitting to a PC
on-chip Program/Erase Controller simplifies the Motherboard.
process of programming or erasing the memory by
taking care of all of the special operations that are The memory is offered in TSOP32 (8 x 14mm),
TSOP40 (10 x 20mm) and PLCC32 packages and
required to update the memory contents. The end
of a program or erase operation can be detected it is supplied with all the bits erased (set to ’1’).

Figure 2. Logic Diagram (FWH Interface) Table 1. Signal Names (FWH Interface)
FWH0-FWH3 Input/Output Communications
VCC VPP FWH4 Input Communication Frame
ID0-ID3 Identification Inputs
4 4 FGPI0-FGPI4 General Purpose Inputs
FWH0-
ID0-ID3 FWH3 IC Interface Configuration
5 RP Interface Reset
FGPI0-
FGPI4 WP INIT CPU Reset
CLK Clock
FWH4 M50FW040 TBL
TBL Top Block Lock
CLK WP Write Protect
IC Reserved for Future Use. Leave
RFU
disconnected
RP
VCC Supply Voltage
INIT
Optional Supply Voltage for Fast
VPP
Erase Operations
VSS Ground
VSS
AI03623 NC Not Connected Internally

6/41
 M50FW040

Figure 3. Logic Diagram (A/A Mux Interface) Table 2. Signal Names (A/A Mux Interface)
IC Interface Configuration
A0-A10 Address Inputs
VCC VPP
DQ0-DQ7 Data Inputs/Outputs
G Output Enable
11 8
W Write Enable
A0-A10 DQ0-DQ7
RC Row/Column Address Select
RB Ready/Busy Output
RC RP Interface Reset
M50FW040
IC RB VCC Supply Voltage

G Optional Supply Voltage for Fast

VPP
Program and Erase Operations
W
VSS Ground
RP
NC Not Connected Internally

VSS
AI10719

Figure 4. PLCC Connections

VCC
VPP

A10
RC

A/A Mux A/A Mux

RP
A8
A9
FGPI2
FGPI3

FGPI4
VCC
VPP

CLK
RP

1 32
A7 FGPI1 IC (VIL) IC (VIH)
A6 FGPI0 NC NC
A5 WP NC NC
A4 TBL VSS VSS
A3 ID3 9 M50FW040 25 VCC VCC
A2 ID2 INIT G
A1 ID1 FWH4 W
A0 ID0 RFU RB
DQ0 FWH0 RFU DQ7
17
FWH1
FWH2
VSS
FWH3
RFU
RFU
RFU
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6

A/A Mux A/A Mux

AI03616

Note: Pins 27 and 28 are not internally connected.

7/41
M50FW040

Figure 5. TSOP32 Connections

NC NC 1 32 INIT G
NC NC FWH4/LFRAME W
NC NC NC NC
NC VSS RFU DQ7
IC (VIH) IC RFU DQ6
A10 GPI4 RFU DQ5
RC CLK RFU DQ4
A/A Mux

A/A Mux
VCC VCC 8 M50FW040 25 FWH3/LAD3 DQ3
VPP VPP 9 24 VSS VSS
RP RP FWH2/LAD2 DQ2
A9 GPI3 FWH1/LAD1 DQ1
A8 GPI2 FWH0/LAD0 DQ0
A7 GPI1 ID0 A0
A6 GPI0 ID1 A1
A5 WP ID2 A2
A4 TBL 16 17 ID3/RFU A3

AI10718

1. the RB pin is not available for the A/A Mux interface in the TSOP32 package.

Figure 6. TSOP40 Connections

NC NC 1 40 VSS VSS
IC (VIH) IC (VIL) VCC VCC
NC NC FWH4 W
NC NC INIT G
NC NC RFU RB
NC NC RFU DQ7
A10 FGPI4 RFU DQ6
NC NC RFU DQ5
RC CLK RFU DQ4
A/A Mux

A/A Mux

VCC VCC 10 31 VCC VCC

M50FW040
VPP VPP 11 30 VSS VSS
RP RP VSS VSS
NC NC FWH3 DQ3
NC NC FWH2 DQ2
A9 FGPI3 FWH1 DQ1
A8 FGPI2 FWH0 DQ0
A7 FGPI1 ID0 A0
A6 FGPI0 ID1 A1
A5 WP ID2 A2
A4 TBL 20 21 ID3 A3
AI03617

8/41
 M50FW040

SIGNAL DESCRIPTIONS
There are two different bus interfaces available on the Interface Configuration, IC, should not be
this part. The active interface is selected before changed during operation.
power-up or during Reset using the Interface Con- To select the Firmware Hub (FWH) Interface the
figuration Pin, IC. Interface Configuration pin should be left to float or
The signals for each interface are discussed in the driven Low, VIL; to select the Address/Address
Firmware Hub (FWH) Signal Descriptions section Multiplexed (A/A Mux) Interface the pin should be
and the Address/Address Multiplexed (A/A Mux) driven High, VIH. An internal pull-down resistor is
Signal Descriptions section below. The supply sig- included with a value of RIL; there will be a leakage
nals are discussed in the Supply Signal Descrip- current of ILI2 through each pin when pulled to VIH;
tions section below. see Table 18.
Firmware Hub (FWH) Signal Descriptions Interface Reset (RP). The Interface Reset (RP)
For the Firmware Hub (FWH) Interface see Figure input is used to reset the memory. When Interface
2., Logic Diagram (FWH Interface), and Table Reset (RP) is set Low, VIL, the memory is in Reset
1., Signal Names (FWH Interface). mode: the outputs are put to high impedance and
the current consumption is minimized. When RP is
Input/Output Communications (FWH0-FWH3). All set High, VIH, the memory is in normal operation.
Input and Output Communication with the memory
After exiting Reset mode, the memory enters
take place on these pins. Addresses and Data for Read mode.
Bus Read and Bus Write operations are encoded
on these pins. CPU Reset (INIT). The CPU Reset, INIT, pin is
used to Reset the memory when the CPU is reset.
Input Communication Frame (FWH4). The In-
It behaves identically to Interface Reset, RP, and
put Communication Frame (FWH4) signals the the internal Reset line is the logical OR (electrical
start of a bus operation. When Input Communica-
AND) of RP and INIT.
tion Frame is Low, VIL, on the rising edge of the
Clock a new bus operation is initiated. If Input Clock (CLK). The Clock, CLK, input is used to
Communication Frame is Low, VIL, during a bus clock the signals in and out of the Input/Output
operation then the operation is aborted. When In- Communication Pins, FWH0-FWH3. The Clock
put Communication Frame is High, VIH, the cur- conforms to the PCI specification.
rent bus operation is proceeding or the bus is idle. Top Block Lock (TBL). The Top Block Lock in-
Identification Inputs (ID0-ID3). The Identifica- put is used to prevent the Top Block (Block 7) from
tion Inputs select the address that the memory re- being changed. When Top Block Lock, TBL, is set
sponds to. Up to 16 memories can be addressed Low, VIL, Program and Erase operations in the
on a bus. For an address bit to be ‘0’ the pin can Top Block have no effect, regardless of the state
be left floating or driven Low, VIL; an internal pull- of the Lock Register. When Top Block Lock, TBL,
down resistor is included with a value of RIL. For is set High, VIH, the protection of the Block is de-
an address bit to be ‘1’ the pin must be driven termined by the Lock Register. The state of Top
High, VIH; there will be a leakage current of ILI2 Block Lock, TBL, does not affect the protection of
through each pin when pulled to VIH; see Table 18. the Main Blocks (Blocks 0 to 6).
By convention the boot memory must have ad- Top Block Lock, TBL, must be set prior to a Pro-
dress ‘0000’ and all additional memories take se- gram or Erase operation is initiated and must not
quential addresses starting from ‘0001’. be changed until the operation completes or un-
predictable results may occur. Care should be tak-
General Purpose Inputs (FGPI0-FGPI4). The Gen- en to avoid unpredictable behavior by changing
eral Purpose Inputs can be used as digital inputs TBL during Program or Erase Suspend.
for the CPU to read. The General Purpose Inputs
Register holds the values on these pins. The pins Write Protect (WP). The Write Protect input is
must have stable data from before the start of the used to prevent the Main Blocks (Blocks 0 to 6)
cycle that reads the General Purpose Input Regis- from being changed. When Write Protect, WP, is
ter until after the cycle is complete. These pins set Low, VIL, Program and Erase operations in the
must not be left to float, they should be driven Low, Main Blocks have no effect, regardless of the state
VIL, or High, VIH. of the Lock Register. When Write Protect, WP, is
set High, VIH, the protection of the Block deter-
Interface Configuration (IC). The Interface Con- mined by the Lock Register. The state of Write
figuration input selects whether the Firmware Hub Protect, WP, does not affect the protection of the
(FWH) or the Address/Address Multiplexed (A/A Top Block (Block 7).
Mux) Interface is used. The chosen interface must
be selected before power-up or during a Reset Write Protect, WP, must be set prior to a Program
and, thereafter, cannot be changed. The state of or Erase operation is initiated and must not be
changed until the operation completes or unpre-

9/41
M50FW040

dictable results may occur. Care should be taken VCC Supply Voltage. The VCC Supply Voltage
to avoid unpredictable behavior by changing WP supplies the power for all operations (Read, Pro-
during Program or Erase Suspend. gram, Erase etc.).
Reserved for Future Use (RFU). These pins do The Command Interface is disabled when the VCC
not have assigned functions in this revision of the Supply Voltage is less than the Lockout Voltage,
part. They must be left disconnected. VLKO. This prevents Bus Write operations from ac-
Address/Address Multiplexed (A/A Mux) cidentally damaging the data during power up,
Signal Descriptions power down and power surges. If the Program/
Erase Controller is programming or erasing during
For the Address/Address Multiplexed (A/A Mux) this time then the operation aborts and the memo-
Interface see Figure 2., Logic Diagram (FWH In- ry contents being altered will be invalid. After VCC
terface), and Table 1., Signal Names (FWH Inter-
becomes valid the Command Interface is reset to
face). Read mode.
Address Inputs (A0-A10). The Address Inputs A 0.1µF capacitor should be connected between
are used to set the Row Address bits (A0-A10) and the VCC Supply Voltage pins and the VSS Ground
the Column Address bits (A11-A18). They are pin to decouple the current surges from the power
latched during any bus operation by the Row/Col- supply. Both VCC Supply Voltage pins must be
umn Address Select input, RC. connected to the power supply. The PCB track
Data Inputs/Outputs (DQ0-DQ7). The Data In- widths must be sufficient to carry the currents re-
puts/Outputs hold the data that is written to or read quired during program and erase operations.
from the memory. They output the data stored at
VPP Optional Supply Voltage. The VPP Optional
the selected address during a Bus Read opera- Supply Voltage pin is used to select the Fast Erase
tion. During Bus Write operations they represent
option of the memory and to protect the memory.
the commands sent to the Command Interface of When VPP < VPPLK Program and Erase operations
the internal state machine. The Data Inputs/Out- cannot be performed and an error is reported in
puts, DQ0-DQ7, are latched during a Bus Write the Status Register if an attempt to change the
operation. memory contents is made. When VPP = VCC Pro-
Output Enable (G). The Output Enable, G, con- gram and Erase operations take place as normal.
trols the Bus Read operation of the memory. When VPP = VPPH Fast Erase operations are
Write Enable (W). The Write Enable, W, controls used. Any other voltage input to VPP will result in
the Bus Write operation of the memory’s Com- undefined behavior and should not be used.
mand Interface. VPP should not be set to VPPH for more than 80
Row/Column Address Select (RC). The Row/ hours during the life of the memory.
Column Address Select input selects whether the VSS Ground. VSS is the reference for all the volt-
Address Inputs should be latched into the Row Ad- age measurements.
dress bits (A0-A10) or the Column Address bits
(A11-A18). The Row Address bits are latched on
the falling edge of RC whereas the Column Ad- Table 3. Block Addresses
dress bits are latched on the rising edge. Size
Address Range
Block
Block Type
Ready/Busy Output (RB). The Ready/Busy pin (Kbytes) Number
gives the status of the memory’s Program/Erase 64 70000h-7FFFFh 7 Top Block
Controller. When Ready/Busy is Low, VOL, the
64 60000h-6FFFFh 6 Main Block
memory is busy with a Program or Erase operation
and it will not accept any additional Program or 64 50000h-5FFFFh 5 Main Block
Erase command except the Program/Erase Sus-
64 40000h-4FFFFh 4 Main Block
pend command. When Ready/Busy is High, VOH,
the memory is ready for any Read, Program or 64 30000h-3FFFFh 3 Main Block
Erase operation. 64 20000h-2FFFFh 2 Main Block
Supply Signal Descriptions
64 10000h-1FFFFh 1 Main Block
The Supply Signals are the same for both interfac-
es. 64 00000h-0FFFFh 0 Main Block

10/41
 M50FW040

BUS OPERATIONS
The two interfaces have similar bus operations but FWH3. The memory outputs Sync data until the
the signals and timings are completely different. wait-states have elapsed.
The Firmware Hub (FWH) Interface is the usual in- Refer to Table 5., FWH Bus Write Field Defini-
terface and all of the functionality of the part is tions, and Figure 8., FWH Bus Write Waveforms,
available through this interface. Only a subset of for a description of the Field definitions for each
functions are available through the Address/Ad- clock cycle of the transfer. See Table 20., FWH In-
dress Multiplexed (A/A Mux) Interface. terface AC Signal Timing Characteristics, and Fig-
Follow the section Firmware Hub (FWH) Bus Op- ure 12., FWH Interface AC Signal Timing
erations below and the section Address/Address Waveforms, for details on the timings of the sig-
Multiplexed (A/A Mux) Bus Operations below for a nals.
description of the bus operations on each inter- Bus Abort. The Bus Abort operation can be used
face. to immediately abort the current bus operation. A
Firmware Hub (FWH) Bus Operations Bus Abort occurs when FWH4 is driven Low, VIL,
The Firmware Hub (FWH) Interface consists of during the bus operation; the memory will tri-state
four data signals (FWH0-FWH3), one control line the Input/Output Communication pins, FWH0-
(FWH4) and a clock (CLK). In addition protection FWH3.
against accidental or malicious data corruption Note that, during a Bus Write operation, the Com-
can be achieved using two further signals (TBL mand Interface starts executing the command as
and WP). Finally two reset signals (RP and INIT) soon as the data is fully received; a Bus Abort dur-
are available to put the memory into a known ing the final TAR cycles is not guaranteed to abort
state. the command; the bus, however, will be released
The data signals, control signal and clock are de- immediately.
signed to be compatible with PCI electrical specifi- Standby. When FWH4 is High, VIH, the memory
cations. The interface operates with clock speeds is put into Standby mode where FWH0-FWH3 are
up to 33MHz. put into a high-impedance state and the Supply
The following operations can be performed using Current is reduced to the Standby level, ICC1.
the appropriate bus cycles: Bus Read, Bus Write, Reset. During Reset mode all internal circuits are
Standby, Reset and Block Protection. switched off, the memory is deselected and the
Bus Read. Bus Read operations read from the outputs are put in high-impedance. The memory is
memory cells, specific registers in the Command in Reset mode when Interface Reset, RP, or CPU
Interface or Firmware Hub Registers. A valid Bus Reset, INIT, is Low, VIL. RP or INIT must be held
Read operation starts when Input Communication Low, VIL, for tPLPH. The memory resets to Read
Frame, FWH4, is Low, VIL, as Clock rises and the mode upon return from Reset mode and the Lock
correct Start cycle is on FWH0-FWH3. On the fol- Registers return to their default states regardless
lowing clock cycles the Host will send the Memory of their state before Reset, see Table 10. If RP or
ID Select, Address and other control bits on INIT goes Low, VIL, during a Program or Erase op-
FWH0-FWH3. The memory responds by output- eration, the operation is aborted and the memory
ting Sync data until the wait-states have elapsed cells affected no longer contain valid data; the
followed by Data0-Data3 and Data4-Data7. memory can take up to tPLRH to abort a Program
or Erase operation.
Refer to Table 4., FWH Bus Read Field Defini-
tions, and Figure 7., FWH Bus Read Waveforms, Block Protection. Block Protection can be
for a description of the Field definitions for each forced using the signals Top Block Lock, TBL, and
clock cycle of the transfer. See Table 20., FWH In- Write Protect, WP, regardless of the state of the
terface AC Signal Timing Characteristics, and Fig- Lock Registers.
ure 12., FWH Interface AC Signal Timing Address/Address Multiplexed (A/A Mux) Bus
Waveforms, for details on the timings of the sig- Operations
nals. The Address/Address Multiplexed (A/A Mux) Inter-
Bus Write. Bus Write operations write to the face has a more traditional style interface. The sig-
Command Interface or Firmware Hub Registers. A nals consist of a multiplexed address signals (A0-
valid Bus Write operation starts when Input Com- A10), data signals, (DQ0-DQ7) and three control
munication Frame, FWH4, is Low, VIL, as Clock signals (RC, G, W). An additional signal, RP, can
rises and the correct Start cycle is on FWH0- be used to reset the memory.
FWH3. On the following Clock cycles the Host will The Address/Address Multiplexed (A/A Mux) Inter-
send the Memory ID Select, Address, other control face is included for use by Flash Programming
bits, Data0-Data3 and Data4-Data7 on FWH0- equipment for faster factory programming. Only a

11/41
M50FW040

subset of the features available to the Firmware Bus Write. Bus Write operations write to the
Hub (FWH) Interface are available; these include Command Interface. A valid Bus Write operation
all the Commands but exclude the Security fea- begins by latching the Row Address and Column
tures and other registers. Address signals into the memory using the Ad-
The following operations can be performed using dress Inputs, A0-A10, and the Row/Column Ad-
the appropriate bus cycles: Bus Read, Bus Write, dress Select RC. The data should be set up on the
Output Disable and Reset. Data Inputs/Outputs; Output Enable, G, and Inter-
face Reset, RP, must be High, VIH and Write En-
When the Address/Address Multiplexed (A/A Mux) able, W, must be Low, VIL. The Data Inputs/
Interface is selected all the blocks are unprotect- Outputs are latched on the rising edge of Write En-
ed. It is not possible to protect any blocks through able, W. See Figure 15., A/A Mux Interface Write
this interface. AC Waveforms, and Table 23., A/A Mux Interface
Bus Read. Bus Read operations are used to out- Write AC Characteristics, for details of the timing
put the contents of the Memory Array, the Elec- requirements.
tronic Signature and the Status Register. A valid Output Disable. The data outputs are high-im-
Bus Read operation begins by latching the Row
pedance when the Output Enable, G, is at VIH.
Address and Column Address signals into the
memory using the Address Inputs, A0-A10, and Reset. During Reset mode all internal circuits are
the Row/Column Address Select RC. Then Write switched off, the memory is deselected and the
Enable (W) and Interface Reset (RP) must be outputs are put in high-impedance. The memory is
High, VIH, and Output Enable, G, Low, VIL, in order in Reset mode when RP is Low, VIL. RP must be
to perform a Bus Read operation. The Data Inputs/ held Low, VIL for tPLPH. If RP is goes Low, VIL, dur-
Outputs will output the value, see Figure 14., A/A ing a Program or Erase operation, the operation is
Mux Interface Read AC Waveforms, and Table aborted and the memory cells affected no longer
22., A/A Mux Interface Read AC Characteristics, contain valid data; the memory can take up to tPL-
for details of when the output becomes valid. RH to abort a Program or Erase operation.

Table 4. FWH Bus Read Field Definitions

Clock Clock
FWH0- Memory
Cycle Cycle Field Description
FWH3 I/O
Number Count
On the rising edge of CLK with FWH4 Low, the contents of FWH0-
1 1 START 1101b I
FWH3 indicate the start of a FWH Read cycle.
Indicates which FWH Flash Memory is selected. The value on FWH0-
2 1 IDSEL XXXX I FWH3 is compared to the IDSEL strapping on the FWH Flash
Memory pins to select which FWH Flash Memory is being addressed.
A 28-bit address phase is transferred starting with the most significant
3-9 7 ADDR XXXX I
nibble first.
10 1 MSIZE 0000b I Always 0000b (only single byte transfers are supported).
11 1 TAR 1111b I The host drives FWH0-FWH3 to 1111b to indicate a turnaround cycle.
1111b The FWH Flash Memory takes control of FWH0-FWH3 during this
12 1 TAR O
(float) cycle.
The FWH Flash Memory drives FWH0-FWH3 to 0101b (short wait-
13-14 2 WSYNC 0101b O sync) for two clock cycles, indicating that the data is not yet available.
Two wait-states are always included.
The FWH Flash Memory drives FWH0-FWH3 to 0000b, indicating
15 1 RSYNC 0000b O
that data will be available during the next clock cycle.
Data transfer is two CLK cycles, starting with the least significant
16-17 2 DATA XXXX O
nibble.
The FWH Flash Memory drives FWH0-FWH3 to 1111b to indicate a
18 1 TAR 1111b O
turnaround cycle.
1111b The FWH Flash Memory floats its outputs, the host takes control of
19 1 TAR N/A
(float) FWH0-FWH3.

12/41
 M50FW040

Figure 7. FWH Bus Read Waveforms

CLK

FWH4

FWH0-FWH3 START IDSEL ADDR MSIZE TAR SYNC DATA TAR

Number of
1 1 7 1 2 3 2 2
clock cycles

AI03437

Table 5. FWH Bus Write Field Definitions

Clock Clock
FWH0- Memory
Cycle Cycle Field Description
FWH3 I/O
Number Count
On the rising edge of CLK with FWH4 Low, the contents of
1 1 START 1110b I
FWH0-FWH3 indicate the start of a FWH Write Cycle.
Indicates which FWH Flash Memory is selected. The value
on FWH0-FWH3 is compared to the IDSEL strapping on the
2 1 IDSEL XXXX I
FWH Flash Memory pins to select which FWH Flash
Memory is being addressed.
A 28-bit address phase is transferred starting with the most
3-9 7 ADDR XXXX I
significant nibble first.
10 1 MSIZE 0000b I Always 0000b (single byte transfer).
Data transfer is two cycles, starting with the least significant
11-12 2 DATA XXXX I
nibble.
The host drives FWH0-FWH3 to 1111b to indicate a
13 1 TAR 1111b I
turnaround cycle.
1111b The FWH Flash Memory takes control of FWH0-FWH3
14 1 TAR O
(float) during this cycle.
The FWH Flash Memory drives FWH0-FWH3 to 0000b,
15 1 SYNC 0000b O
indicating it has received data or a command.
The FWH Flash Memory drives FWH0-FWH3 to 1111b,
16 1 TAR 1111b O
indicating a turnaround cycle.
1111b The FWH Flash Memory floats its outputs and the host takes
17 1 TAR N/A
(float) control of FWH0-FWH3.

Figure 8. FWH Bus Write Waveforms

CLK

FWH4

FWH0-FWH3 START IDSEL ADDR MSIZE DATA TAR SYNC TAR

Number of
1 1 7 1 2 2 1 2
clock cycles

AI03441

13/41
M50FW040

COMMAND INTERFACE
All Bus Write operations to the memory are inter- If the address falls in a protected block then the
preted by the Command Interface. Commands Program operation will abort, the data in the mem-
consist of one or more sequential Bus Write oper- ory array will not be changed and the Status Reg-
ations. ister will output the error.
After power-up or a Reset operation the memory During the Program operation the memory will
enters Read mode. only accept the Read Status Register command
The commands are summarized in Table and the Program/Erase Suspend command. All
7., Commands. Refer to Table 7. in conjunction other commands will be ignored. Typical Program
with the text descriptions below. times are given in Table 12.
Read Memory Array Command. The Read Mem- Note that the Program command cannot change a
ory Array command returns the memory to its bit set at ‘0’ back to ‘1’ and attempting to do so will
Read mode where it behaves like a ROM or not cause any modification on its value. The Erase
EPROM. One Bus Write cycle is required to issue command must be used to set all of the bits in the
the Read Memory Array command and return the block to ‘1’.
memory to Read mode. Once the command is is- See Figure 19., Program Flowchart and Pseudo
sued the memory remains in Read mode until an- Code, for a suggested flowchart on using the Pro-
other command is issued. From Read mode Bus gram command.
Read operations will access the memory array. Erase Command. The Erase command can be
While the Program/Erase Controller is executing a used to erase a block. Two Bus Write operations
Program or Erase operation the memory will not are required to issue the command; the second
accept the Read Memory Array command until the Bus Write cycle latches the block address in the in-
operation completes. ternal state machine and starts the Program/Erase
Read Status Register Command. The Read Sta- Controller. Once the command is issued subse-
tus Register command is used to read the Status quent Bus Read operations read the Status Reg-
Register. One Bus Write cycle is required to issue ister. See the section on the Status Register for
the Read Status Register command. Once the details on the definitions of the Status Register
command is issued subsequent Bus Read opera- bits.
tions read the Status Register until another com- If the block is protected then the Erase operation
mand is issued. See the section on the Status will abort, the data in the block will not be changed
Register for details on the definitions of the Status and the Status Register will output the error.
Register bits. During the Erase operation the memory will only
Read Electronic Signature Command. The Read accept the Read Status Register command and
Electronic Signature command is used to read the the Program/Erase Suspend command. All other
Manufacturer Code and the Device Code. One commands will be ignored. Typical Erase times
Bus Write cycle is required to issue the Read Elec- are given in Table 12.
tronic Signature command. Once the command is The Erase command sets all of the bits in the block
issued subsequent Bus Read operations read the to ‘1’. All previous data in the block is lost.
Manufacturer Code or the Device Code until an-
other command is issued. See Figure 21., Erase Flowchart and Pseudo
Code, for a suggested flowchart on using the
After the Read Electronic Signature Command is Erase command.
issued the Manufacturer Code and Device Code
can be read using Bus Read operations using the Clear Status Register Command. The Clear Sta-
addresses in Table 6. tus Register command can be used to reset bits 1,
3, 4 and 5 in the Status Register to ‘0’. One Bus
Program Command. The Program command Write is required to issue the Clear Status Register
can be used to program a value to one address in command. Once the command is issued the mem-
the memory array at a time. Two Bus Write opera- ory returns to its previous mode, subsequent Bus
tions are required to issue the command; the sec- Read operations continue to output the same data.
ond Bus Write cycle latches the address and data
in the internal state machine and starts the Pro- The bits in the Status Register are sticky and do
gram/Erase Controller. Once the command is is- not automatically return to ‘0’ when a new Program
sued subsequent Bus Read operations read the or Erase command is issued. If an error occurs
then it is essential to clear any error bits in the Sta-
Status Register. See the section on the Status
Register for details on the definitions of the Status tus Register by issuing the Clear Status Register
command before attempting a new Program or
Register bits.
Erase command.

14/41
 M50FW040

Program/Erase Suspend Command. The Pro- Signature and Program/Erase Resume com-
gram/Erase Suspend command can be used to mands will be accepted by the Command Inter-
pause a Program or Erase operation. One Bus face. Additionally, if the suspended operation was
Write cycle is required to issue the Program/Erase Erase then the Program command will also be ac-
Suspend command and pause the Program/Erase cepted; only the blocks not being erased may be
Controller. Once the command is issued it is nec- read or programmed correctly.
essary to poll the Program/Erase Controller Status See Figure 20., Program Suspend & Resume
bit to find out when the Program/Erase Controller Flowchart and Pseudo Code, and Figure
has paused; no other commands will be accepted 22., Erase Suspend & Resume Flowchart and
until the Program/Erase Controller has paused. Pseudo Code, for suggested flowcharts on using
After the Program/Erase Controller has paused, the Program/Erase Suspend command.
the memory will continue to output the Status Reg-
ister until another command is issued. Program/Erase Resume Command. The Pro-
gram/Erase Resume command can be used to re-
During the polling period between issuing the Pro- start the Program/Erase Controller after a
gram/Erase Suspend command and the Program/ Program/Erase Suspend operation has paused it.
Erase Controller pausing it is possible for the op- One Bus Write cycle is required to issue the Pro-
eration to complete. Once Program/Erase Control- gram/Erase Resume command. Once the com-
ler Status bit indicates that the Program/Erase mand is issued subsequent Bus Read operations
Controller is no longer active, the Program Sus- read the Status Register.
pend Status bit or the Erase Suspend Status bit
can be used to determine if the operation has com-
pleted or is suspended. For timing on the delay be- Table 6. Read Electronic Signature
tween issuing the Program/Erase Suspend Code Address Data
command and the Program/Erase Controller
Manufacturer Code 00000h 20h
pausing see Table 12.
During Program/Erase Suspend the Read Memo- Device Code 00001h 2Ch
ry Array, Read Status Register, Read Electronic

15/41
M50FW040

Table 7. Commands
Bus Write Operations

Cycles
Command 1st 2nd
Address Data Address Data
Read Memory Array 1 X FFh
Read Status Register 1 X 70h
1 X 90h
Read Electronic Signature
1 X 98h
2 X 40h PA PD
Program
2 X 10h PA PD
Erase 2 X 20h BA D0h
Clear Status Register 1 X 50h
Program/Erase Suspend 1 X B0h
Program/Erase Resume 1 X D0h
1 X 00h
1 X 01h
Invalid/Reserved 1 X 60h
1 X 2Fh
1 X C0h
Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block.
Read Memory Array. After a Read Memory Array command, read the memory as normal until another command is issued.
Read Status Register. After a Read Status Register command, read the Status Register as normal until another command is issued.
Read Electronic Signature. After a Read Electronic Signature command, read Manufacturer Code, Device Code until another com-
mand is issued.
Erase, Program. After these commands read the Status Register until the command completes and another command is issued.
Clear Status Register. After the Clear Status Register command bits 1, 3, 4 and 5 in the Status Register are reset to ‘0’.
Program/Erase Suspend. After the Program/Erase Suspend command has been accepted, issue Read Memory Array, Read Status
Register, Program (during Erase suspend) and Program/Erase resume commands.
Program/Erase Resume. After the Program/Erase Resume command the suspended Program/Erase operation resumes, read the
Status Register until the Program/Erase Controller completes and the memory returns to Read Mode.
Invalid/Reserved. Do not use Invalid or Reserved commands.

16/41
 M50FW040

STATUS REGISTER
The Status Register provides information on the still failed to verify that the block has erased cor-
current or previous Program or Erase operation. rectly. The Erase Status bit should be read once
Different bits in the Status Register convey differ- the Program/Erase Controller Status bit is ‘1’ (Pro-
ent information and errors on the operation. gram/Erase Controller inactive).
To read the Status Register the Read Status Reg- When the Erase Status bit is ‘0’ the memory has
ister command can be issued. The Status Register successfully verified that the block has erased cor-
is automatically read after Program, Erase and rectly; when the Erase Status bit is ‘1’ the Pro-
Program/Erase Resume commands are issued. gram/Erase Controller has applied the maximum
The Status Register can be read from any ad- number of pulses to the block and still failed to ver-
dress. ify that the block has erased correctly.
The Status Register bits are summarized in Status Once the Erase Status bit is set to ‘1’ the it can
Register Bits. Refer to Table 8. in conjunction with only be reset to ‘0’ by a Clear Status Register com-
the text descriptions below. mand or a hardware reset. If it is set to ‘1’ it should
Program/Erase Controller Status (Bit 7). The Pro- be reset before a new Program or Erase command
gram/Erase Controller Status bit indicates whether is issued, otherwise the new command will appear
the Program/Erase Controller is active or inactive. to fail.
When the Program/Erase Controller Status bit is Program Status (Bit 4). The Program Status bit
‘0’, the Program/Erase Controller is active; when can be used to identify if the memory has applied
the bit is ‘1’, the Program/Erase Controller is inac- the maximum number of program pulses to the
tive. byte and still failed to verify that the byte has pro-
The Program/Erase Controller Status is ‘0’ imme- grammed correctly. The Program Status bit should
diately after a Program/Erase Suspend command be read once the Program/Erase Controller Status
is issued until the Program/Erase Controller paus- bit is ‘1’ (Program/Erase Controller inactive).
es. After the Program/Erase Controller pauses the When the Program Status bit is ‘0’ the memory has
bit is ‘1’. successfully verified that the byte has pro-
During Program and Erase operation the Pro- grammed correctly; when the Program Status bit is
gram/Erase Controller Status bit can be polled to ‘1’ the Program/Erase Controller has applied the
find the end of the operation. The other bits in the maximum number of pulses to the byte and still
Status Register should not be tested until the Pro- failed to verify that the byte has programmed cor-
gram/Erase Controller completes the operation rectly.
and the bit is ‘1’. Once the Program Status bit is set to ‘1’ it can only
After the Program/Erase Controller completes its be reset to ‘0’ by a Clear Status Register com-
operation the Erase Status, Program Status, VPP mand or a hardware reset. If it is set to ‘1’ it should
Status and Block Protection Status bits should be be reset before a new Program or Erase command
tested for errors. is issued, otherwise the new command will appear
to fail.
Erase Suspend Status (Bit 6). The Erase Sus-
pend Status bit indicates that an Erase operation VPP Status (Bit 3). The VPP Status bit can be
has been suspended and is waiting to be re- used to identify an invalid voltage on the VPP pin
sumed. The Erase Suspend Status should only be during Program and Erase operations. The VPP
considered valid when the Program/Erase Con- pin is only sampled at the beginning of a Program
troller Status bit is ‘1’ (Program/Erase Controller or Erase operation. Indeterminate results can oc-
inactive); after a Program/Erase Suspend com- cur if VPP becomes invalid during a Program or
mand is issued the memory may still complete the Erase operation.
operation rather than entering the Suspend mode. When the VPP Status bit is ‘0’ the voltage on the
When the Erase Suspend Status bit is ‘0’ the Pro- VPP pin was sampled at a valid voltage; when the
gram/Erase Controller is active or has completed VPP Status bit is ‘1’ the VPP pin has a voltage that
its operation; when the bit is ‘1’ a Program/Erase is below the VPP Lockout Voltage, VPPLK, the
Suspend command has been issued and the memory is protected; Program and Erase opera-
memory is waiting for a Program/Erase Resume tion cannot be performed.
command. Once the VPP Status bit set to ‘1’ it can only be re-
When a Program/Erase Resume command is is- set to ‘0’ by a Clear Status Register command or a
sued the Erase Suspend Status bit returns to ‘0’. hardware reset. If it is set to ‘1’ it should be reset
before a new Program or Erase command is is-
Erase Status (Bit 5). The Erase Status bit can be
sued, otherwise the new command will appear to
used to identify if the memory has applied the fail.
maximum number of erase pulses to the block and

17/41
M50FW040

Program Suspend Status (Bit 2). The Program gram or Erase operation has tried to modify the
Suspend Status bit indicates that a Program oper- contents of a protected block. When the Block Pro-
ation has been suspended and is waiting to be re- tection Status bit is to ‘0’ no Program or Erase op-
sumed. The Program Suspend Status should only erations have been attempted to protected blocks
be considered valid when the Program/Erase since the last Clear Status Register command or
Controller Status bit is ‘1’ (Program/Erase Control- hardware reset; when the Block Protection Status
ler inactive); after a Program/Erase Suspend com- bit is ‘1’ a Program or Erase operation has been at-
mand is issued the memory may still complete the tempted on a protected block.
operation rather than entering the Suspend mode. Once it is set to ‘1’ the Block Protection Status bit
When the Program Suspend Status bit is ‘0’ the can only be reset to ‘0’ by a Clear Status Register
Program/Erase Controller is active or has complet- command or a hardware reset. If it is set to ‘1’ it
ed its operation; when the bit is ‘1’ a Program/ should be reset before a new Program or Erase
Erase Suspend command has been issued and command is issued, otherwise the new command
the memory is waiting for a Program/Erase Re- will appear to fail.
sume command. Using the A/A Mux Interface the Block Protection
When a Program/Erase Resume command is is- Status bit is always ‘0’.
sued the Program Suspend Status bit returns to Reserved (Bit 0). Bit 0 of the Status Register is
‘0’. reserved. Its value should be masked.
Block Protection Status (Bit 1). The Block Pro-
tection Status bit can be used to identify if the Pro-

Table 8. Status Register Bits

Operation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

Program active ‘0’ (1) ‘0’ ‘0’ ‘0’ ‘0’ ‘0’

X

Program suspended ‘1 X(1) ‘0’ ‘0’ ‘0’ ‘1’ ‘0’

Program completed successfully ‘1’ X(1) ‘0’ ‘0’ ‘0’ ‘0’ ‘0’

Program failure due to VPP Error ‘1’ X(1) ‘0’ ‘0’ ‘1’ ‘0’ ‘0’

Program failure due to Block Protection (FWH Interface only) ‘1’ X(1) ‘0’ ‘0’ ‘0’ ‘0’ ‘1’

Program failure due to cell failure ‘1’ X(1) ‘0’ ‘1’ ‘0’ ‘0’ ‘0’

Erase active ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’

Erase suspended ‘1’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
Erase completed successfully ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
Erase failure due to VPP Error ‘1’ ‘0’ ‘0’ ‘0’ ‘1’ ‘0’ ‘0’
Erase failure due to Block Protection (FWH Interface only) ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘1’
Erase failure due to failed cell(s) in block ‘1’ ‘0’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’
Note: 1. For Program operations during Erase Suspend Bit 6 is ‘1’, otherwise Bit 6 is ‘0’.

18/41
 M50FW040

FIRMWARE HUB (FWH) INTERFACE CONFIGURATION REGISTERS

When the Firmware Hub Interface is selected sev- ple hacking and malicious attack. When the Lock
eral additional registers can be accessed. These Down Bit is set, ‘1’, further modification to the
registers control the protection status of the Write Lock, Read Lock and Lock Down Bits cannot
Blocks, read the General Purpose Input pins and be performed. A reset or power-up is required be-
identify the memory using the Electronic Signature fore changes to these bits can be made. When the
codes. See Table 9. for the memory map of the Lock Down Bit is reset, ‘0’, the Write Lock, Read
Configuration Registers. Lock and Lock Down Bits can be changed.
Lock Registers Firmware Hub (FWH) General Purpose Input
The Lock Registers control the protection status of Register
the Blocks. Each Block has its own Lock Register. The Firmware Hub (FWH) General Purpose Input
Three bits within each Lock Register control the Register holds the state of the Firmware Hub Inter-
protection of each block, the Write Lock Bit, the face General Purpose Input pins, FGPI0-FGPI4.
Read Lock Bit and the Lock Down Bit. When this register is read, the state of these pins
The Lock Registers can be read and written, is returned. This register is read-only and writing to
though care should be taken when writing as, once it has no effect.
the Lock Down Bit is set, ‘1’, further modifications The signals on the Firmware Hub Interface Gener-
to the Lock Register cannot be made until cleared, al Purpose Input pins should remain constant
to ‘0’, by a reset or power-up. throughout the whole Bus Read cycle in order to
See Table 10. for details on the bit definitions of guarantee that the correct data is read.
the Lock Registers. Manufacturer Code Register
Write Lock. The Write Lock Bit determines Reading the Manufacturer Code Register returns
whether the contents of the Block can be modified the manufacturer code for the memory. The man-
(using the Program or Erase Command). When ufacturer code for STMicroelectronics is 20h. This
the Write Lock Bit is set, ‘1’, the block is write pro- register is read-only and writing to it has no effect.
tected; any operations that attempt to change the Device Code Register
data in the block will fail and the Status Register
will report the error. When the Write Lock Bit is re- Reading the Device Code Register returns the de-
vice code for the memory, 2Ch. This register is
set, ‘0’, the block is not write protected through the
Lock Register and may be modified unless write read-only and writing to it has no effect.
protected through some other means. Firmware Hub (FWH) General Purpose Input
When VPP is less than VPPLK all blocks are pro- Register
tected and cannot be modified, regardless of the The Firmware Hub (FWH) General Purpose Input
state of the Write Lock Bit. If Top Block Lock, TBL, Register holds the state of the Firmware Hub Inter-
is Low, VIL, then the Top Block (Block 7) is write face General Purpose Input pins, FGPI0-FGPI4.
protected and cannot be modified. Similarly, if When this register is read, the state of these pins
Write Protect, WP, is Low, VIL, then the Main is returned. This register is read-only and writing to
Blocks (Blocks 0 to 6) are write protected and can- it has no effect.
not be modified. The signals on the Firmware Hub Interface Gener-
After power-up or reset the Write Lock Bit is al- al Purpose Input pins should remain constant
ways set to ‘1’ (write protected). throughout the whole Bus Read cycle in order to
guarantee that the correct data is read.
Read Lock. The Read Lock bit determines
whether the contents of the Block can be read Manufacturer Code Register
(from Read mode). When the Read Lock Bit is set, Reading the Manufacturer Code Register returns
‘1’, the block is read protected; any operation that the manufacturer code for the memory. The man-
attempts to read the contents of the block will read ufacturer code for STMicroelectronics is 20h. This
00h instead. When the Read Lock Bit is reset, ‘0’, register is read-only and writing to it has no effect.
read operations in the Block return the data pro- Device Code Register
grammed into the block as expected.
Reading the Device Code Register returns the de-
After power-up or reset the Read Lock Bit is al- vice code for the memory, 2Ch. This register is
ways reset to ‘0’ (not read protected). read-only and writing to it has no effect.
Lock Down. The Lock Down Bit provides a
mechanism for protecting software data from sim-

19/41
M50FW040

Table 9. Firmware Hub Register Configuration Map

Memory Default
Mnemonic Register Name Access
Address Value
T_BLOCK_LK Top Block Lock Register (Block 7) FBF0002h 01h R/W
T_MINUS01_LK Top Block [-1] Lock Register (Block 6) FBE0002h 01h R/W
T_MINUS02_LK Top Block [-2] Lock Register (Block 5) FBD0002h 01h R/W
T_MINUS03_LK Top Block [-3] Lock Register (Block 4) FBC0002h 01h R/W
T_MINUS04_LK Top Block [-4] Lock Register (Block 3) FBB0002h 01h R/W
T_MINUS05_LK Top Block [-5] Lock Register (Block 2) FBA0002h 01h R/W
T_MINUS06_LK Top Block [-6] Lock Register (Block 1) FB90002h 01h R/W
T_MINUS07_LK Top Block [-7] Lock Register (Block 0) FB80002h 01h R/W
FGPI_REG Firmware Hub (FWH) General Purpose Input Register FBC0100h N/A R
MANUF_REG Manufacturer Code Register FBC0000h 20h R
DEV_REG Device Code Register FBC0001h 2Ch R

Table 10. Lock Register Bit Definitions

Bit Bit Name Value Function
7-3 Reserved
‘1’ Bus Read operations in this Block always return 00h.
2 Read-Lock
‘0’ Bus read operations in this Block return the Memory Array contents. (Default value).
Changes to the Read-Lock bit and the Write-Lock bit cannot be performed. Once a ‘1’ is
‘1’ written to the Lock-Down bit it cannot be cleared to ‘0’; the bit is always reset to ‘0’ following
1 Lock-Down a Reset (using RP or INIT) or after power-up.
‘0’ Read-Lock and Write-Lock can be changed by writing new values to them. (Default value).
Program and Erase operations in this Block will set an error in the Status Register. The
‘1’
0 Write-Lock memory contents will not be changed. (Default value).
‘0’ Program and Erase operations in this Block are executed and will modify the Block contents.
Note: 1. Applies to Top Block Lock Register (T_BLOCK_LK) and Top Block [-1] Lock Register (T_MINUS01_LK) to Top Block [-7] Lock Reg-
ister (T_MINUS07_LK).

Table 11. General Purpose Inputs Register Definition

Bit Bit Name Value Function
7-5 Reserved
‘1’ Input Pin FGPI4 is at VIH
4 FGPI4
‘0’ Input Pin FGPI4 is at VIL
‘1’ Input Pin FGPI3 is at VIH
3 FGPI3
‘0’ Input Pin FGPI3 is at VIL
‘1’ Input Pin FGPI2 is at VIH
2 FGPI2
‘0’ Input Pin FGPI2 is at VIL
‘1’ Input Pin FGPI1 is at VIH
1 FGPI1
‘0’ Input Pin FGPI1 is at VIL
‘1’ Input Pin FGPI0 is at VIH
0 FGPI0
‘0’ Input Pin FGPI0 is at VIL
Note: 1. Applies to the General Purpose Inputs Register (FGPI-REG).

20/41
 M50FW040

PROGRAM AND ERASE TIMES

The Program and Erase times are shown in Table
12.

Table 12. Program and Erase Times

Parameter Test Condition Min Typ (1) Max Unit

Byte Program 10 200 µs

Block Program 0.4 5 sec
VPP = 12V ± 5% 0.75 8 sec
Block Erase
VPP = VCC 1 10 sec
Program/Erase Suspend to Program pause(2) 5 µs

Program/Erase Suspend to Block Erase pause(2) 30 µs

Note: 1. TA = 25°C, VCC = 3.3V
2. Sampled only, not 100% tested.

21/41
M50FW040

MAXIMUM RATING
Stressing the device above the rating listed in the plied. Exposure to Absolute Maximum Rating con-
Absolute Maximum Ratings table may cause per- ditions for extended periods may affect device
manent damage to the device. These are stress reliability. Refer also to the STMicroelectronics
ratings only and operation of the device at these or SURE Program and other relevant quality docu-
any other conditions above those indicated in the ments.
Operating sections of this specification is not im-

Table 13. Absolute Maximum Ratings

Symbol Parameter Min Max Unit
TSTG Storage Temperature –65 150 °C
TLEAD Lead Temperature during Soldering See note 1 °C

VIO (2) Input or Output Voltage –0.6 VCC + 0.6 V

VCC Supply Voltage –0.6 4 V

VPP Program Voltage –0.6 13 V
Note: 1. Compliant with JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK ® 7191395 specification, and
the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.
2. Minimum Voltage may undershoot to –2V and for less than 20ns during transitions. Maximum Voltage may overshoot to VCC + 2V
and for less than 20ns during transitions.

22/41
 M50FW040

DC AND AC PARAMETERS
This section summarizes the operating measure- Conditions summarized in Table 14., Table 15.
ment conditions, and the DC and AC characteris- and Table 16. Designers should check that the op-
tics of the device. The parameters in the DC and erating conditions in their circuit match the operat-
AC characteristics Tables that follow, are derived ing conditions when relying on the quoted
from tests performed under the Measurement parameters.

Table 14. Operating Conditions

Symbol Parameter Min Max Unit
Ambient Operating Temperature (Device Grade 1) 0 70 °C
TA
Ambient Operating Temperature (Device Grade 5) –20 85 °C
VCC Supply Voltage 3 3.6 V

Table 15. FWH Interface AC Measurement Conditions

Parameter Value Unit
Load Capacitance (CL) 10 pF

Input Rise and Fall Times ≤ 1.4 ns

Input Pulse Voltages 0.2 VCC and 0.6 VCC V

Input and Output Timing Ref. Voltages 0.4 VCC V

Table 16. A/A Mux Interface AC Measurement Conditions

Parameter Value Unit

Load Capacitance (CL) 30 pF

Input Rise and Fall Times ≤ 10 ns

Input Pulse Voltages 0 to 3 V

Input and Output Timing Ref. Voltages 1.5 V

Figure 9. FWH Interface AC Testing Input Output Waveforms

0.6 VCC

0.4 VCC

0.2 VCC
Input and Output AC Testing Waveform

IO < ILO IO > ILO IO < ILO

Output AC Tri-state Testing Waveform

AI03404

23/41
M50FW040

Figure 10. A/A Mux Interface AC Testing Input Output Waveform

3V

1.5V

0V

AI01417

Table 17. Impedance

Symbol Parameter Test Condition Min Max Unit

CIN(1) Input Capacitance VIN = 0V 13 pF

CCLK(1) Clock Capacitance VIN = 0V 3 12 pF

Recommended Pin
LPIN(2) Inductance
20 nH

Note: 1. Sampled only, not 100% tested.

2. See PCI Specification.
3. TA = 25 °C, f = 1 MHz).

24/41
 M50FW040

Table 18. DC Characteristics

Symbol Parameter Interface Test Condition Min Max Unit
FWH 0.5 VCC VCC + 0.5 V
VIH Input High Voltage
A/A Mux 0.7 VCC VCC + 0.3 V

FWH –0.5 0.3 VCC V

VIL Input Low Voltage
A/A Mux -0.5 0.8 V
VIH(INIT) INIT Input High Voltage FWH 1.35 VCC + 0.5 V

VIL(INIT) INIT Input Low Voltage FWH –0.5 0.2 VCC V

ILI(2) Input Leakage Current 0V ≤ VIN ≤ VCC ±10 µA

IC, IDx Input Leakage
ILI2
Current
IC, ID0, ID1, ID2, ID3 = VCC 200 µA

IC, IDx Input Pull Low

RIL 20 100 kΩ
Resistor

FWH IOH = –500µA 0.9 VCC V

VOH Output High Voltage
A/A Mux IOH = –100µA VCC – 0.4 V

FWH IOL = 1.5mA 0.1 VCC V

VOL Output Low Voltage
A/A Mux IOL = 1.8mA 0.45 V

ILO Output Leakage Current 0V ≤ VOUT ≤ VCC ±10 µA

VPP1 VPP Voltage 3 3.6 V
VPP Voltage
VPPH 11.4 12.6 V
(Fast Erase)

VPPLK(1) VPP Lockout Voltage 1.5 V

VLKO(1) VCC Lockout Voltage 1.8 2.3 V

FWH4 = 0.9 VCC, VPP = VCC

ICC1 Supply Current (Standby) FWH All other inputs 0.9 VCC to 0.1 VCC 100 µA
VCC = 3.6V, f(CLK) = 33MHz

FWH4 = 0.1 VCC, VPP = VCC

ICC2 Supply Current (Standby) FWH All other inputs 0.9 VCC to 0.1 VCC 10 mA
VCC = 3.6V, f(CLK) = 33MHz

Supply Current VCC = VCC max, VPP = VCC

ICC3 (Any internal operation FWH f(CLK) = 33MHz 60 mA
active) IOUT = 0mA

ICC4 Supply Current (Read) A/A Mux G = VIH, f = 6MHz 20 mA

Supply Current
ICC5(1) (Program/Erase)
A/A Mux Program/Erase Controller Active 20 mA

VPP Supply Current

IPP VPP > VCC 400 µA
(Read/Standby)

VPP Supply Current VPP = VCC 40 mA

IPP1(1)
(Program/Erase active) VPP = 12V ± 5% 15 mA
Note: 1. Sampled only, not 100% tested.
2. Input leakage currents include High-Z output leakage for all bi-directional buffers with tri-state outputs.

25/41
M50FW040

Figure 11. FWH Interface Clock Waveform

tCYC

tHIGH tLOW

0.6 VCC
0.5 VCC
0.4 VCC, p-to-p
0.4 VCC
(minimum)
0.3 VCC
0.2 VCC

AI03403

Table 19. FWH Interface Clock Characteristics

Symbol Parameter Test Condition Value Unit

tCYC CLK Cycle Time(1) Min 30 ns

tHIGH CLK High Time Min 11 ns

tLOW CLK Low Time Min 11 ns
Min 1 V/ns
CLK Slew Rate peak to peak
Max 4 V/ns
Note: 1. Devices on the PCI Bus must work with any clock frequency between DC and 33MHz. Below 16MHz devices may be guaranteed
by design rather than tested. Refer to PCI Specification.

26/41
 M50FW040

Figure 12. FWH Interface AC Signal Timing Waveforms

CLK

tCHQV tCHQZ tDVCH

tCHQX tCHDX

FWH0-FWH3 VALID

VALID OUTPUT DATA FLOAT OUTPUT DATA VALID INPUT DATA

AI03405

Table 20. FWH Interface AC Signal Timing Characteristics

PCI
Symbol Parameter Test Condition Value Unit
Symbol
Min 2 ns
tCHQV tval CLK to Data Out
Max 11 ns
CLK to Active
tCHQX(1) ton
(Float to Active Delay)
Min 2 ns

CLK to Inactive
tCHQZ toff Max 28 ns
(Active to Float Delay)
tAVCH
tDVCH
tsu Input Set-up Time(2) Min 7 ns

tCHAX
tCHDX
th Input Hold Time(2) Min 0 ns

Note: 1. The timing measurements for Active/Float transitions are defined when the current through the pin equals the leakage current spec-
ification.
2. Applies to all inputs except CLK.

27/41
M50FW040

Figure 13. Reset AC Waveforms

RP, INIT

tPLPH tPHWL, tPHGL, tPHFL

W, G, FWH4
tPLRH

RB

AI03420

Table 21. Reset AC Characteristics

Symbol Parameter Test Condition Value Unit
tPLPH RP or INIT Reset Pulse Width Min 100 ns

Program/Erase Inactive Max 100 ns

tPLRH RP or INIT Low to Reset
Program/Erase Active Max 30 µs

RP or INIT Slew Rate(1) Rising edge only Min 50 mV/ns

tPHFL RP or INIT High to FWH4 Low FWH Interface only Min 30 µs

tPHWL RP High to Write Enable or Output
A/A Mux Interface only Min 50 µs
tPHGL Enable Low
Note: 1. See Chapter 4 of the PCI Specification.

28/41
 M50FW040

Figure 14. A/A Mux Interface Read AC Waveforms

tAVAV

A0-A10 ROW ADDR VALID COLUMN ADDR VALID NEXT ADDR VALID

tAVCL tAVCH

tCLAX tCHAX

RC

tCHQV

tGLQV tGHQZ

tGLQX tGHQX

DQ0-DQ7 VALID

tPHAV

RP

AI03406

Table 22. A/A Mux Interface Read AC Characteristics

Symbol Parameter Test Condition Value Unit
tAVAV Read Cycle Time Min 250 ns
tAVCL Row Address Valid to RC Low Min 50 ns
tCLAX RC Low to Row Address Transition Min 50 ns
tAVCH Column Address Valid to RC high Min 50 ns
tCHAX RC High to Column Address Transition Min 50 ns

tCHQV(1) RC High to Output Valid Max 150 ns

tGLQV(1) Output Enable Low to Output Valid Max 50 ns

tPHAV RP High to Row Address Valid Min 1 µs

tGLQX Output Enable Low to Output Transition Min 0 ns

tGHQZ Output Enable High to Output Hi-Z Max 50 ns

tGHQX Output Hold from Output Enable High Min 0 ns
Note: 1. G may be delayed up to tCHQV – tGLQV after the rising edge of RC without impact on tCHQV.

29/41
M50FW040

Figure 15. A/A Mux Interface Write AC Waveforms

Write erase or Write erase confirm or Automated erase Read Status Ready to write
program setup valid address and data or program delay Register Data another command

A0-A10 R1 C1 R2 C2

tCLAX tAVCH

tAVCL tCHAX

RC

tWHWL

tWLWH tCHWH

tVPHWH tWHGL

tWHRL

RB

tQVVPL

VPP

tDVWH tWHDX

DQ0-DQ7 DIN1 DIN2 VALID SRD

AI04185

Table 23. A/A Mux Interface Write AC Characteristics

Symbol Parameter Test Condition Value Unit
tWLWH Write Enable Low to Write Enable High Min 100 ns
tDVWH Data Valid to Write Enable High Min 50 ns
tWHDX Write Enable High to Data Transition Min 5 ns
tAVCL Row Address Valid to RC Low Min 50 ns
tCLAX RC Low to Row Address Transition Min 50 ns
tAVCH Column Address Valid to RC High Min 50 ns
tCHAX RC High to Column Address Transition Min 50 ns
tWHWL Write Enable High to Write Enable Low Min 100 ns

tCHWH RC High to Write Enable High Min 50 ns

tVPHWH(1) VPP High to Write Enable High Min 100 ns

tWHGL Write Enable High to Output Enable Low Min 30 ns

tWHRL Write Enable High to RB Low Min 0 ns

tQVVPL(1,2) Output Valid, RB High to VPP Low Min 0 ns

Note: 1. Sampled only, not 100% tested.
2. Applicable if VPP is seen as a logic input (VPP < 3.6V).

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 M50FW040

PACKAGE MECHANICAL

Figure 16. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Outline
D A1
D1 A2

1 N
B1
E2

e
E3 E1 E F
B
0.51 (.020) E2

1.14 (.045)

D3 A

R CP

D2 D2
PLCC-A

Note: Drawing is not to scale.

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M50FW040

Table 24. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Mechanical Data
millimeters inches
Symbol
Typ Min Max Typ Min Max
A 3.18 3.56 0.125 0.140
A1 1.53 2.41 0.060 0.095
A2 0.38 – 0.015 –
B 0.33 0.53 0.013 0.021
B1 0.66 0.81 0.026 0.032
CP 0.10 0.004
D 12.32 12.57 0.485 0.495
D1 11.35 11.51 0.447 0.453
D2 4.78 5.66 0.188 0.223
D3 7.62 – – 0.300 – –
E 14.86 15.11 0.585 0.595
E1 13.89 14.05 0.547 0.553
E2 6.05 6.93 0.238 0.273
E3 10.16 – – 0.400 – –
e 1.27 – – 0.050 – –
F 0.00 0.13 0.000 0.005
R 0.89 – – 0.035 – –
N 32 32

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 M50FW040

Figure 17. TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Outline
A2

1 N
e

B
N/2

D1 A
D CP

DIE

TSOP-a A1 α L

Note: Drawing is not to scale.

Table 25. TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Mechanical Data
millimeters inches
Symbol
Typ Min Max Typ Min Max
A 1.200 0.0472
A1 0.050 0.150 0.0020 0.0059
A2 0.950 1.050 0.0374 0.0413
α 0° 5° 0° 5°
B 0.170 0.270 0.0067 0.0106
C 0.100 0.210 0.0039 0.0083
CP 0.100 0.0039
D 13.800 14.200 0.5433 0.5591
D1 12.300 12.500 0.4843 0.4921
e 0.500 – – 0.0197 – –
E 7.900 8.100 0.3110 0.3189
L 0.500 0.700 0.0197 0.0276
N 32 32

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M50FW040

Figure 18. TSOP40 – 40 lead Plastic Thin Small Outline, 10x20 mm, Package Outline
A2

1 N
e

B
N/2

D1 A
D CP

DIE

TSOP-a A1 α L

Note: Drawing is not to scale.

Table 26. TSOP40 – 40 lead Plastic Thin Small Outline, 10x20 mm, Package Mechanical Data
millimeters inches
Symbol
Typ Min Max Typ Min Max
A 1.200 0.0472
A1 0.050 0.150 0.0020 0.0059
A2 0.950 1.050 0.0374 0.0413
B 0.170 0.270 0.0067 0.0106
C 0.100 0.210 0.0039 0.0083
CP 0.100 0.0039
D 19.800 20.200 0.7795 0.7953
D1 18.300 18.500 0.7205 0.7283
e 0.500 – – 0.0197 – –
E 9.900 10.100 0.3898 0.3976
L 0.500 0.700 0.0197 0.0276
α 0° 5° 0° 5°
N 40 40

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 M50FW040

PART NUMBERING

Table 27. Ordering Information Scheme

Example: M50FW040 K 1 T G

Device Type
M50

Architecture
F = Firmware Hub Interface

Operating Voltage
W = 3V to 3.6V

Device Function
040 = 4 Mbit (x8), Uniform Block

Package
K = PLCC32
NB = TSOP32 (8 x 14mm)
N = TSOP40: 10 x 20 mm

Device Grade
5 = Temperature range –20 to 85 °C.
Device tested with standard test flow
1 = Temperature range 0 to 70 °C.
Device tested with standard test flow

Option
blank = Standard Packing
T = Tape & Reel Packing

Plating Technology
blank = Standard SnPb plating
G = Lead-Free, RoHS compliant, Sb2O3-free and TBBA-free

Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device,
please contact the ST Sales Office nearest to you.

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M50FW040

FLOWCHARTS AND PSEUDO CODES

Figure 19. Program Flowchart and Pseudo Code

Start

Write 40h or 10h Program command:

– write 40h or 10h
– write Address & Data
(memory enters read status state after
the Program command)
Write Address
& Data

NO do:
Read Status –read Status Register if Program/Erase
Register Suspend command given execute
Suspend suspend program loop
YES

NO
b7 = 1 Suspend
Loop
while b7 = 1
YES

NO VPP Invalid If b3 = 1, VPP invalid error:

b3 = 0
Error (1, 2) – error handler

YES

NO Program If b4 = 1, Program error:

b4 = 0
Error (1, 2) – error handler

YES

FWH NO Program to Protected If b1 = 1, Program to protected block error:

Interface b1 = 0
Block Error (1, 2) – error handler
Only
YES

End
AI03407

Note: 1. A Status check of b1 (Protected Block), b3 (VPP invalid) and b4 (Program Error) can be made after each Program operation by
following the correct command sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

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 M50FW040

Figure 20. Program Suspend & Resume Flowchart and Pseudo Code

Start

Write B0h

Program/Erase Suspend command:

Write 70h – write B0h
– write 70h

do:
Read Status – read Status Register
Register

NO
b7 = 1 while b7 = 1

YES

NO
b2 = 1 Program Complete If b2 = 0 Program completed

YES

Write a read
Command

Read data from

another address

Program/Erase Resume command:

Write D0h Write FFh – write D0h to resume the program
– if the Program operation completed
then this is not necessary.
The device returns to Read as
normal (as if the Program/Erase
Program Continues Read Data suspend was not issued).

AI03408

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M50FW040

Figure 21. Erase Flowchart and Pseudo Code

Start

Write 20h Erase command:

– write 20h
– write Block Address & D0h
(memory enters read Status Register after
the Erase command)
Write Block Address
& D0h

do:
NO – read Status Register
Read Status – if Program/Erase Suspend command
Register given execute suspend erase loop
Suspend
YES

NO Suspend
b7 = 1
Loop

while b7 = 1
YES

NO VPP Invalid If b3 = 1, VPP invalid error:

b3 = 0
Error (1) – error handler

YES

NO Command If b4, b5 = 1, Command sequence error:

b4, b5 = 0
Sequence Error (1) – error handler

YES

NO If b5 = 1, Erase error:
b5 = 0 Erase Error (1)
– error handler

YES

FWH NO Erase to Protected If b1 = 1, Erase to protected block error:

Interface b1 = 0
Block Error (1) – error handler
Only
YES

End

AI03409

Note: 1. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

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 M50FW040

Figure 22. Erase Suspend & Resume Flowchart and Pseudo Code

Start

Write B0h

Program/Erase Suspend command:

Write 70h – write B0h
– write 70h

do:
Read Status – read Status Register
Register

NO
b7 = 1 while b7 = 1

YES

NO
b6 = 1 Erase Complete If b6 = 0, Erase completed

YES

Read data from

another block
or
Program

Program/Erase Resume command:

Write D0h Write FFh – write D0h to resume erase
– if the Erase operation completed
then this is not necessary.
The device returns to Read as
normal (as if the Program/Erase
Erase Continues Read Data suspend was not issued).

AI03410

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M50FW040

REVISION HISTORY

Table 28. Document Revision History

Date Version Revision Details
September 2000 -01 First Issue
04-Oct-2000 -02 DC Characteristics: ICC4 changed

11-Apr-01 -03 Document type: from Preliminary Data to Data Sheet

Program and Erase functions clarification
Read Electronic Signature table change
FWH Register Configuration Map table change
Input Register Definition table, note clarification
DC Characteristics parameters clarification and new VIH and VIL parameters added
FWH Interface AC Signal Timing Characteristics change
A/A Mux Interface Read AC Characteristics change
A/A Mux Interface Write AC Characteristics change
A/A Mux Interface Write AC Waveforms change
06-Jul-2001 -04 Note 2 changed (Table 13., Absolute Maximum Ratings)
RFU pins must be left disconnected
12-Mar-2002 -05
Specification of PLCC32 package mechanical data revised
Revision numbering modified.
Document imported in new template (and so reformatted).
Temperature Range ordering information replaced by Device Grade, Standard
09-Jul-2004 6.0
packing option added and Plating Technology added to Table 27., Ordering
Information Scheme. TLEAD parameter added to Table 13., Absolute Maximum
Ratings and TBIAS parameter removed.

12-Jul-2004 7.0 Inches values corrected in Table 27., Ordering Information Scheme.
TSOP32 package added. Figure 3., Logic Diagram (A/A Mux Interface) and Table
10-Nov-2004 8.0
2., Signal Names (A/A Mux Interface) added.

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 M50FW040

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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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