UNIT-V

1 Processor which is complex and expensive to produce is c

________
a) RISC
b) EPIC
c) CISC
d) Multi-core
2 The architecture that uses a tighter coupling between the a
compiler and the processor is ____________
a) EPIC
b) Multi-core
c) RISC
d) CISC
3 What is 80/20 rule? A
a) 80% instruction is generated and 20% instruction is
executed
b) 80% instruction is executed and 20% instruction is
generated
c) 80%instruction is executed and 20% instruction is not
executed
d) 80% instruction is generated and 20% instructions are
not generated
4 Which is the first company who defined RISC b
architecture?
a) Intel
b) IBM
c) Motorola
d) MIPS
5 How is memory accessed in RISC architecture? a
a) load and store instruction
b) opcode instruction
c) memory instruction
d) bus instruction
6 Which of the following has a Harvard architecture? c
a) EDSAC
b) SSEM
c) PIC
d) CSIRAC
7 Which of the following processors has CISC architecture? D
a) AVR
b) Atmel
c) Blackfin
d) Zilog Z80
8 How many bit register set does RISC 1 model used? b
a) 138*24
b) 138*32
c) 69*16
d) 69*32
9 Which of the following ARM instructions performs a a
logical shift left by 2 bits on register R1 and adds it
to R2?
A. ADD R3, R2, R1, LSL #2
B. ADD R3, R1, R2, LSR #2
C. ADD R3, R1, R2, LSL #2
 D. ADD R3, R2, R1 followed by LSL R3, R3, #2

10 What does the ARM instruction BNE label do? b

A. Branch if the result is negative
B. Branch if the zero flag is not set
C. Branch if the carry flag is clear
D. Branch always

11 Which flag combination causes the ARM BLT B

(Branch if Less Than) instruction to take the
branch?
A. Z = 1
B. N ≠ V
C. N = V
D. C = 0

12 What happens when the ARM instruction STR R2, a

[R1], #4 is executed?
A. R2 is stored at address in R1, then R1 is
incremented by 4
B. R2 is stored at address (R1 + 4)
C. R2 is loaded from address in R1, then R1 is
incremented by 4
D. R1 is incremented, then R2 is stored

13 In ARM, what is the effect of the instruction MOV a

R3, R1, LSR #1?
A. R1 is shifted right by 1 and result stored in R3
B. R1 is shifted left by 1 and stored in R3
C. R1 is rotated right and stored in R3
D. R1 is copied directly to R3

14 Which ARM instruction allows combining shift and b

arithmetic in one step?
A. MOV
B. ADD R0, R1, R2, LSL #2
C. STR
D. BNE
15 Which addressing mode is used in LDR R4, [R5, #8]!? a
A. Pre-indexed
B. Post-indexed
C. Offset
D. Immediate

16 What is a register window in RISC architectures like c

SPARC primarily used for?
A. Memory-mapped I/O
B. Interrupt handling
C. Efficient parameter passing between procedures
D. Floating-point computation

17 In register window-based architectures, what causes a b

window overflow?
A. Exceeding memory size
B. Too many procedure calls without returns
C. Stack overflow
D. Too many parameters in a single function

18 What happens during a register window underflow in c

SPARC-like architectures?
A. Registers are overwritten
B. Memory is allocated for parameters
C. Register contents are restored from memory
D. All registers are flushed

19 Which of the following is NOT a typical feature of RISC c

architecture?
A. Load/store architecture
B. Few addressing modes
C. Complex instructions
D. Uniform instruction format

20 Why are RISC architectures more suitable for pipelining c

than CISC?
A. They have fewer registers
B. Their instructions are variable in length
C. Instructions are simple and execute in fixed time
D. They use microcode for execution

21 In a typical 5-stage RISC pipeline (IF, ID, EX, MEM, WB), c

at which stage is the branch target address computed?
A. IF
B. ID
C. EX
D. MEM
22 Which of the following hazards can occur in a pipeline
when a branch instruction is encountered?
A. Structural hazard
B. Data hazard
C. Control hazard
D. Register hazard
23 Which mechanism helps reduce the performance c
penalty of a pipeline control hazard caused by branch
instructions?
A. Load buffering
B. Write combining
C. Branch prediction
D. Instruction duplication

24 A RISC processor has a 5-stage pipeline. If each c

instruction takes 1 clock cycle per stage and the
pipeline is full, how many clock cycles are needed to
execute 100 instructions?
A. 100
B. 104
C. 105
D. 109

25 A CISC instruction takes 4 clock cycles to execute. A c

RISC instruction takes 1 cycle but needs 1.5× more
instructions to perform the same task. If the clock rate
is the same, which architecture finishes faster for a
task that requires 40 CISC instructions?
26 A processor executes instructions with 1 CPI (Cycles Per b
Instruction) and runs at 2 GHz. How many instructions
does it execute in 1 second?
A. 2 million
B. 2 billion
C. 1 billion
D. 4 billion

27 In a register window system with 10 windows, how b

many times can a procedure be nested before causing a
window overflow, assuming each call uses one window?
A. 8
B. 9
C. 10
D. 11

28 A 32-bit RISC instruction has 6 bits for opcode and 5 c

bits each for source and destination registers. How
many bits are left for immediate or address fields?
A. 10
B. 12
C. 16
D. 18

29 If memory access takes 100 ns and a register access c

takes 10 ns, how much faster is register-based
parameter passing compared to memory-based?
(Assume 4 parameters)
A. 2.5×
B. 5×
C. 10×
D. 15×
30 A RISC processor has a pipeline with 5 stages. If 20% of b
instructions are branches and every branch causes a 2-
cycle stall, what is the average CPI assuming ideal CPI
is 1?
A. 1.0
B. 1.2
C. 1.4
D. 1.5

31 A function in a register window system calls 4 nested d

procedures. If each call uses a new window and
windows overlap by 8 registers, how many registers are
used (not reused)?
A. 64
B. 80
C. 96
D. 88

32 A RISC CPU has 32 registers. If each instruction can use A

2 source and 1 destination register, how many unique
combinations of registers are possible for a single
instruction?
A. 32³
B. 32²
C. 32
D. 64

33 The i386 processor uses 32-bit general-purpose C

registers. If a program uses 8 such registers fully, how
much register storage (in bytes) is being used?
A. 16 bytes
B. 32 bytes
C. 64 bytes
D. 128 bytes

34 The i486 processor supports pipelined instruction c

execution with a 5-stage pipeline. If one instruction
completes every clock cycle after the pipeline is filled,
how many cycles are needed to execute 50
instructions?
A. 50
B. 54
C. 55
D. 56
35 The Pentium processor has two pipelines (U and V) that b
can execute two instructions per cycle under ideal
conditions. How many cycles are required to execute
100 instructions if dual-issue happens 60% of the time?
A. 50
B. 62.5
C. 70
D. 80

36 A Raspberry Pi 4 has a quad-core 1.5 GHz processor. If d

 one core can execute 1 instruction per cycle, how many
instructions can all 4 cores execute in 2 seconds?
A. 6 × 10⁹
B. 9 × 10⁹
C. 12 × 10⁹
D. 15 × 10⁹

UNIT-IV
1 How many total bits are available in the 8051’s 4 I/O c
ports (P0–P3)?
A. 16 bits
B. 24 bits
C. 32 bits
D. 64 bits

2 The 8051 has 4 register banks. Each bank contains 8 c

registers. How many bytes are used in total by all
register banks?
A. 4 bytes
B. 8 bytes
C. 16 bytes
D. 32 bytes

3 If the stack pointer (SP) in 8051 is at 07H, and two d

PUSH operations are performed, what will be the final
SP value?
A. 07H
B. 08H
C. 09H
D. 0AH

4 How many memory locations are available for bit- c

addressable operations in internal RAM of 8051?
A. 16
B. 32
C. 64
D. 128

5 The 8051 has a total of 128 bytes of internal RAM. If 32 a

bytes are used for register banks and 16 for bit-
addressable area, how many bytes remain for general-
purpose RAM?
A. 80
B. 64
C. 48
D. 96

6 If the stack pointer is initialized to 07H, how many c

bytes can be safely used in the stack before it collides
with register bank areas (00H–1FH)?
A. 8
B. 16
C. 24
D. 32
7 How many flag bits are available in the 8051's PSW c
(Program Status Word)?
A. 4
B. 5
C. 6
D. 8
8 If Port 0 is used for both input and output, how many c
combinations can its 8 bits represent?
A. 64
B. 128
C. 256
D. 512

9 In the 8051, how many stack levels are available if only b

internal RAM (128 bytes) is used and the stack starts at
08H?
A. 80
B. 104
C. 120
D. 128

10 If you select register bank 2 using PSW, what is the c

starting address for R0 in that bank?
A. 00H
B. 08H
C. 10H
D. 18H

11 An 8051 port is configured for output. If the value a

written to the port is 0xAA, how many pins are set
high?
A. 4
B. 5
C. 6
D. 8

12 If the 8051 accesses external memory using 16-bit d

addressing, how many unique addresses can it
generate?
A. 64
B. 256
C. 1024
D. 65536

13 In the 8051, each PUSH instruction increases the SP by d

1. If SP = 60H and 10 PUSH instructions are executed,
what is the new SP value?
A. 6AH
B. 6BH
C. 6CH
D. 6DH

14 Which of the following is a Special Function Register in d

 8051?
A. A (Accumulator)
B. PCON
C. TMOD
D. All of the above

15 What is the address of the Program Counter in the 8051 c

SFR space?
A. 00H
B. 80H
C. Not in SFR
D. FFH

16 What is the role of the TCON register in the 8051? b

A. Controls port direction
B. Controls timer operation
C. Sets UART baud rate
D. Controls interrupt priority

17 Which signal in the 8051 is used to reset the d

microcontroller?
A. EA
B. PSEN
C. ALE
D. RST

18 What is the function of the EA (External Access) pin in c

8051?
A. Enable ADC
B. Access external RAM
C. Control external program memory access
D. Enable UART

19 Which pin is used to latch the address when using a

external memory with 8051?
A. ALE
B. PSEN
C. RD
D. WR

20 Which addressing mode is used in the instruction MOV b

A, #0x25?
A. Direct
B. Immediate
C. Indirect
D. Indexed

21 What addressing mode is used in MOV A, @R0? b

A. Direct
B. Indirect
C. Immediate
D. Register

22 Which bus system is synchronous and supports multiple c

 masters and slaves?
A. PCI
B. ISA
C. I2C
D. USB

23 In an 8051-based system, the timer is set in Mode 1 d

(16-bit). What is the maximum count value it can hold?
A. 255
B. 512
C. 1024
D. 65535

24 If stack starts at 07H and grows to 2FH (bit-addressable d

end), how many bytes can be used for stack storage?
A. 32
B. 33
C. 40
D. 41

25 An interrupt takes 3 machine cycles to service and b

occurs every 1000 machine cycles. What percentage of
CPU time is spent on interrupts?
A. 0.1%
B. 0.3%
C. 3%
D. 5%

26 If Port 1 is configured as output and the instruction a

MOV P1, #0Fh is executed, how many bits are logic
high?
A. 4
B. 5
C. 8
D. 3

27 How many total flag bits are in the 8051’s PSW and d
TCON registers combined?
A. 6
B. 7
C. 8
D. 9

28 The MOVX instruction in 8051 accesses external c

memory. If external RAM is 64KB, how many address
lines are needed?
A. 8
B. 12
C. 16
D. 32

29 In the 8051, how many instructions use immediate c

addressing? (Assuming standard instruction set of ~111
instructions)
 A. 10
B. 16
C. 24
D. 30

30 PCI uses a 32-bit bus with a frequency of 33 MHz. What c

is the max data transfer rate (MB/s)?
A. 33
B. 66
C. 132
D. 264

31 If an 8-bit I2C register is updated every 10 ms, how c

many times is it updated in 1 minute?
A. 1000
B. 6000
C. 3000
D. 1200

32 In the I2C bus, a 7-bit addressing scheme is used. How b

many unique devices can be addressed?
A. 64
B. 127
C. 128
D. 256

33 If the 8051 crystal frequency is 12 MHz, what is the a

duration of one machine cycle?
A. 1 µs
B. 0.5 µs
C. 2 µs
D. 1.5 µs

34 In 8051, how many machine cycles does a MOV A, #data b

instruction require if each machine cycle takes 1 µs?
A. 1 µs
B. 2 µs
C. 3 µs
D. 4 µs

35 If each SFR is 1 byte and 21 of them are used in a a

program, how much total memory (in bits) is used?
A. 168 bits
B. 168 bytes
C. 210 bits
D. 21 bytes

36 How many SFRs are there in the 8051 microcontroller a

(in the address range 80H to FFH)?
A. 64
B. 128
C. 32
D. 256