3.

8259 cascade or MS mode (done)

4.8259 (158-162,166-167)
5.DMA 8257 pg 200-215 (google/chatgpt/yt)
11.page translation (not in pyq)

Alright! I carefully checked all the papers you uploaded. Here's a chapter-wise segregation of all the
questions, along with their priority (based on how often they appeared across the papers) and
marks:

📚 1. 8086 (Architecture, Modes, Timing Diagrams, Interrupts, etc.)

Question Marks Priority
Draw and explain architecture of 8086. 10 High
Draw and explain Write/Read operation Timing Diagram (Maximum and Minimum
10 each High
mode).
Explain maximum mode and minimum mode of 8086. 10 Medium
Explain the interrupt structure of 8086 (IVT), differentiate hardware/software
10 High
interrupts.
📚 2. Instruction Set and Programming (8086 Instructions + ALPs)
Question Marks Priority
Explain XLAT, DAA, LAHF, AAA instructions. 10 High
Explain STOSB, DAA instructions. 10 Medium
Medium
Assembly language program to exchange contents of two
10
memory blocks.

Assembly language program to search a character in string. High (Repeated in two

10
(Again) papers)
Assembly language program to arrange 10 numbers. 10 Medium
Write ALP for searching a character in a string. 10 High
Write ALP for reversing a string of 10 characters. 10 Medium
Write ALP for arranging numbers in ascending order. 10 Medium
Write ALP for transferring block of data. 10 Medium
📚 3. Memory and Peripheral Interface (8255, 8259, 8257)
Question Marks Priority
Modes of 8255 with block diagram and CWR Initialization. 10 High
Explain 8257 DMA Controller and data transfer modes. 10 Medium
Interface 8257 DMA controller with 8086 and explain. 10 Medium
Explain Initialization Command Words (ICWs) and Operational Command Words
10 High
(OCWs) of 8259 PIC.
Master Slave Mode of 8259 with diagram (slave on IR0, IR4). 10 Medium

📚 4. Intel 80386 (Architecture, Modes, Register Organization, Protection Mechanism)

Question Marks Priority
Differentiate Real Mode, Virtual Mode, Protected Mode of 80386. 10 High
Explain Segment Descriptor of 80386. 10 Medium
Explain Register Organization of 80386. 10 Medium
Question Marks Priority
Explain Protection Mechanism of 80386DX. 10 Medium
Explain EFLAG Register of 80386. 10 Medium

📚 5. Pentium Processor (P1 Architecture, Pipelines, MESI, Branch Prediction)

Question Marks Priority
Explain Floating Point Pipeline of Pentium Processor. 10 Medium
Explain Branch Prediction Mechanism of Pentium Processor. 10 Medium
Explain Cache Organization of Pentium Processor. 10 Medium
Compare Pentium 1, 2, and 3 (also with 80386). 10 High
Explain MESI protocol. 10 Medium

📚 6. Pentium 4 (NetBurst, Hyper-threading)

Question Marks Priority
Draw and explain NetBurst Microarchitecture of Pentium 4. 10 High
Explain Hyper-threading Technology and its use. 10 Medium

🔥 Summary:
 Very High Priority Topics (Must Study First):
o 8086 Architecture + Timing Diagrams
o Interrupt structure of 8086
o Real/Virtual/Protected Mode (80386)
o 8255 Modes + CWR
o ALP: Search a Character
o 8259 ICWs and OCWs
o Compare 80386, Pentium 1, 2, 3
o Pentium 4 NetBurst Architecture
 Medium Priority Topics:
o Floating Point Pipeline of Pentium
o MESI Protocol
o Branch Prediction
o 8257 DMA Controller
o Hyper-threading

🚀 Very High Priority (Most Repeated / Important Topics)

(These must be done first! Expected for sure.)
Topics Chapters
8086 Architecture (with diagram) 8086
Timing Diagrams (Read/Write, Max/Min mode) 8086
Interrupt structure of 8086 (IVT) 8086
Real Mode, Virtual Mode, Protected Mode (Difference) 80386
8255 Modes (Mode 0, Mode 1, Mode 2) with CWR Initialization Memory & Interface
8259 PIC (ICW, OCW, Master-Slave mode) Memory & Interface
Compare 80386, Pentium 1, 2, and 3 Pentium Processor
Pentium 4 NetBurst Architecture (with diagram) Pentium 4
Topics Chapters
Assembly Program: Search a Character in String Programming

📚 High Priority (Often Asked, Slightly Less Repeated)

(Do these after Very High ones.)
Topics Chapters
XLAT, DAA, LAHF, AAA Instructions Explanation Instruction Set
ALP: Reverse a String Programming
Floating Point Pipeline of Pentium Processor Pentium Processor
Branch Prediction Mechanism (Pentium) Pentium Processor
MESI Protocol (Pentium 2/3 Cache Coherency) Pentium Processor
Segment Descriptor (80386) 80386
EFLAG Register (80386) 80386
Interface DMA Controller 8257 with 8086 Memory & Interface

📖 Medium Priority (Bonus Topics - If Time Permits)

(Revise if you finish the above early.)
Topics Chapters
Assembly Program: Arrange Numbers in Ascending Order Programming
Assembly Program: Exchange Memory Blocks Programming
Cache Organization of Pentium Processor Pentium Processor
Hyper-Threading Technology (Pentium 4) Pentium 4
Register Organization of 80386 80386
DMA Controller 8257 Data Transfer Modes Memory & Interface
8257 Control Registers Explanation Memory & Interface
Design 8086-based system (32KB ROM, 16KB RAM) 8086

🔥 In Short:
 First finish Very High priority topics → 8-9 topics.
 Then go to High priority topics → 8 topics.
 Then finish Medium topics if you have extra energy/time → ~8 topics.

Q1. Segment descriptor

In the Intel x86 family (like 80386), memory is divided into parts called segments.
Each segment is like a separate block of memory with a specific purpose (like code, data, or
stack).
A Segment Descriptor is a special data structure (64 bits = 8 bytes) that describes
everything about one memory segment.
It tells the CPU:
 Where the segment starts (Base Address)
 How big it is (Limit)
 What type of segment it is (code/data/system)
 Who is allowed to use it (Privilege Level)
 Whether the segment is present in memory
 Other properties like granularity, access rights, etc.

The Segment Descriptor is divided into the following fields:

1. Segment Base Address (32 bits)
 It tells the CPU the starting address of the segment.
 Memory in 80386 can go up to 4 GB (2³² bytes).
 The base address is split across 3 parts inside the descriptor (low, middle, high).
2. Segment Limit (20 bits)
 Tells the size of the segment.
 20 bits are used, which means the maximum limit could be:
o 1 MB if measured in bytes (G = 0),
o 4 GB if measured in 4 KB blocks (G = 1).
3. Granularity Bit (G)
 Decides how the Segment Limit is counted:
o G = 0 ➔ Limit is in bytes.
o G = 1 ➔ Limit is in 4 KB units.
🔹 Example:
 Limit = 0xFFFFF and G = 1 → Segment size ≈ 4 GB
 Limit = 0xFFFFF and G = 0 → Segment size ≈ 1 MB
4. O (Reserved Bit)
 Reserved by Intel.
 Must be 0 for compatibility.
 CPU ignores it; users/programmers cannot use it.
5. U/AVL (User Available Bit)
 Optional for user programs or operating systems.
 CPU ignores this bit.
 Can be used for any purpose you want.
6. P (Present Bit)
 P = 1 ➔ The segment is in memory and ready to use.
 P = 0 ➔ Segment is not present, and if accessed, a "Segment Not Present" exception
occurs.
7. DPL (Descriptor Privilege Level)
 2 bits wide.
 Defines who can access the segment:
o DPL = 0 ➔ Highest privilege (Kernel)
o DPL = 3 ➔ Lowest privilege (User mode)
Important: Lower DPL values mean higher trust.
8. S (System Bit)
 S = 1 ➔ It's a code or data segment.
 S = 0 ➔ It's a system segment (like a Task State Segment).
9. Type (4 bits)
 Describes the kind of segment:
o For data segments: writable, readable, expand-down, etc.
o For code segments: executable, readable, conforming, etc.
o For system segments: task gates, interrupt gates, etc.
10. A (Accessed Bit)
 CPU automatically sets this bit the first time the segment is accessed (read, written,
or executed).
 Helps the OS know if the segment has been used.

Q2. Register organization of 80386

1. Overview of 80386 Registers

The Intel 80386 microprocessor contains several types of registers, each playing a critical
role in processing and system control. The registers are categorized into:
  General-Purpose Registers (GPRs)
 EFLAGS Register
 Control Registers (CR0, CR2, CR3)
Each category supports operations like arithmetic processing, memory addressing, system
control, and task management.
2. General-Purpose Registers (GPRs)

80386 provides eight 32-bit general-purpose registers.

 These can be accessed as 32-bit, 16-bit, or even 8-bit registers depending on the
instruction.
 Lower 16 bits are directly accessible (like AX, BX, CX, DX, etc.)
 Upper and lower 8 bits are accessible separately (like AH, AL, BH, BL, etc.)
Register Purpose
EAX Accumulator for arithmetic and I/O operations
EBX Base register for memory addressing and indexing
ECX Counter register used in loop and shift operations
EDX Data register used in multiplication, division, and I/O
ESI Source Index for string and memory operations
EDI Destination Index for string operations
EBP Base Pointer used to reference stack frames
ESP Stack Pointer pointing to the top of the stack
🔹 Note:
 E prefix means Extended (for 32-bit).
 For example, AX is the lower 16 bits of EAX.
 AH and AL are the high and low 8 bits of AX, respectively.
3. EFLAGS Register
  A 32-bit register used to store important status and control flags.
 These flags indicate the outcome of operations and control certain features of the
CPU.
Important Groups of Flags:
 Arithmetic Flags: Indicate outcomes of arithmetic operations.
 Control Flags: Control CPU operations like interrupts and debugging.
 System Flags: Used for system-level task switching and virtual memory.
Flag Meaning
CF Carry Flag (bit 0) - Set on arithmetic carry/borrow
PF Parity Flag (bit 2) - Set if the number of set bits is even
AF Auxiliary Carry Flag (bit 4) - Used in BCD operations
ZF Zero Flag (bit 6) - Set if the result is zero
SF Sign Flag (bit 7) - Set if the result is negative
TF Trap Flag (bit 8) - Enables single-step debugging
IF Interrupt Flag (bit 9) - Enables hardware interrupts
DF Direction Flag (bit 10) - Controls string operation direction
IOPL I/O Privilege Level (bits 12-13) - Sets I/O privilege
NT Nested Task (bit 14) - Shows if task switch is active
RF Resume Flag (bit 16) - For debugging
VM Virtual 8086 Mode (bit 17) - Enables running 16-bit applications in 32-bit mode.
4. Control Registers

Control Registers manage operating modes, memory management, and paging in 80386.
Register Purpose
CR0 Controls system modes (Real Mode, Protected Mode, Paging)
Register Purpose
CR1 Reserved (not used)
CR2 Holds the linear address causing a page fault
CR3 Holds the address of the page directory for paging
CR0 - Important Bits:
Bit Meaning
PE (Bit 0) Protection Enable - Enables Protected Mode
MP (Bit 1) Monitor Coprocessor - Controls FPU
EM (Bit 2) Emulation - Software-based FPU
TS (Bit 3) Task Switched - FPU task switching
PG (Bit 31) Paging Enable - Activates paging
CR2:
 Stores the linear address where a page fault happened.
 Useful for debugging and memory management.
CR3:
 Contains the Page Directory Base Address.
 Important for implementing virtual memory through paging.
 Also has cache control bits:
o PWT (Page Write-Through)
o PCD (Page Cache Disable)
Summary Table: 80386 Register Organization
Type Registers Purpose
General EAX, EBX, ECX, EDX, ESI, EDI, EBP,
Data processing, memory addressing
Purpose ESP
Flags Register EFLAGS Status reporting and control
Control Mode control, paging, memory
CR0, CR2, CR3
Registers management

Q3.Cache Organization in Pentium Processor

i) What is Cache Memory?
Cache memory is a small, high-speed storage area located closer to the CPU. Its primary
function is to store frequently accessed data or instructions that the CPU needs. Since
accessing data from the main memory (RAM) is relatively slower, cache helps reduce the
access time by providing faster retrieval of the most used data, thus boosting the
performance of the system.
ii) Importance of Cache Memory
The main objective of the cache memory is to bridge the performance gap between the
processor and the main memory. By storing copies of frequently used data, the cache
memory can quickly supply the processor with the data it needs, rather than waiting for the
slower main memory to provide it. This drastically reduces the CPU's wait time and ensures
that the processor operates at peak efficiency.
iii) Levels of Cache in Pentium Processors
In modern processors like the Pentium series, cache memory is organized in multiple levels
(L1, L2, and L3), each with different sizes and speeds. These levels work together to optimize
performance.
1. L1 Cache:
o Location: L1 cache is located directly inside the CPU, typically integrated into
the processor chip.
o Size: It is the smallest among all cache levels, ranging from 16KB to 64KB.
o Speed: L1 cache is the fastest, offering the shortest access time .(nanosecs)
o Function: The L1 cache is split into two parts: one for data (L1d) and one for
instructions (L1i). This split allows the CPU to fetch data and instructions
simultaneously, improving overall throughput.
2. L2 Cache:
o Location: L2 cache is usually located on the processor chip but outside the
core, though in some newer processors, it is integrated within the core.
o Size: It is larger than L1, with sizes ranging from 128KB to several megabytes
(MB).
o Speed: L2 cache is slower than L1 but faster than the main memory, with
access times typically in the tens of nanoseconds.
o Function: L2 cache acts as a backup for the L1 cache. If data is not found in
the L1 cache, the CPU checks the L2 cache before accessing the main
memory.
3. L3 Cache:
o Location: L3 cache is typically shared across all CPU cores and is located on
the same chip, although in some designs it may be external to the processor.
o Size: L3 cache is the largest of the three, ranging from a few MB to 32MB or
more.
o Speed: L3 cache is slower than L2 but still faster than main memory.
o Function: The L3 cache stores data that is less frequently accessed than that
stored in L1 or L2 but still needs to be available quickly for processing.
iv) Cache Organization Techniques
To effectively utilize cache memory, different organization schemes are used. These schemes
determine how the cache is structured and how data is placed within it. In Pentium
processors, several cache organization techniques are employed:
1. Direct-Mapped Cache:
o Description: In a direct-mapped cache, each block of main memory maps to
exactly one cache line. The mapping is straightforward, using a specific
algorithm to associate each memory block with a unique cache location.
o Advantages: This is a simple and efficient method with fast access times.
o Disadvantages: The main drawback is that it is prone to cache conflicts (also
known as "collision"). If multiple memory blocks map to the same cache line,
one will overwrite the other, leading to inefficient cache use and increased
misses.
 o Example: If two memory addresses, A and B, map to the same cache line,
only one can be stored at any given time, resulting in a cache miss each time
the CPU accesses the other address.
2. Set-Associative Cache:
o Description: A set-associative cache improves upon the direct-mapped
method by dividing the cache into multiple sets, with each set containing
multiple lines (slots). A memory block can map to any line within a specific
set, allowing more flexibility in storing data.
o Ways of Set-Associativity: In this organization, the cache can be 2-way, 4-way,
8-way, or more, depending on how many cache lines each set contains.
A 2-way set-associative cache has two cache lines per set, a 4-way set-
associative cache has four lines, and so on.
o Advantages: This reduces the likelihood of cache conflicts compared to the
direct-mapped cache, resulting in fewer cache misses.
o Disadvantages: The complexity of accessing data increases because the CPU
has to check multiple lines within a set, slightly increasing the access time
compared to a direct-mapped cache.
3. Fully Associative Cache:
o Description: In a fully associative cache, any block of memory can be stored in
any line of the cache. There is no restriction as to which cache line a memory
block can occupy.
o Advantages: This method offers the most flexibility because it eliminates
cache conflicts. If a memory block is not found in the cache, it can be placed
in any available cache line.
o Disadvantages: The main downside is that it is more complex and slower than
direct-mapped or set-associative caches because the cache controller has to
search all the cache lines to find the data. This makes fully associative caches
less feasible for large caches due to their slower performance.
o Use: Fully associative caches are typically used in smaller caches (like L1) to
ensure high speed.
Conclusion
In summary, the Pentium processor employs a multi-level cache system (L1, L2, and L3) to
optimize data access times, enhance CPU performance, and handle the increasing demand
for speed in modern computing. Various cache organization techniques such as direct-
mapped, set-associative, and fully associative caching are used to balance speed, complexity,
and efficiency, with each having its own advantages and disadvantages. Efficient cache
management is essential for maintaining high performance and ensuring that the processor
can operate at maximum speed without being bottlenecked by slower memory access times.
Q4. Explain hyperthreading and its use in pentium4.
Introduction:
 Hyper-Threading Technology (HTT) is a proprietary technology developed by Intel.
 It enables a single physical processor core to behave like two logical processors,
allowing better utilization of CPU resources.
 First introduced in Intel Pentium 4 processors based on the NetBurst architecture.
Working Principle:
 In a conventional processor core, many execution units (like ALUs, FPUs) are idle
when a program stalls (e.g., waiting for data from memory).
 Hyper-Threading fills these idle execution slots by introducing a second thread into
the same core.
 The physical core maintains two separate architectural states (program counter,
registers, etc.) but shares the execution engine.
 This is known as Simultaneous Multithreading (SMT).
Components Duplicated and Shared:
 Duplicated: Program counters, register sets, control logic (to make each thread
appear independent).
 Shared: Execution units (ALUs, FPUs), caches (L1, L2), branch predictors, and buses.

How it appears to the Operating System:

 OS views each logical processor as an independent CPU.
 Example: A Pentium 4 processor with Hyper-Threading will appear as two CPUs in
Task Manager (Windows).

Hyper-Threading Technology (HTT) is a technique developed by Intel that allows a single

physical processor core to behave like two logical processors.
How Hyper-Threading Works:
 Each physical core is split into two logical cores.
 These logical cores share the physical core’s resources, such as execution units and
caches.
 The operating system recognizes the processor as having double the number of
cores, so it can schedule two threads to run simultaneously on one physical core.
 The idea is to utilize idle resources: when one thread is stalled (e.g., waiting for data
from memory), the other can continue executing.
Use in Pentium 4:
 Pentium 4 processors with Hyper-Threading show up as two CPUs in the operating
system.
 It was designed to boost multitasking and improve performance in multi-threaded
applications like video editing, gaming, 3D rendering, etc.
 Performance Gains: By allowing two threads to be processed at once, Pentium 4
could better utilize processor resources, reducing the impact of delays like cache
misses or memory access times.
Example:
 Suppose a Pentium 4 is executing two programs: video encoding and a word
processor.
 Without HTT: CPU would execute instructions from one program, then switch to the
next, causing delay.
 With HTT: Both programs' threads are processed simultaneously, leading to
smoother performance.
Key Features of Hyper-Threading in Pentium 4:
 Simultaneous Multi-threading (SMT): Two threads executed simultaneously on a
single core.
 Improved resource utilization: Unused units like ALUs and FPUs are kept busy by the
second thread.
 Reduced context-switching overhead: Since two threads can run together, switching
between them becomes faster.
Example: Imagine two tasks: one performing addition, the other performing multiplication.
If task one stalls waiting for data, task two can use the available multipliers, ensuring no part
of the processor sits idle.
Advantages:
1. Improved Multitasking:
o Multiple applications (e.g., browser, video editing software) can be run more
smoothly.
2. Better Resource Utilization:
o Otherwise idle units are kept busy, enhancing throughput.
3. Reduced Context Switch Overheads:
o Faster task-switching between threads.
4. Performance Boost in Multithreaded Applications:
o Programs designed for multi-core systems benefit from faster execution.

Limitations:
 Shared resource contention: Two threads sharing same physical resources may cause
performance degradation if not managed properly.
 Not true doubling of performance: Performance gains are typically 20–30%, not
100%, due to resource sharing.
 Requires OS and application support: Only applications designed for multithreading
can fully utilize HTT.

Conclusion:
Hyper-Threading was a major innovation by Intel to extract better performance from single-
core processors.
In Pentium 4, it significantly improved multitasking ability and maintained competitive
performance even when clock speed improvements faced physical limits like power and heat
dissipation.
Q5.Draw and explain Pentium 4 net burst architecture.

Introduction:
 Pentium 4 introduced the NetBurst microarchitecture.
 Focused on achieving very high clock speeds.
 Relied on deep pipelining, high instruction throughput, and aggressive speculation
techniques.
Detailed Explanation of Components:
1. Instruction Fetch Unit:
 Fetches x86 instructions from memory.
 Integrated Branch Prediction Logic predicts outcome of branches.
 Instruction Translation Lookaside Buffer (ITLB) helps map virtual to physical
addresses quickly.
2. Instruction Decode Unit:
 Complex x86 CISC instructions are decoded into simpler RISC-like micro-operations
(uOps).
 Important to support faster and simpler execution later on.
3. Trace Cache:
 Unique feature.
 Caches already-decoded micro-operations (instead of raw instructions).
 Saves time and energy by avoiding re-decode during branch predictions.
4. Out-of-Order Execution Engine:
 Allows instructions to be executed as soon as operands are ready, even if previous
instructions are delayed.
 Boosts CPU efficiency and reduces idle times.
5. Execution Units:
 Include ALUs (for integer operations), FPUs (floating-point operations), SIMD units
(Single Instruction Multiple Data for multimedia).
 Pentium 4 had optimized pipelines for high-speed ALU operations.
6. Retirement Unit:
 Even though instructions are executed out-of-order, results must be committed in
the correct order to maintain program correctness.
 Handles reordering and final output of instructions.
7. Write-Back Stage:
 Results are written back to register file or memory after instruction retirement.

Key Innovations in NetBurst:

 Hyper-Pipelined Technology:
o 20-stage pipeline (later versions had 31 stages).
o Enabled higher clock frequencies but increased latency.
 Rapid Execution Engine:
o ALUs ran at twice the core frequency (e.g., 3 GHz core had ALUs running at 6
GHz).
 Branch Prediction Enhancement:
o Sophisticated predictors to minimize pipeline flushing on mispredictions.
 Streaming SIMD Extensions 2 (SSE2):
o Enhanced SIMD capabilities for multimedia, gaming, and scientific
computations.
Challenges of NetBurst:
 High Power Consumption:
o Very high clock speeds led to high thermal output (e.g., Prescott cores were
notorious for heating).
 Pipeline Stalls:
o Deep pipeline caused severe penalties on branch mispredictions.
 Limited Scaling:
o Despite design intentions, the architecture couldn’t scale beyond ~4 GHz,
leading Intel to shift to Core microarchitecture later.
Conclusion:
NetBurst was an ambitious architecture aiming for record-breaking clock speeds.
While it introduced important technologies like Trace Cache, Hyper-Threading, and deep
pipelines,
it faced challenges like heat generation, power consumption, and diminishing performance
returns, which eventually led Intel to rethink CPU design in later generations.
Q6. Explain Initialization Command Words (ICWs) and Operational Command
Words (OCWs) of 8259 PIC.

Command word of 8259 is divided into two parts :

 Initialization command words(ICW)
 Operating command words(OCW)
Initialization command words(ICW) :
 ICW is given during the initialization of 8259 i.e. before its start functioning.
 ICW1 and ICW2 commands are compulsory for initialization.
 ICW3 command is given during a cascaded configuration.
 If ICW4 is needed, then it is specified in ICW1.
 The sequence order of giving ICW commands is fixed i.e. ICW1 is given first and then
ICW2 and then ICW3.
 Any of the ICW commands can not be repeated, but the entire initialization process
can be repeated if required.
Operating command words(OCW) :
 OCW is given during the operation of 8259 i.e. microprocessor starts using 8259.
 OCW commands are not compulsory for 8259.
 The sequence order of giving OCW commands is not fixed.
 The OCW commands can be repeated.
Initialization sequence of 8259 :

ICW1 command :
 The control word is recognized as ICW1 when A0 = 0 and D4 = 1.
 It has the control bits for Edge and level triggering mode, single/cascaded mode, call
address interval and whether ICW4 is required or not.
  Address lines A7 to A5 are used for interrupt vector addresses.
When the ICW1 is loaded, then the initializations performed are:
 The edge sense circuit is reset because, by default, 8259 interrupt is edge triggered.
 The interrupt mask register is cleared.
 IR7 is assigned to priority 7.
 Slave mode address is assigned as 7.
 When D0 = 0, this means IC4 command is not required. Therefore, functions used in
IC4 are reset.
 Special mask mode is reset and status read is assigned to IRR.
ICW2 command :
 The control word is recognized as ICW2 when A0= 1.
 It stores the information regarding the interrupt vector address.
 In the 8085 based system, the A15 to A8 bits of control word is used for interrupt
vector addresses.
 In the 8086 based system, T6 to T3 bits are inserted instead of A15 to A8 and A10 to
A8 are used for selecting interrupt level, i.e. 000 for IR0 and 111 for IR7.

Initialization of 8259 by ICW1 and ICW2 command words

ICW3 :
ICW3 command word is used when there is more than one 8259 present in the system i.e.
when SNGL bit in ICW1 is 0, then it will load 8-bit slave register.
ICW3
ICW4 :
 When AEOI = 1, then Automatic end of interrupt mode is selected.
 When SFMN = 1, then a special fully nested mode is selected.
 when BUF = 0 , then Non buffered mode is used (i.e. M/S is don’t care) and when
M/S = 1, then 8259 is master, otherwise it is a slave.
 when µPM = 1, then 8086 operations are performed, otherwise 8085 operations are
performed.

ICW4
Operational command word(OCW) :
OCW1 –
It is used to set and reset the mask bits in IMR(interrupt mask register). M 7 – M0 describes 8
mask bits

OCW2 –
It is used for selecting the mode of operation of 8259. Here L2 to L0 are used to describe
interrupt level on which action need to be performed.
Detailed operations are described in the diagram below.
OCW3 –
 When the ESMM (Enable special mask mode ) bit is set, then the SMM bit is don’t
care. If SMM = 1 and ESMM = 1, then 8259 will enter in Special mask mode.
 If ESMM = 1 and SMM = 0, then 8259 will return into normal mask mode.
 RR and RIS are used to give the read register command.
 P = 1 is used for poll command.

Q8.Mesi Protocol Overview (2 marks)

The MESI protocol is used in multiprocessor systems to maintain cache coherence. It defines
four states that a cache line (a unit of cache storage) can exist in:
1. M (Modified): The cache line is only in the current processor's cache and has been
modified. The main memory has outdated data.
2. E (Exclusive): The cache line is only in the current processor's cache, and the data is
consistent with main memory (i.e., unmodified).
3. S (Shared): The cache line may be stored in multiple caches, and the data is
consistent with main memory.
4. I (Invalid): The cache line is not valid (i.e., the data is not stored in the cache).
Functionality of the States (4 marks)
  Modified (M): This state indicates that the cache contains the most recent copy of
the data and is the only one that has the modified copy. No other cache has this
data, and it must be written back to the main memory if it is evicted or replaced.
 Exclusive (E): The cache line is present in only one cache, and it matches the main
memory's value. However, no other processor's cache has the line. This state implies
that the cache is the sole holder of the data, and any write operation by this
processor will change it to the "Modified" state.
 Shared (S): The cache line may be present in multiple caches, but the data is
consistent with main memory. A read operation from this cache does not change the
state, and any processor can read the data, but writes are not allowed in this state.
 Invalid (I): The cache does not contain valid data. A read or write to this cache line is
not allowed, and the cache will need to fetch fresh data from another cache or main
memory.
Transition Between States (3 marks)
The protocol defines state transitions based on interactions between the cache and the
processor. These transitions occur based on:
1. Cache read and write operations: A processor can transition a cache line from
Exclusive or Shared to Modified by writing to the line. Similarly, reads can promote
lines to the Shared or Exclusive state.
2. Bus transactions: Communication between processors on the shared bus can
invalidate or share cache lines. For example, when one processor writes to a cache
line, other caches holding the line may transition to Invalid, forcing them to fetch the
updated data from memory or another cache.
Importance of MESI (1 mark)
The MESI protocol helps in maintaining data consistency across multiple caches in a system
with multiple processors. This is essential for ensuring the accuracy of data while preventing
problems such as race conditions and data corruption.

Q9. Explain DMA 8257 , data tranfer modes and control word register.

DMA stands for Direct Memory Access. It is designed by Intel to transfer data at the fastest
rate. It allows the device to transfer the data directly to/from memory without any
interference of the CPU.
Using a DMA controller, the device requests the CPU to hold its data, address and control
bus, so the device is free to transfer data directly to/from the memory. The DMA data
transfer is initiated only after receiving HLDA signal from the CPU.
How DMA Operations are Performed?
Following is the sequence of operations performed by a DMA −
 Initially, when any device has to send data between the device and the memory, the
device has to send DMA request (DRQ) to DMA controller.
 The DMA controller sends Hold request (HRQ) to the CPU and waits for the CPU to
assert the HLDA.
  Then the microprocessor tri-states all the data bus, address bus, and control bus. The
CPU leaves the control over bus and acknowledges the HOLD request through HLDA
signal.
 Now the CPU is in HOLD state and the DMA controller has to manage the operations
over buses between the CPU, memory, and I/O devices.

Modes of DMA Transfer:

Now after getting some brief idea about DMA and its working it’s the time to analyze Modes
of DMA Transfer.
Mode-1:
Burst Mode –
 In this mode Burst of data (entire data or burst of block containing data) is
transferred before CPU takes control of the buses back from DMAC.
 This is the quickest mode of DMA Transfer since at once a huge amount of data is
being transferred.
 Since at once only the huge amount of data is being transferred so time will be saved
in huge amount.
Pros:
 Fastest mode of DMA Transfer
Cons:
 Less user friendly because during the DMA transfer CPU will be blocked.
Mode-2:
Cycle Stealing Mode –
 Slow IO device will take some time to prepare data (or word) and within that time
CPU keeps the control of the buses.
 Once the data or the word is ready CPU give back control of system buses to DMAC
for 1-cycle in which the prepared word is transferred to memory.
 As compared to Burst mode this mode is little bit slowest since it requires little bit of
time which is actually consumed by IO device while preparing the data.
Pros:
 Most Efficient way for DMA Transfer.
 CPU won’t be blocked entire time.
Cons:
 Rate of DMA Transfer will be less.
Mode-3:
Interleaving Mode –
 Whenever CPU does not require the system buses then only control of buses will be
given to DMAC.
 In this mode, CPU will not be blocked due to DMA at all.
 This is the slowest mode of DMA Transfer since DMAC has to wait might be for so
long time to just even get the access of system buses from the CPU itself.
 Hence due to which less amount of data will be transferred.
Pros:
 CPU will not be blocked at all.
Cons:
 Slowest DMA transfer rate.

Format of the Control Register:

Bit Function Meaning
Memory-to-Memory Enable 1 = Enable memory-to-memory
7
(MEMEN) transfer, 0 = Disable
6 Channel 3 Enable (CH-3 EN) 1 = Enable Channel 3
5 Channel 2 Enable (CH-2 EN) 1 = Enable Channel 2
4 Channel 1 Enable (CH-1 EN) 1 = Enable Channel 1
3 Channel 0 Enable (CH-0 EN) 1 = Enable Channel 0
Bit Function Meaning
Priority Resolver Enable 1 = Enable rotating priority, 0 = Fixed
2
(PRIORITY EN) priority
Extended Write Enable
1 1 = Enable extended write signal
(EXTWR)
Terminal Count Stop (TC 1 = Stop channel after terminal
0
STOP) count, 0 = continue