Basics of I2C:

The I2C Protocol

TIPL 6101
TI Precision Labs – Digital Communications
Prepared by Joseph Wu
Presented by Alex Smith

1
I2C Introduction

I2C Introduction
I2C – Inter Integrated Circuit
Serial data
Created by Philips Semiconductor
CONTROLLER TARGET
DEVICE DEVICE in 1982
(Microcontroller, (Precision Data
DSP) Serial clock Converter)
No license needed since 2006,
many I2C compatible device
manufacturers
Widely used protocol

2
I2C Communication Modes

I2C Mode Speed

Standard Mode 100 kbps
Fast Mode 400 kbps
Fast Mode Plus 1 Mbps
High Speed Mode 3.4 Mbps
Ultra-Fast Mode 5 Mbps

3
I2C Communication Modes

I2C Mode Speed

Standard Mode 100 kbps
Fast Mode 400 kbps
Fast Mode Plus 1 Mbps
High Speed Mode 3.4 Mbps
Ultra-Fast Mode 5 Mbps

Similar in implementation, with different timing requirements

4
I2C Communication Modes

I2C Mode Speed

Standard Mode 100 kbps
Fast Mode 400 kbps
Fast Mode Plus 1 Mbps
High Speed Mode 3.4 Mbps
Ultra-Fast Mode 5 Mbps

Requires controller code

for high speed transfer

5
I2C Communication Modes

I2C Mode Speed

Standard Mode 100 kbps
Fast Mode 400 kbps
Fast Mode Plus 1 Mbps
High Speed Mode 3.4 Mbps
Ultra-Fast Mode 5 Mbps

Write-only, omits some

standard I2C features

6
I2C Physical Layer

VDD
I2C System Features

SDA
Only two communication lines
for all devices on the bus
SCL
(SDA, SCL)
VDD

VDD
VDD

VDD
SDA

SDA

SDA

SDA
SCL

SCL
SCL

SCL
Bi-directional communication,
Mic rocont roller
Controller 1
Mic rocont roller
Controller 2
ADC
Target 1
DAC
Target 2
half duplex
Allows for multiple controllers
GND

GND
GND

GND
and multiple targets
GND

GND Requires pull-up resistors on

both SDA and SCL

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I2C Physical Layer – Open-Drain Connection

VDD When NMOS turns ON,

Pull-up SDA or SCL is pulled low
resistor
SDA,
SCL
SDA, SCL Voltage
VDD
Device
I2C logic

GND

Open-drain GND Quick transition from high to low as NMOS pulls

connection
charge from any bus capacitance from SDA, SCL

8
I2C Physical Layer – Open-Drain Connection

VDD When NMOS turns OFF,

Pull-up SDA or SCL is released and returns
resistor
SDA, high from the pullup resistor
SCL
SDA, SCL Voltage
VDD
Device
I2C logic

GND

Open-drain GND Exponential rise depends on capacitance on SDA

connection
or SCL and pullup resistor size

Low resistance: faster communication, more power

High resistance: slower communication, less power
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I2C Physical Layer – Open Collector vs Push-Pull
VDD VDD Open Drain
• Open drain output can
Open Drain

connect together
Device
SDA
Device
• Any output that goes low
I2C logic I2C logic
On
Any output that goes
low takes priority Off will pull the bus low
Q1 Q2
• This type of connection is
Open-drain
connection
GND GND Open-drain
connection
called a “wired-OR”
VDD VDD
Push Pull

Q1 Q3
Push-Pull
On Off • Open drain output cannot
Device Device
I2C logic
Off On
I2C logic connect together
Bus Contention
Q2 Output at
indeterminate state
Q4 • Connecting outputs together
Push-Pull
Output tries
GND GND Push-Pull can cause a bus contention
Output tries
to dive high
to dive low where the output state is
indeterminate
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I2C Protocol – START and STOP

SDA

SCL

I2C START I2C STOP

A controller device claims the A controller device completes
I2C bus for communication communication with a target
with a target device device and releases the I2C bus
11
I2C Protocol – Logical Ones and Zeros

I2C Logical Bits

SDA is the data line, SCL is
serial clock
SDA
SDA only transitions when
SCL is low (except during
START and STOP)
SDA is high when SCL pulses
is a logical one
SCL
SDA is low when SCLK pulses
is a logical zero

1 0

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I2C Protocol – Timing Diagram

Address Frame Data Frame

SDA A6 A5 A4 A3 A2 A1 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0

SCL

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I2C Protocol – Timing Diagram

Address Frame Data Frame

SDA A6 A5 A4 A3 A2 A1 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0

SCL

An I2C START condition comes from the controller and

sends SDA low before SCL is sent low to claim the bus

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I2C Protocol – Timing Diagram

Address Frame Data Frame

SDA A6 A5 A4 A3 A2 A1 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0

SCL

Seven bits make up the I2C address

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I2C Protocol – Timing Diagram

Address Frame Data Frame

SDA A6 A5 A4 A3 A2 A1 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0

SCL

R/W bit indicates the direction of communication

1: Controller wants to read from the target device
0: Controller wants to write to the target device

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I2C Protocol – Timing Diagram

Address Frame Data Frame

SDA A6 A5 A4 A3 A2 A1 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0

SCL

SDA is pulled down as an ACKT (acknowledge, target)

After the address byte, the target device ACKs the communication

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I2C Protocol – Timing Diagram

Address Frame Data Frame

SDA A6 A5 A4 A3 A2 A1 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0

SCL

Single byte communication for data frames

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I2C Protocol – Timing Diagram

Address Frame Data Frame

SDA A6 A5 A4 A3 A2 A1 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0

SCL

ACK follows each data frame

Write to the target – ACKT comes from the target device
Read from the target – ACKC comes from the controller device

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I2C Protocol – Timing Diagram

Address Frame Data Frame

SDA A6 A5 A4 A3 A2 A1 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0

SCL

I2C STOP condition comes from the controller and sends

SDA high before SCL is sent high to release the bus

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Thanks for your time!
Please try the quiz.

21
Quiz: Basics of I2C: The I2C Protocol
1. Before the address frame of I2C communication, what actions make up the
START condition?
a. The controller device sets the SDA low, and then sets the SCL low
b. The controller device sets the SCL low, and then sets the SDA low
c. The controller device sets the SCL low, and the target device pulls the SDA low as
an ACK

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Quiz: Basics of I2C: The I2C Protocol
1. Before the address frame of I2C communication, what actions make up the
START condition?
a. The controller device sets the SDA low, and then sets the SCL low
b. The controller device sets the SCL low, and then sets the SDA low
c. The controller device sets the SCL low, and the target device pulls the SDA low as
an ACK

SDA

SCL

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Quiz: Basics of I2C: The I2C Protocol
2. In the address frame, after the controller device sends the 7 bit address, what
is the next part of the I2C protocol sent?
a. The target device sends the ACK to acknowledge the communication coming from
the controller device
b. The controller device sends the R/W bit to indicate if it wants to read from or write to
the target device
c. The controller device send a STOP condition before sending the next data

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Quiz: Basics of I2C: The I2C Protocol
2. In the address frame, after the controller device sends the 7 bit address, what
is the next part of the I2C protocol sent?
a. The target device sends the ACK to acknowledge the communication coming from
the controller device
b. The controller device sends the R/W bit to indicate if it wants to read from or write to
the target device
c. The controller device send a STOP condition before sending the next data

A6 A5 A4 A3 A2 A1 A0 R/W

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Quiz: Basics of I2C: The I2C Protocol
3. Because of the NMOS open-drain connection to SDA and SCL, which part of
the communication waveform is faster?
a. The rise time of SDA and SCL
b. The fall time of SDA and SCL
c. The rise time and fall time of SDA and SCL are the same

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Quiz: Basics of I2C: The I2C Protocol
3. Because of the NMOS open-drain connection to SDA and SCL, which part of
the communication waveform is faster?
a. The rise time of SDA and SCL
b. The fall time of SDA and SCL
c. The rise time and fall time of SDA and SCL are the same

SDA, SCL Voltage

VDD

GND

Open-drain connections are actively pulled down

instead and are faster than a resistive pull up

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Quiz: Basics of I2C: The I2C Protocol
4. What is the benefit of having an open-drain connection over push-pull outputs
for I2C?
a. High speed drive for the bus outputs
b. Reduction of bus capacitance
c. Prevents destructive current draw during bus contention when outputs are tied
together

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Quiz: Basics of I2C: The I2C Protocol
4. What is the benefit of having an open-drain connection over push-pull outputs
for I2C?
a. High speed drive for the bus outputs
b. Reduction of bus capacitance
c. Prevents destructive current draw during bus contention when outputs are tied
together

Push-Pull outputs may pull a large current when

the outputs are tied together and there is bus
contention

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Thanks for your time!

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© Copyright 2020 Texas Instruments Incorporated. All rights reserved.
This material is provided strictly “as-is,” for informational purposes only, and without any warranty.
Use of this material is subject to TI’s , viewable at TI.com
Hello, and welcome to our in-depth look at
communications with precision data converters. In this
video, we describe the basics of I2C communication. We'll
discuss the digital lines and the structure of the I2C
protocol. Finally, we’ll give an example of how data is
transmitted to and received from a precision data
converter using I2C. By the end of the presentation, you
should understand the basics of how I2C is implemented,
the structure of the I2C protocol, and how to I2C is used
to read from and write to different peripheral devices.

1
I2C, often called I two C, stands for the Inter-Integrated
Circuit protocol. I2C was invented in 1982 by Philips
Semiconductor (now NXP Semiconductor) as a low speed
communication protocol for connecting microprocessor
controller devices with lower-speed peripheral target
devices. Since 2006, implementing the I2C protocol does not
require a license, and many semiconductor device
companies, including TI, have introduced I2C compatible
devices.
I2C is a widely used protocol for many reasons. It requires
only two lines for communications. Like other serial
communication protocols, there is a serial data line and a
serial clock line. I2C can connect to multiple devices on the
bus with only the two lines. The controller device can
communicate with any target device through a I2C address
sent through the serial data line. I2C is simple and
economical for device manufacturers to implement.

2
I2C has several speed modes starting with the standard
mode, which is a serial protocol that goes up to 100
kilobits per second. This is followed by the Fast mode
which tops out at 400 kilobits per second. Both of these
protocols are widely supported and may be used by the
controller if the bus capacitance and drive capability
allow for the faster speed.

The Fast mode plus allows for communication as high as 1

megabit per second. To achieve this speed, drivers may
require extra strength to comply with faster rise and fall
times.

3
These three modes are relatively similar, using a
communication structure that is the same. However, they
all have different timing specifications for each of the
modes and hardware implementation of the I2C in the
devices are different to accommodate the different
speeds.

4
I2C also has two other modes for higher data rates.

High-Speed Mode has a data rate to 3.4 megabits per

second. In this mode, the controller device must first use
a controller code to allow for high-speed data transfer.
This enables High-speed mode in the target device. This
mode may also require an active pull-up to drive the
communication lines at a higher data rate.

5
Ultra-Fast is the fastest mode of operation and transfers
data up to 5 megabits per second. This mode is write-only
and omits some I2C features in the communication
protocol.

6
One of the reasons that I2C is a common protocol is because there are only two
lines used for communications. The first line is SCL, which is a serial clock primarily
controlled by the controller. SCL is used to synchronously clock data in and out of
the target device. The second line is SDA, which is the serial data line. SDA is used to
transmit data between the controller devices and target devices. In comparison, the
serial peripheral interface or SPI protocol requires four lines for communication. In
addition to the serial clock, the SPI chip select line selects the device for
communication, and there are two data lines, used for input and output from the
target device.
For I2C, the controller device controls the serial clock SCL, the SDA is used to send
data in both directions. The SDA is bi-directional, which means that the controller
devices and target devices can both send data on the line. For example, the
controller device can send configuration data to the target device, and the target
device can send conversion data back to the controller device. Communication is
half duplex where only a controller or a target device is sending data on the bus at a
time.
An I2C controller device starts and stops communication, which removes the
potential problem of bus contention. Also, communication with a target device is
sent through a unique address on the bus. This allows for both multiple controller
and multiple target devices on the I2C bus.
The SDA and SCL lines have an open drain connection to all devices on the bus. This
requires a pull-up resistor to a common voltage supply.

7
The open-drain connection are used on both SDA and SCL
lines and connect to an NMOS transistor. This diagram
shows an I2C device connected to an SDA or SCL line with
a pull-up resistor to VDD. This open-drain connection
controls the I2C communication line and pulls it low or
releases it high.

To set the voltage level of the SDA or SCL line, the NMOS
is set ON or OFF. When the NMOS is ON, the device pulls
current through the resistor to ground. This pulls the line
low. Typically the transition from high to low for I2C is fast
as the NMOS pulls down on SDA and SCL. The speed of
the transition is determined by the NMOS drive strength
and the bus capacitance on SDA or SCL.

8
When the NMOS is OFF, the device stops pulling current, and the
pull-up resistor pulls the SDA or SCL line to VDD. This pulls the line
high. Through control of this open-drain connection, both SDA and
SCL can be set high and low, enabling the I2C communication.
Because of capacitance on the I2C communication line, the SDA or
SCL line discharge with an exponential RC time constant depending
on the size of the pullup resistor and capacitance on the I2C bus.

Typically, pull-up resistors are set between 1 kiloOhm to 10

kiloOhms. The bus speed may help determine the size of the
resistance. With higher resistive values, the I2C bus may pull up the
line slower and limit the bus speed. Capacitance on the bus lines
also has an impact on communication. Higher capacitance limits the
speed of I2C communication, the number of devices, and the
physical distance between devices on the bus.

A smaller pullup resistor has a faster rise time, but require more
power for communication. A larger pullup resistor has a slower rise
time leading to slower communication, but requires less power.

9
One of the benefits of I2C using an open collector is that
bus contention will not put the bus into a destructive
state. With an open drain output many devices can be
connected together. For any output on that connection, if
either output pulls the line low, the line will be low. This
kind of connection is called a “wired-OR”. The output is
the logical OR of the all the outputs when tied together.

If the outputs were a push-pull type, they could not be

tied together without the possibility of a destructive
state. A push-pull output has complementary NMOS and
PMOS transistors that drive the output high or low. Tied
together, if one output is high and another output is low,
this bus contention would have an undetermined state,

10
possibly settling at the mid supply point. Additionally, one
device has NMOS conducting current and another device
has a PMOS conducting current. This would source current
from VDD to GND through a very low impedance path,
conducting as much current as the transistors would allow.
This could be a significant amount of current, potentially
damaging the devices.

10
I2C communication is initiated from the controller device
with an I2C start condition. If the bus is open, an I2C
controller may claim the bus for communication by
sending an I2C START condition. To do this, the controller
device first pulls the SDA low and then pulls the SCL low.
This sequence indicates that the controller device is
claiming the I2C bus for communication, forcing other
controller devices on the bus to hold their
communication.

When the controller device has completed it’s

communication, it releases the SCL high and then
releases the SDA high. This indicates an I2C STOP
condition. This releases the bus to allow other masters to
communicate or to allow for the same controller to
communicate with another device.

11
I2C uses a sequence of ones and zeros for its serial
communication. SDA is used for the data bits while SCL is the
serial clock that times the bit sequence.

A logical one is sent when the SDA releases the line, allowing
the pull-up resistor to pull the line to a high level.

A logical zero is sent when SDA pulls down on the line,

setting a low level near ground.

The ones and zeros are received when SCL is pulsed. For a
valid bit, SDA does not change between a rising edge and
the falling edge of SCK for that bit. If SDA changes between
the rising and falling edges of the SCL, this may be
interpreted as a STOP or START condition on the I2C bus.

12
The I2C protocol is broken up into frames.
Communication starts from the controller device with an
address frame. The address frame is followed by one or
more data frames consisting of one byte. Each frame also
has an acknowledge bit to ensure that the target device
or the controller device has received communication.

13
At the beginning of the address frame, the controller
device initiates a START condition. First, the controller
device pulls SDA low, and then it pulls SCL low for the
START. This allows the controller device to claim the bus
without contention from other controller devices on the
bus.

14
Each I2C target device has an associated I2C address.
When the controller device wants to communicate with a
particular device it uses its device address to send or
receive data in the following I2C frames. The I2C address
consists of 7 bits and devices on the I2C should have a
unique address on the bus.

A 7 bit address would normally imply 2^7 (or 128) unique

addresses. However, there are several reserved I2C
addresses which limits the number of possible devices.
The address is sent with the SDA as the data and SCL as
the serial clock. With this information, you should be able
to read through the I2C communication of a device and
understand what is being sent back and forth from the
controller device and the target device.

15
Following the address is the read – write bit. If this bit is
1, then the controller is asking the target device to read
data from it. If this bit is 0, then the controller is asking to
write data to the target device.

16
After any byte of communication between the controller
device and the target device, one more bit is used to
verify the communication was successful. At the end of
the address byte communication, the target device pulls
down the SDA during the SCL pulse to indicate that it
understood that it was being contacted by the controller.
This is known as an ACKT or acknowledge bit for the
target. If this bit is high, then no target device understood
that it was being contacted and the communication was
unsuccessful. If the bit is high, this is known as a NACK
and there was no acknowledge bit.

17
The address frame is followed by one or more data
frames. These frames are sent one byte at a time.

18
After the data byte is transferred, there is another ACKT,
or acknowledge from the target. If the data byte is a write
to the device, then the target device pulls the SDA low to
ACKnowledge the transfer.
If the data byte is a read from the device, the controller
pulls the SDA low for an ACKC, or acknowledge from the
controller, to acknowledge the receipt of the data.

19
After the communication is completed, the controller
issues an I2C STOP condition. SCL is first released and
then SDA is release. This is the controller indicating that
the communication is completed and the I2C bus is
released.

This is the basic setup for any I2C communication

between the controller device and the target device.
Communication may be comprised of more than on byte
of data, and it may take a write and a read from the
device to read any give device register.

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That concludes this video – thank you for watching! Please try the quiz to
check your understanding of this video’s content.

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