A New AC-DC Converter Using Bridgeless SEPIC

M. R. Sahid*, A. H. M. Yatim*, Taufik Taufik**

*Faculty of Electrical Engineering, Universiti Teknologi Malaysia, 81310 UTM Skudai, Malaysia
** Electrical Engineering Department, California Polytechnic State University, San Luis Obispo, CA 93407, USA
E-mail: rodhi@fke.utm.my, halim@ieee.org, taufik@calpoly.edu

C2 Do2

Abstract-A new bridgeless power factor correction circuit (PFC)

based on single ended primary inductance converter (SEPIC) is L1 C1 Do1 Rload

proposed. The number of component conducted at each

subinterval mode is reduced compared to the existing topologies.
Analysis of the converter operated in discontinuous-conduction S1
Co2
mode (DCM) is discussed. Experimental circuit for the proposed Ds1 L3

converter is developed with universal input voltage capability VAC Co1

for 50V DC output voltage connected to 100W load. The L2

simulation and experimental results are presented to show the Ds2

performances of the proposed circuit. S2

I. INTRODUCTION (a)
L1 Cb1 Do1
The active power factor correction (PFC) circuits are
widely used to effectively draw the energy from the mains via L2
Do2
R
an AC to DC converter. These PFC circuits are normally Ds1
Co
consists of full bridge diode rectifier and DC-DC converter. If Vg S1

only one DC-DC converter is used, then it will be classified

as a single-stage converter while two-stage converter utilizes L3
Ds2
two-DC-DC converter. On the other hand, some PFC circuits
S2
are realized without the full-bridge rectifier circuit, which is Cb2

known as the bridgeless PFC topology. D.M Mitchell has

(b)
proposed the very first bridgeless PFC topology back in 1983 L1 Cb1 Do1
[1]. Actually, these bridgeless PFC circuit combines the
operation of bridge rectifier and DC-DC converter into a Vg L2 R

single circuit. S1
Co

With a simple circuit analysis, it can be identified that the

bridgeless PFC topology namely the Boost bridgeless has less
number of components conduct at each switching cycle Ds2

compared to the conventional Boost PFC circuit. Numerous

works on bridgeless PFC have been reported which focus on
several key issues such as newly proposed topology, higher (c)
L1
power factor and higher efficiency capability [2]-[7],
compared to the conventional PFC converters. Recently, a Vg
Do2
R

new bridgeless PFC circuit based on single ended primary Ds1

Co

inductance converter (SEPIC) has been proposed [8] and the

schematic diagram is depicted in Figure 1(a). It is reported
that this converter offer several advantages as a PFC circuit L3

such as lower input current, easily implemented as isolated S2

Cb2
converter and less electromagnetic inference (EMI).
However, several drawbacks has been identified in this (d)
converter such as; too many components conducted at each Fig. 1. Circuit topology for (a) bridgeless SEPIC PFC in [8], and (b) the
proposed bridgeless SEPIC operated during (c) positive and (d) negative
switching period, isolated gate drive circuit is required to
half line cycle
drive the MOSFETs and two sets of output capacitors at two
different terminals are required. On top of that it is found that In this paper, a new bridgeless power factor correction
the output load terminal is floating between the two separated circuit (PFC) based on SEPIC is proposed. The circuit
output capacitor. diagram of the proposed bridgeless PFC circuit is shown in

978-1-4244-5226-2/10/$26.00 ©2010 IEEE 286

Figure 1(b). Interestingly, the proposed circuit is much cycle will be discussed while the same operation can be
simpler compared to the one proposed in [8] in several performed for the negative half-line cycle. The proposed
aspects namely: (1) less number of components operated at converter will operate in Discontinuous Conduction Modes
each input-voltage cycle, (2) the minimum number of output (DCM) since this type of mode offers several advantages
capacitor (Co) required is one, (3) driving the MOSFETs gate namely capability to operate as PFC is inherent, suitable for
terminal is simpler due to both ‘source’ terminals of the low power applications and lower component stress. As
MOSFETs are connected to a common node and last but not depicted in Figure 2 and Figure 3, the circuit operation of the
least, (4) no gate-driver circuit with isolation is required. proposed converter within each switching period, TS, can be
As the analysis goes deeper, it is found that the circuit divided into three subinterval modes, namely MODE 1
analysis can be divided into two main parts which are the (d1TS), MODE 2 (d2TS) and MODE 3 (d3TS). Throughout the
operation during positive half-line cycle and negative half- circuit analysis, it is assumed that all the components are
line cycle as shown in Fig 1 (c) and (d). During positive half- ideal and lossless.
line cycle, all components will conduct except Ds1, S2, C2,
L3 and Do2. During negative cycle, the components that will In MODE 1, the equivalent circuit is shown in Figure 2(a).
not conduct are Ds2, S1, C1, L2 and Do1. Thus only eight As can be seen, when the upper MOSFET, S1, is turned on,
components will be conducted at each half-line cycle the current from the source, Vg, will flow through the input
compared to eleven in the bridgeless SEPIC converter inductor and continue to S1 and Ds2 before completing the
proposed in [8]. Note that at each half line cycle of the input current path through Vg. At the same time, as shown in
voltage, the proposed converter operated more or less like a Figure 3, the current through L1 increased linearly to its peak
SEPIC DC-DC converter. S1,S2
II. CIRCUIT OPERATION
ON OFF t
In this paper, only the operation during positive half line- 0A

iL1(t)

t
0A

iCb1(t)
0A t

(a)

iL2(t)

t
0A

vL1 (t)
t

(b)
iCo(t)
t
0A

vL2 (t)
t

(c)
d1TS d2TS d3TS
Fig. 2. Equivalent circuit during (a) MODE 1(d1TS), (b) MODE 2(d2TS) and Fig. 3. Waveforms within each switching period for several components.
(c) MODE 3(d3TS).

287
value, 0.35
vg (1)
iL1− peak = (d1TS ) 0.3
L1
CCM/DCM
where d1 is the duty cycle. On the other hand, the second 0.25 Boundary
inductor, L2 discharged its energy linearly to Cb1 and creates

Duty Cycle, D1
a current path to MOSFET S1 before returning to L2. It is 0.2
found that the current flowing through S1 is the addition of
the current through L1 and L2. At this point, the output 0.15 CCM

voltage is equal to the capacitor voltage, Vo, due to output DCM

0.1
diode, Do1 being reverse-biased.
Figure 2(b) shows the circuit in MODE 2. Obviously at this
0.05
mode, S1 is turned off such that no current will flow through Pout=50W
it, but now Do1 is forward-biased. At this point, together with Pout=20W Pout=100W Pout=200W
0
Vg, the current through L1 falls linearly due to the process of 100 150 200 250 300 350
Input Voltage, Vm
discharging its current to the load through iCb1 and iDo1 and
create the return path through Ds2. At the same time, L2 will Fig. 4. Boundary condition for CCM and DCM operation.
also discharge its current linearly to the load through iDo1. Where R is the resistive load value. On the other hand, to
Now, the current flowing through Do1 is the summation of iL1 ensure DCM operation for each switching period, the
and iL2. Thus, the peak current for Do1 is component selection must follow this equation,
⎛v v ⎞ 2 La .
iDo1− pk = i L1− pk + i L 2− pk = d1TS ⎜⎜ g + Cb1 ⎟⎟ (2)
1 − d1 > (6)
⎝ L1 L2 ⎠ RTS
Since vCb1 ≈ v g , equation (2) can be further simplifies to By using equation 5, the boundary between CCM and DCM
operation can be visualized as dotted line shown in Figure 4.
⎛v ⎞ If the converter operates above the dotted line, it will be
iDo1− pk = d1TS ⎜⎜ g ⎟⎟ (3)
operating in the CCM region while operation below the
⎝ La ⎠ dotted line means that it is operating in the DCM region.
where La = L1//L2. In addition, the peak current flowing Thus, from the figure, it is obvious that with any load
through MOSFET S1 is exactly the same with Do1 due to the condition, when the converter operated at certain duty cycle
summation of current at L1 and L2. Interestingly, the current
and input voltage values, it will either operate in CCM or
stress as shown in equation (3) for the proposed circuit is
DCM. In this work, a suitable duty cycle and load condition
similar with Figure 1(a). However, it should be noted that in
should be determined at first place in order to secure DCM
Figure 1(a), the equivalent inductance, La, consist of three
parallel inductors [8], whereas in this circuit, only two operation.
inductors are paralleled. In other word, the La value for the
circuit in Figure 1(a) is smaller than La in the proposed circuit III. RESULTS AND DISCUSSION
which will result smaller current stress in the proposed
circuit. From Figure 3, the d2 width can be determine by The proposed circuit is designed based on the parameters
examining the ripple current at L1 such that, given in TABLE I. All the parameters are selected based on
the equations discussed in previous chapter especially
vg (4) equation (6) which will ensure the circuit operation in DCM.
d2 = d1
(vCb1 + vO − v g ) As can be seen, the proposed circuit is capable to operate with
Finally, in MODE 3, both S1 and Do1 are turned off universal input voltage source ranging from 115 Vrms to 230
resulting only two closed current path which is at the input Vrms at 100W output load condition.
and the output side. It is assumed that at this point, the energy
at L1 and L2 are equal while Vg is equal to VCb1. As a result, TABLE I
the input current is approximately equal to zero. However, an DESIGN PARAMETERS OF THE PROPOSED CICRCUIT
almost DC current exist at this mode and the amount of Input voltage, Vg 115-230Vrms at 50Hz
current at L1 and L2 are equal but on the opposite direction. L1 150uH
By equating the average current of Do1 with the output L2 and L3 70uH
Bulk capacitor, CB1 & CB2 1uF
current, iO=VO/R, the relationship between input and output Output voltage, Vout 50V DC
voltage or normally known as voltage conversion ratio is, Switching frequency, fS 50kHz
vO RTS (5)
Rated output power, Po 100W
M = = d1 Output capacitor, CO 1410uF
vg 2 La

288
 Using PSpice, the input voltage and current waveforms its values are similar to the designed ones. Figure 6 shows the
based on simulation are presented in Figure 5 (a) & (b) for experimental results for the proposed circuit.
115Vrms and 230Vrms input voltage respectively. The From Figure 6(a), the input current follows the voltage
current rigidly follows the input voltage which justifies the waveform and is in phase with the 115 Vrms input voltage
inherent PFC capability when operated at DCM. With the with power factor for this condition recorded at 0.98. The
given duty cycle, the output voltage has successfully achieved same results can be observed for 230 Vrms input voltage in
the desired 50 VDC having a15% voltage ripple at twice the Figure 6(b) with 0.97 power factor. It is proved that without
line frequency, as shown in Figure 5(c). In Figure 5(d), the
input current is obviously operated in DCM, with three modes
of operations. iL1(115Vrms)
The experimental circuit is also developed based on the
design parameters specified in Table 1. All the components
are selected based on its availability in the market such that
4.0A vg(115Vrms)
iL1(115Vrms
0A

-4.0A
200V
(a)

vg(115Vrms)
0V
iL(230Vrms)

-200V
40ms 50ms 60ms 70ms 80ms
(a)
4.0A
iL1(230Vrms) vg(230Vrms)
0A

-4.0A
400V (b)
vg(230Vrms)
0V

-400V
40ms 50ms 60ms 70ms 80ms
(b) vout=50V DC
60V

50V
vout=50V DC
40V
200V
vg(115Vrms)
(c)
0V

iL1
-200V
40ms 50ms 60ms 70ms 80ms
(c)
2.0A iL1
0A
vGS-S1
-2.0A
40V
vGS-S1
20V

0V
67.487ms 67.500ms 67.520ms 67.540ms 67.560ms 67.580ms (d)
(d)
Fig. 5. Simulation results for (a) input voltage and input current with Fig. 6. Experimental results for (a) input voltage and input current with
|Vg|=115Vrms, (b) input voltage and input current with |Vg|=230Vrms, (c) |Vg|=115Vrms, (b) input voltage and input current with |Vg|=230Vrms, (c)
output voltage and, (d) input current and gate drive signal within each output voltage and, (d) input current and gate drive signal within each
switching period. switching period.

289
 any current regulation, the input current is capable to be IV. CONCLUSIONS
reshaped to sinusoidal waveform and in phase with the input
In this paper, a new Bridgeless PFC circuit based on SEPIC
voltage due to DCM operation. In addition, this circuit can
DC-DC converter has been proposed and verified by
achieve high power factor. In Figure 6(c), the output voltage
simulation and experimental works. It is showed that the
is set at 50 VDC with 16% 100 Hz voltage ripple. . Finally, as
depicted in Figure 6(d), the input current waveform shows the proposed circuit is capable to achieve high power factor
operation in DCM with respect to the desired duty cycle value under universal input voltage condition. The capability to
which is used to drive the two MOSFETs, S1 and S2. reshape the input current is inherent when the circuit is
Figure 7(a) shows the efficiency of the proposed converter operated in DCM. This circuit would be most suitable to be
operated at two distinctive input voltage values, 115Vrms and used as a switch mode power supply application for low
230Vrms. As can be seen, the proposed converter is capable power equipments especially those requiring high quality
to obtain high efficiency at light load condition, which is input power
above 90% efficiency for both input voltage values. It should
be noted that this efficiency is including the LC input filter. ACKNOWLEDGMENT
Without this input filter, the efficiency should be higher. On
the power factor values as shown in Figure 7(b), the PF is The authors would like to thank to MOHE (Ministry of
always greater than 0.9 for 115Vrms input voltage but for Higher Education), Malaysia for the financial support.
230Vrms input voltage, the converter suffer low power factor
especially for power below 60W. The power factor values are REFERENCES
measured for the filtered input current. [1] D.M. Mitchell, "AC-DC Converter having an improved power
factor",U.S. Patent 4,412,277, Oct. 25, 1983.
[2] Huber, Laszlo; Jang, Yungtaek; Jovanovic, Milan M.,"Performance
Evaluation of Bridgeless PFC Boost Rectifiers" IEEE Transactions on
Power Electronics, vol. 23, no 3, pp.1381-1390, May 2008.
93.0 [3] D. Tollik and A. Pietkiewicz, “Comparative analysis of 1-phase active
power factor correction topologies,” in Proc. Int. Telecommunication
92.5 Energy Conf., Oct. 1992, pp. 517–523.
92.0 [4] A. F. Souza and I. Barbi, “High power factor rectifier with reduced
conduction and commutation losses,” in Proc. Int. Telecommunication
Efficiency (%)

91.5 Energy Conf., Jun. 1999, pp. 8.1.1–8.1.5.

[5] J. Liu, W. Chen, J. Zhang, D. Xu, and F. C. Lee, “Evaluation of power
91.0 losses in different CCM mode single-phase boost PFC converters via
90.5 115Vrms simulation tool,” in Rec. IEEE Industry Applications Conf., Sep. 2001,
pp. 2455–2459.
90.0 230Vrms [6] J. C. Salmon, “Circuit topologies for PWM boost rectifiers operated
from 1-phase and 3-phase ac supplies and using either single or split dc
89.5 rail voltage outputs,” Proc. IEEE Applied Power Electronics Conf.,
89.0 Mar. 1995, pp. 473–479.
[7] Woo-Young Choi, Jung-Min Kwon, Eung-Ho Kim, Jong-Jae Lee, and
20 40 50 60 80 100 Bong-Hwan Kwon, “Bridgeless Boost Rectifier with Low Conduction
Losses and Reduced Diode Reverse-Recovery Problems” IEEE
Power (W) Transactions on Industrial Electronics, vol. 54, no.2, pp.769-780, April
2007.
(a) [8] Ismail EH. “Bridgeless SEPIC Rectifier With Unity Power Factor and
Reduced Conduction Losses”, IEEE Transactions on Industrial
1.00 Electronics; vol 56, no.4, pp.1147-1157, April 2009.
0.95
0.90
0.85
0.80
PF

0.75
0.70 115Vrms
0.65 230Vrms
0.60
0.55
0.50
20 40 50 60 80 100
Power (W)

(b)
Fig. 7. (a) The efficiency and (b) power factor for the proposed converter at
115Vrms and 230Vrms input voltages.

290