Tutorial 4:

Encoder/Decoders/Multiplexers
The objectives of this tutorial:
CLO4. Analyze and design combinational logic circuits and building blocks.

Q1) [10 points] Implement the following functions using a decoder

Q2) [10 points]

b) You are requested to construct and implement a 5 x 32 decoder using one 2x4 decoder and
four 3x8 decoders. Connect the EN lines, for the rest just write the pin name in the correct place.

Q3) [35 points] Use multiplexers to implement functions:

Symbol Actual circuit Boolean equation

_ _ _
_
Sub = I1 S1 S2 + I2 S1 S2 + I3
S1 S2 + I4 S1 S2

Using a multiplexer to implement the function:

Function F = Σ (0,1,3,4) Proof:
A B C F Thus
F = 1 . A’B’C’ + 1 . A’B’C + 0 . A’BC’ + 1 . A’BC
0 0 0 0 1 + 1 . AB’C’ + 0 .ABC’ + 0 .ABC’ + 0 .ABC
1 0 0 1 1 So
2 0 1 0 0 F = 1 . A’B’C’ + 1 . A’B’C + 1 . A’BC + 1 . AB’C’
In other words:
3 0 1 1 1 F = A’B’C’ + A’B’C + A’BC + AB’C’
4 1 0 0 1 Which is:
5 1 0 1 0 F = Σ (0,1,3,4)
6 1 1 0 0
7 1 1 1 0
Use the same idea to implement the following functions:
Q4) [16 points] An 8x1 multiplexer has inputs A, B and C connected to the selection inputs S2,
S1, and S0 respectively. Determine the Boolean function that the multiplexer implements. The
data inputs through I0 through I7 are as follows:
(a) I1 = I2 = I4 = 0; I3 = I5 = 1; I0 = I7 = D; and I6 = D’

a)
I1 = I2 = I4 = 0; I3 = I5 = 1; I0 = I7 = D; and I6 = D0.

ABCD F
0000 0 F=D
0001 1
0010 0 F=0
0011 0
0100 0 F=0
0101 0
0110 1 F=1
0111 1
1000 0 F=0
1001 0
1010 1 F=1
1011 1
1100 1 F = D’
1101 0
1110 0 F=D
1111 1

F = ∑m (1,6,7,10,11,12,15)
F = A’B’C’D + A’BCD’ + A’BCD + AB’CD’ + AB’CD + ABC’D’ + ABCD
F = A’B’C’D + A’BC + AB’C+ABC’D’+ ACD

(b) I2 = I3 = 0; I4 = I5 = I7 = 1; I0 = I6 = D; and I1 = D’

I2 = I3 = 0; I4 = I5 = I7 = 1; I0 = I6 = D; and I1 = D’
ABCD F
0000 0 F=D
0001 1
0010 1 F = D’
0011 0
0100 0 F=0
0101 0
0110 0 F=0
0111 0
1000 1 F=1
1001 1
1010 1 F=1
1011 1
1100 0 F=D
1101 1
1110 1 F=1
1111 1

F = ∑m (1,2,8,9,10,11,13,14,15)
F = A’B’C’D + A’B’CD’ + AB’C’D’ + AB’C’D+ AB’CD’ + AB’CD+ABC’D + ABCD’ + ABCD
F = B’CD’+B’C’D+AB’+AD+AC

Q5) [9 points] You are requested to construct an 8-to-1 multiplexer with active low enable
using one 2x4 decoders, four 2x1 Multiplexers, and any other necessary logic gates. Connect
the EN lines, for the rest just write the pin name in the correct place.
I0 I1 I2 I3 I4 I5 I6 I7 EN

S0
S1
S2

Out
Q6) [10 point] Find the 1’s and 2’s complement of the following binary numbers?
Value 1’s Complement 2’s Complement
00111000 11000111 11001000
10101010 01010101 01010110
00001111 11110000 11110001
11110000 00001111 00010000
11001100 00110011 00110100

Q7) [10 point] Design an 8-bit adder-subtractor digital circuit?

Q8) [15 point] Using full adders, design a circuit that converts a BCD code into Excess-3 code?
 0 A3 0 A2 1 A1 1
A0

Q9) [15 point] Design a 8 bit adder/subtractor using two 4-bit full adders (IC7483) ?

8 bit add/subtract
Add/Subtract

Cout
Vcc

IC 7483 IC 7483
GND
Cin
Q2) [20 point] Given the circuit for a 2-bit adder :

Ai Bi Ai Bi
Gi Gi

Pi Pi
Ci Ci

Ci+1 Ci+1 Si
Si

a) Assume that carry in for the first bit is 0, use design by contraction to simplify the circuit
for a an 2-bit adder

b) Convert the circuit for 2-bit full adder above into circuit using NAND gates only.
 Step 1, convert all the design into NAND gates only.

Find the simplest form of the circuit and find the Gate Input Cost:

Step2, Assume C0 = 0 and simplify;

Q10) [10 points] Implement the following Boolean function:

F(W, X, Y, Z) = ∑ m(3, 5, 6, 11, 14, 15)

a) Wire the equation for F as a sum of Minterms in algebraic form: (4 marks)

 W X Y Z F
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 0
1 1 1 0 1
1 1 1 1 1

b) Using two 2-to-4 Decoders. (6 marks)

W X Y Z

2x4 Decoder 2x4 Decoder

m3 m2 m1 m0 m3 m2 m1 m0
Q11) [30 points] A T-intersection has three traffic lights at its three directions (i.e., north, east,
and south), where these traffic lights are enabled through a controller. We would like to design
some components of this controller using a decoder and a combinational circuit called “Enabler”,
under the following assumptions.
 The counter component is already given. It follows the gray code sequence: 0000, 0001,
0011, 0010, 0110, 0101, 0100, 1100, 1101, 0000, ….
 The enabler component yields 4-digit BCD numbers from (0 to 9).
 The traffic light system follows the following sequence (north, east, and then south).
 Each traffic light follows the typical sequence of color phases: green, yellow, and red.
 A traffic light remains red once its red light is enabled.

Traffic Light Controller

Counte
Enabler Decoder
r

a) [10 points] Design the Enabler circuit:

Input Output
W X Y Z A B C D
0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
3 0 0 1 1 0 0 1 0
2 0 0 1 0 0 0 1 1
6 0 1 1 0 0 1 0 0
7 0 1 1 1 0 1 0 1
5 0 1 0 1 0 1 1 0
4 0 1 0 0 0 1 1 1
12 1 1 0 0 1 0 0 0
13 1 1 0 1 1 0 0 1
 00 01 11 10 00 01 11 10
00 00
01 01 1 1 1 1
11 1 1 X X 11 X X
10 X X X X 10 X X X X
A=W B = W’X

00 01 11 10 00 01 11 10
00 1 1 00 1 1
01 1 1 01 1 1
11 X X 11 1 X X
10 X X X X 10 X X X X
C = X’Y + W’XY’ D = WZ + X’YZ’ + XYZ + X’Y’Z +
W’XY’Z'

b) [10 points] Integrate the three components of the traffic light controller system (using
only NAND and inverter gates in the enabler circuits).
Q12) [15 points] Design a 4 by 12 decoder using only a single AND gate, 2-to-4 and 3-to-8
decoders with enable inputs.

3-to-8
Decoder

0
0
2 1
21 2
22 3
4
5
6
Enable 7

2-to-4
Decoder
0
0
2 1
21 2
Enable 3
Q13) Design a four-line to two-line priority encoder with active LOW inputs and outputs, with
priority assigned to the higher order data input line. Use Logsim to implement and simulate the
circuit. Add a seven-segment display to display the result.

Solution

Q14) The functional table for the 74148 octal-to-binary encoder is reproduced below.

The circuit diagram below shows two 74148s connected to form an active-LOW input, active-LOW
output digital circuit. Show the logic levels on each line (write 0 or 1 as appropriate) for an input
hexadecimal C (decimal 12). Repeat for an input of 6.
Solution:

Show the logic levels on each line (write 0 or 1 as appropriate) for an input hexadecimal C (decimal
12). Repeat for an input of 6.
Values for input=C(1100).
You can see the output is the 0011 which active LOW, it means it represents 1100 which the binary
code for C (12)
What does the circuit do? It is a 16x4 priority encoder
Why is the EI input of the right encoder tied to ground?

To make the right encoder always enabled, because it has priority so it must always be enabled.
And one of its input lines are active LOW than the encoder to the left will be disabled.
If none of its inputs are active LOW, then it will out 111 and its EO will be 0, which will enable the
left encoder.

What is the purpose of connection between EO of the right encoder to the EI input of the left
encoder.
In order to make the left encoder disabled when the right encoder is in use.
Because the right encoder has priority.

Q15) Suppose a crane has fifteen hydraulic solenoid valves controlling its motion:

Tilt up (fast)
Tilt down (fast)
Tilt up (slow)
Tilt down (slow)
Turn left (fast)
Turn right (fast)
Turn left (slow)
Turn right (slow)
Cable up (fast)
Cable down (fast)
Cable up (slow)
Cable down (slow)
Bucket open (fast)
Bucket open (slow)
Bucket close (slow)
You are part of a team building a remote “pendant” control for this crane with fifteen buttons on it
for controlling each of the fifteen solenoid valves. This control pendant connects to the main system
by a multiconductor cable, but you really want to limit the number of wires in this cable to keep it
as light-weight as possible:

Design a circuit that solves this problem.