SEQUENTIAL CIRCUIT
Introduction:
Sequential circuits consist of a combinational circuit to which memory elements are
connected to form a feedback path.
The memory elements are devices capable of storing binary information.
The binary information stored in these elements at any given time defines the state of
the sequential circuit at that time.
The sequential circuit receives binary information from external inputs (Xn) that,
together with the present state (Yn-1) of the memory elements, determine the binary
value of the outputs (Yn).
f(Xn, Yn-1) = Yn
Latches:
Latch means to hold something or something which do not change.
Latches are the basic building blocks of any flip-flop and they are capable of holding
1-bit until necessary.
Storage elements that operate with signal levels are referred to as latches.
Latches are level sensitive devices.
i) NOR Latch:
The SR latch is a circuit with two-cross-coupled NOR Gates or two-cross-coupled
NANAD Gates and two input labeled ‘S’ for set and ‘R’ for reset.
Outputs Qn and Q’n are the complement of each other in valid scenario.
ii) NAND Latch:
1. SR Flip-Flop:
The operation of the basic SR latch can be modified by providing an additional input
signal that determines (controls), when the state of the latch be changed by
determining whether S and R can affect the circuit.
It consists of the basic SR latch and two additional AND Gates.
The control input ‘E’ acts as an enable signal for the other two inputs (S and R).
The outputs of AND Gates stay at the ‘0’ as long as the enable signal remains at ‘0’ as
one input of AND Gate gets ‘0’, resulting in ‘0’ as output.
When the enable input goes to 1, information from S or R input is allowed to affect
the latch.
Both input and output will at ‘Q’ pin, i.e., Q = Qn, Qn+1, Qn+2, ……
From the function table, we can conclude that:
a) When, S = 0 & R = 0, SR-flip-flop will act as memory element, i.e., Qn+1 = Qn.
b) When, S = 0 & R = 1 (Reset), SR-flip-flop will always give ‘0’.
c) When, S = 1 (Set) & R = 0, SR-flip-flop will always give ‘1’.
d) When, S = 1 (Set) & R = 1 (Reset), SR-flip-flop get confused, means we get
‘Don’t-Care’ condition.
Here ‘X’ is the ‘Don’t-Care’ condition.
Types of Modes:
i) Transparent Mode:
A system is said to be in transparent mode, when enable-line (clock) is set (E = 1).
Means flip-flop will respond according to the values at S & R pins.
ii) Latch Mode:
A system is said to be in latch mode, when enable-line (clock) is disabled (E = 0).
In this mode, the flip-flop will work as a memory element.
The value stored in flip-flop will not be affected by the values at S & R pins.
Means, value inside the flip-flop remain unchanged, irrespective of the values of S &
R.
In this mode, out system will not affect the flip-flop.
Types of Clock Triggering:
1) Negative Edge Triggering 3) Negative Level Triggering
2) Positive Edge Triggering 4) Positive Level Triggering
Order of Priority:
Types of SR Flip-Flop based on Clock Triggering:
Variation of Waveform According to The Clock:
Note-1:
Edge triggering is always preferred over level triggering, because in edge triggering
system is in transparent mode for very less amount of time. So, system will be stable.
The key to the proper operation of a flip-flop is to trigger it only during a signal
transition (edge).
A clock pulse goes through two transitions: from ‘0’ to ‘1’ (+ve edge) and the return
from ‘1’ to ‘0’ (-ve edge).
To produce a flip-flop that triggers only during a signal transition (edge) (from ‘0’ to
‘1’ or from ‘1’ to ‘0’) of the synchronization signal (clock) and is disabled during the
rest of the clock pulse.
Note-2:
Latches are the basic circuits from which all flip-flops are constructed.
The storage elements (memory) used in clocked sequential circuits are called flip-
flops.
A flip-flop is a binary storage device, capable of storing one bit of information. In a
stable state, the output of a flip-flop is either ‘0’ or ‘1’ (it is called bi-stable multi-
vibrator).
A flip-flop is said to be stable if it has complementary behavior (Q and Q’).
Latches are level sensitive devices while flip-flops are edge sensitive devices.
Storage elements that operate with signal levels are referred to as latches and those
who controlled by a clock transition (edge) are flip-flops.
Note-3:
Flip-flops can be either level-triggered (asynchronous, transparent or opaque) or edge-
triggered (synchronous or clocked).
The term flip-flop has historically referred to both level-triggered and edge-triggered
circuits that store a single bit of data using gates.
2. JK Flip-Flop:
SR flip-flop fails when Both S & R = 1, the result is invalid output.
To resolve the problem, we use JK flip-flop
Here, we take feedback from outputs.
3. T (Toggle) Flip Flop:
The T (Toggle) flip-flop is a complementing flip-flop and can be obtained from a JK
flip-flop when inputs J and K are tied together.
4. D (Delay) Flip-Flop:
The D (data/delay) flip-flop, tracks the input at D and produces the same value as
output.
Flip-Flop Conversion:
We will require the characteristics table of target flip-flop.
We will require the excitation table of the given flip-flop.
Determine the excitation values for characteristics table.
Obtain the expressions for input of given flip-flop in terms of target.
COUNTERS
Introduction:
A counter is a sequential circuit that goes through a predetermined sequence of binary
states on the application of input pulses.
A counter that follows the binary number sequence is called a binary counter.
A ‘n-bit’ binary counter consists of ‘n-flip-flops’ and can count in binary from ‘0’ to
(2n ‒ 1).
Counters are available in two categories:
1. Synchronous Counter
2. Asynchronous Counter (Ripple Adder)
1. Synchronous Counter:
In synchronous counter, all flip-flops are triggered with same clock simultenously.
Synchronous counters are also called parallel counters.
Tdelay = TFF + TCC
Example-1:
Example-2:
Example-3:
Example-4:
Example-5:
Example-6:
Note:
We will take the help of excitation table of the flip-flops for the construction of
counter.
2. Asynchronous Counter (Ripple Counter):
A binary ripple counter consists of a series connection of complementing flip-flops,
with the output of each flip-flop connection to the input of the next higher order flip-
flop.
The flip-flop holding the least significant bit receives the incoming count pulses.
Output of each flip-flop connected to input of clock of next higher flip-flop.
Flip-Flop Representation:
Example-1:
Example-2:
Note:
Difference between Synchronous & Asynchronous Counters:
Self-Starting Counter:
A counter is said to be self-starting, if it provides the counting sequence irrespective
of initial state.
Free Running Counter:
A counter is said to be free running, if it maintains all possible states in the counting
sequence.
Conclusion:
If a counter is free running, it is also self-starting, vice-versa may or may not be true.
Examples:
REGISTERS
Introduction:
Registers are basically storing devices which are also designed using basic element
called flip-flops.
D-flip-flops are most popular choice for register because they don’t perform any
functionality and output is simply based on current input. So, they act as a buffer.
Apart from storing registers sometimes also be used in performing basic mathematical
operations like multiply by 2, by left shift and dividing by 2, by right shift.
Types of Registers:
There are four types of registers:
1. Serial In Serial Out Register (SISO)
2. Serial In Parallel Out Register (SIPO)
3. Parallel In Serial Out Register (PISO)
4. Parallel In Parallel Out Register (PIPO)
1. Serial-In-Serial-Out Shift Register (SISO):
The shift register, which allows serial input (one bit after the other through a single
data line) and produces a serial output is known as serial-in-serial-out shift register
(SISO).
The circuit consists of four D-flip-flops which are connected serially.
Since, there is only one output, the data leaves the shift register one bit at a time in a
serial pattern, thus the name serial in serial out register (SISO).
The main use of a SISO is to act as a delay element.
In SISO, registers to provide ‘n-bit’ data serially in, it requires ‘n-clock’ pulse and to
provide serial output, it requires (n-1) clock pulse.
2. Serial-In-Parallel-Out Shift Register (SIPO):
The shift register, which allows serial input (one bit after the other through a single
data line) and produces a parallel output is known as serial-in-parallel-out shift
register.
The circuit consists of four D-flip-flops which are connected serially.
The output of the first flip-flop is connected to the input of the next flip-flop and so
on.
In SIPO, registers to provide ‘n-bit’ data serially in, it requires ‘n-clock’ pulse and to
provide parallel output, it requires ‘0’ clock pulse.
3. Parallel-In-Serial-Out Shift Register (PISO):
The shift register, which allows parallel input (data is given separately to each flip-
flop and in a simultaneous manner) and produces a serial output is known as parallel-
in-serial-out shift register.
The circuit consists of four D-flip-flops, which are connected with each other.
The clock input is directly connected to all the flip-flops but the input data is
connected individually to each flip-flop through a multiplexer at the input of every
flip-flop.
The output of the previous flip-flop and parallel data input are connected to the input
of the MUX and the output of the MUX is connected to the next flip-flop.
A parallel-in-serial-out (PISO) shift register is used to convert parallel data to serial
data.
For parallel input of data, put P = 0.
For serial output of data, put P = 1.
In PISO register, to provide parallel input, it requires ‘1’ clock pulse and to provide
serial output, it requires (n-1) clock.
4. Parallel-In-Parallel-Out Shift Register (PIPO):
The shift register, which allows parallel input (data is given separately to each flip-
flop in simultaneously manner) and also produces a parallel output is known as
parallel-in-parallel-out shift register.
The circuit consists of four D-flip-flops which are connected with each other.
In this type of register, there are no interconnection between the individual flip-flops
since no serial shifting of data is required.
Data is given as input separately for each flip-flop and in the same way, output also
collected individually from each flip-flop.
A parallel in parallel out (PIPO) shift register is used as a temporary storage device
and like SISO shift register it acts as a delay element.
For parallel input, it requires ‘1’ clock pulse and for parallel output, it requires ‘0’
clock.
Number of Clocks:
4-Bit Ring Counter:
A ring counter is a circular shift register with only one flip-flop being set at any
particular time, all others are cleared.
The single bit is shifted from one flip-flop to next to produce the sequence of timing
signals.
Output of the last flip-flop is connected to the input of the first flip-flop in case of ring
counter.
The circuit consists of four D-flip-flops, which are connected with each other.
Number of states (counting sequence) in ring counter = number of flip-flops.
If D3D2D1D0 = 0 0 0 0, there will be only one state (sequence), i.e., 0 0 0 0.
Number of unused states in ring counter = (2n ‒ n).
Johnson Counter:
Also called Twisted Ring Counter/ Switch Tail Ring Counter/ Walking Ring Counter.
A ‘n-bit’ ring counter circulates a single bit among the flip-flops to provide ‘n-states’.
The number of states can be doubled, if the shift register is connected as a switch-tail
ring counter.
A switch-tail ring counter is a circular shift register with the complemented output of
the last flip-flop connected to the input of the first flip-flop.
Number of states (counting sequence) in ring counter = 2*(number of flip-flops).
Number of unused states in ring counter = (2n ‒ 2n).
Example:
