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DLD Unit Ii

The document discusses parity bit generators and checkers, detailing even and odd parity systems for 3-bit binary inputs. It includes truth tables and Boolean expressions for both even and odd parity generators and checkers, explaining how they detect errors in transmitted data. Additionally, circuit diagrams for the parity generator and checker are provided to illustrate their implementations.

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0% found this document useful (0 votes)
51 views127 pages

DLD Unit Ii

The document discusses parity bit generators and checkers, detailing even and odd parity systems for 3-bit binary inputs. It includes truth tables and Boolean expressions for both even and odd parity generators and checkers, explaining how they detect errors in transmitted data. Additionally, circuit diagrams for the parity generator and checker are provided to illustrate their implementations.

Uploaded by

sarithavempati6
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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fig: 4 to 16 Decoder circuit

Fig: BCD to Decimal Decoder Circuit Diagram


BCD to 7-Segment Decoder
BCD to 7-Segment Decoder
Parity Bit Generator
There are two types of parity bit generators based on the type of parity bit being generated. Even
parity generator generates an even parity bit. Similarly, odd parity generator generates an odd
parity bit.

Even Parity Generator


• Now, let us implement an even parity generator for a 3-bit binary input, ABC. It
generates an even parity bit, P.

1. If the number of 1’s in the Input are even number(ex:2,4,6), then parity bit is 0

2. If the number of 1’s in the Input are odd number(ex:1,3,5), then parity bit is 1

3 Bit EVEN Parity Generator truth table Boolean Expression

Binary Input Even Parity bit From the above Truth table, we can write
ABC P
the Boolean function
000 0 P= A`B`C+ A`BC`+AB`C`+ABC
001 1
010 1 P=A`(B`C+BC`)+A(B`C`+BC)
011 0
P=A`( B ⊕ C)+A(BΘC)
100 1
101 0 P=A`( B ⊕ C)+A( B ⊕ C)`
110 0
111 1 p =A ⊕ B ⊕ C

Fig:3 Bit Even Parity Generator Circuit Using 2-input XOR Gate
Parity Checker
 It is a logic circuit that checks for possible errors in the transmission.
 This circuit can be an even parity checker or odd parity checker depending on the type of
parity generated at the transmission end.

Even Parity Checker


Even parity checker checks error in the transmitted data, which contains message bits along
with even parity.

3 Bit Even Parity Checker


• Suppose at the transmitting end, even parity bit is generated, and we have three input
message signals A,B,C and one parity bit P.

• It generates an even parity check bit, Cp. This bit will be 0, if the received data contains
an even number of 1’s. That means, there is no error in the received data

• This even parity check bit Cp will be 1, if the received data contains an odd number of
1`s. That means, there is an error in the received data.

3 Bit Even Parity checker truth table

4-Bit Received Message Parity Error Check


ABCP Cp
0000 0
0001 1
0010 1
0011 0
0100 1
0101 0
0110 0
0111 1
1000 1
1001 0
1010 0
1011 1
1100 0
1101 1
1110 1
1111 0
Boolean Expression

From the above Truth table, we can write the Boolean function

Cp= A`B`C`P+A`B`CP`+A`BC`P`+A`BCP+AB`C`P`+AB`CP+ABC`P+ABCP`

Cp=A`B`(C`P+CP`)+A`B(C`P`+CP)+AB`(C`P`+CP)+AB(C`P+CP`)

Cp=A`B`(C ⊕ P)+A`B(C Θ P)+AB`(C Θ P)+AB(C ⊕ P)

Cp=(C ⊕ P)(A`B`+AB)+(C Θ P)(A`B+AB`)

Cp=(C ⊕ P) (AΘB)+(C Θ P) (A⊕B)

Cp=(C ⊕ P) (A ⊕ B)`+(C ⊕ P)` (A⊕B)

Cp= (C ⊕ P) ⊕(AΘB)

Cp= (A ⊕ B ⊕ C ⊕ P)

Fig: 3 Bit Even Parity Checker Circuit Using 2-input XOR Gate
Odd Parity Generator

• Now, let us implement an odd parity generator for a 3-bit binary input, ABC.
It generates an odd parity bit, P.

1. If the number of 1’s in the Input are even number (ex:2,4,6), then parity bit is 1

2. If the number of 1’s in the Input are odd number (ex:1,3,5), then parity bit is 0

3 Bit ODD Parity Generator truth table Boolean Expression

Binary Input ODD Parity bit From the above Truth table, we can write
ABC P
the Boolean function

000 1 P= A`B`C`+ A`BC+AB`C+ABC`


001 0
P= (A`B`+AB)C`+(A`B+AB`)C
010 0
011 1 P= (AΘB)C`+( A ⊕ B)C
100 0 P= (A ⊕ B)`C`+(A ⊕ B)C
101 1
110 1 P= (A ⊕ B )Θ C

111 0

Fig:3 Bit ODD Parity Generator Circuit


Odd Parity Checker
Odd parity checker checks error in the transmitted data, which contains message bits along
with odd parity.

3 Bit Odd Parity Checker


• Suppose at the transmitting end, odd parity bit is generated, and we have three input
message signals A,B,C and one parity bit P.

• The parity checker circuit is fed all these four bits to check for possible errors.

• It generates an odd parity check bit, Cp. This bit will be 0, if the received data contains
an odd number of 1’s. That means, there is no error in the received data

• This odd parity check bit Cp will be 1, if the received data contains an even number of
1`s. That means, there is an error in the received data.

3 Bit Odd Parity checker truth table

4-Bit Received Message Parity Error Check


ABCP Cp
0000 1
0001 0
0010 0
0011 1
0100 0
0101 1
0110 1
0111 0
1000 0
1001 1
1010 1
1011 0
1100 1
1101 0
1110 0
1111 1
Boolean Expression

From the above Truth table, we can write the Boolean function

Cp= A`B`C`P`+A`B`CP+A`BC`P+A`BCP`+AB`C`P+AB`CP`+ABC`P`+ABCP

Cp=A`B`(C`P`+CP)+A`B(C`P+CP`)+AB`(C`P+CP`)+AB(C`P`+CP)

Cp=A`B`(CΘP)+A`B(C⊕P)+AB`(C⊕P)+AB(CΘP)

Cp=(CΘP)(A`B`+AB)+(C⊕P)(A`B+AB`)

Cp=(CΘP) (AΘB)+(C⊕P) (A⊕B)

Cp=(CΘP) (AΘB)+(CΘP)` (AΘB)`

Cp= (CΘP) Θ(AΘB)

Cp= (AΘB Θ CΘP)

Fig: 3 Bit ODD Parity Checker Circuit Using 2-input XNOR Gate
Fig: BCD to Excess-3 Code Converter

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