Unit-V

What Is Logic Synthesis?

• Logic synthesis is the process of converting a high-
level description of the design into an optimized gate-
level representation, given a standard cell library and
certain design constraints.
• A standard cell library can have simple cells, such as
basic logic gates like and, or, and nor, or macro cells,
such as adders, muxes, and special flipflops.
• A standard cell library is also known as the
technology library.
 Impact of logic synthesis
• For large designs, manual conversion was prone to
human error.
• The designer could never be sure that the design
constraints were going to be met until the gate-level
implementation was completed and tested.
• A significant portion of the design cycle was dominated
by the time taken to convert a high-level design into
gates.
• If the gate-level design did not meet requirements, the
turnaround time for redesign of blocks was very high.
• What-if scenarios were hard to verify.
• Each designer would implement design blocks
differently.
• If a bug was found in the final, gate-level design,
this would sometimes require redesign of
thousands of gates.
• Design reuse was not possible. Designs were
technology-specific, hard to port,
• and very difficult to reuse.
• High-level design is less prone to human error because designs
are described at a higher level of abstraction.

• Conversion from high-level design to gates is fast.

• What-if scenarios are easy to verify.

• Logic synthesis tools optimize the design as a whole. This

removes the problem with varied designer styles for the
different blocks in the design and suboptimal designs.

• If a bug is found in the gate-level design, the designer goes

back and changes the high-level description to eliminate the
bug.

• Logic synthesis tools allow technology-independent design.

•
Verilog Constructs
• Hence, there are restrictions on the way these
constructs are used for the logic synthesis tool.

• For example, the while and forever loops must be broken

by a @ (posedge clock) or @ (negedge clock) statement
to enforce cycle-by-cycle behavior and to prevent
combinational feedback.

• Another restriction is that logic synthesis ignores all

timing delays specified by #<delay> construct.

• Therefore, pre- and post-synthesis Verilog simulation

results may not match.
 Interpretation of a Few Verilog
Constructs
• The assign statement
The assign construct is the most
fundamental construct used to describe
combinational logic at an RTL level.
Ex: assign out = (a & b) | c;

Assign op = s?a:b
 The if-else statement
Single if-else statements translate to
multiplexers where the control signal is
the signal or variable in the if clause.

if(s)
out = i1;
else
out = i0;
 The case statement
• The case statement also can used to infer
multiplexers. The above multiplexer would
have been inferred from the following
description that uses case statements:

case (s)
1'b0 : out = i0;
1'b1 : out = i1;
endcase

• Large case statements may be used to infer

large multiplexers.
 for loops
• The for loops can be used to build cascaded
combinational logic.
• For example, the following for loop builds an 8-bit full
adder:

c = c_in;
for(i=0; i <=7; i = i + 1)
{c, sum[i]} = a[i] + b[i] + c; // builds an 8-bit ripple adder
c_out = c;
 The always statement
• The always statement can be used to infer
sequential and combinational logic.
• For sequential logic, the always statement
must be controlled by the change in the
value of a clock signal clk.
• For combinational logic, the always
statement must be triggered by a signal
other than the clk, reset, or preset.
Synthesized Design Flow: RTL to
Gates
• The designer describes the design at a high level by using RTL
constructs.
• The RTL description is converted by the logic synthesis tool to
an unoptimized, intermediate, internal representation is called
translation.
• Design constraints such as area, timing, and power are not
considered in the translation process.
• In logic optimization, The logic is now optimized to remove
redundant logic.
• In this technology mapping phase, the synthesis tool takes the
internal representation and implements the representation in
gates, using the cells provided in the technology library.
 Modeling Tips for Logic Synthesis
• Use meaningful names for signals and variables

• Avoid mixing positive and negative edge-triggered flipflops

• Use basic building blocks vs. use continuous assign

statements
• Instantiate multiplexers vs. Use if-else or case statements

• Use parentheses to optimize logic structure

• Use arithmetic operators *, /, and % vs. Design building

blocks
• Be careful with multiple assignments to the same variable.
 Types of Delay Models
There are three types of delay models used
in Verilog
• Distributed Delay
• Lumped Delay
• Pin-to-Pin Delays
 Distributed Delay
• Distributed delays can be modeled by
assigning delay values to individual gates
or
• By using delay values in individual assign
statements.
//Distributed delays in
gate-level modules
module M1(out, a, b, c, d);
output out;
input a, b, c, d;
wire e, f;
//Delay is distributed to
each gate.
and #5 al(e, a, b);
and#7 a2(f, c, d);
and #4 a3(out, e, f);
endmodule
//Distributed delays in data flow definition of
a module
module M (out, a, b, c, d);
output out;
input a, b, c, d;
wire e, f;
//Distributed delay in each expression
assign #5 e = a & b;
assign#7 f = c & d;
assign #4 out = e & f;
endmodule
 Lumped Delay
• Lumped delays are specified on module
basis.
• They can be specified as a single delay on
the output gate of the module.
• The cumulative delay of all paths is
lumped at one location.
 //Lumped Delay Model
module M (out, a, b, c, d) ;
output out;
input a, b, c, d;
wire e, f ;
and a1 (e, a, b) ;
• The maximum delay from any and a2(f, c, d) ;
input to the output of the above and #11 a3 (out, e, f) ; //
figure which is 7+4=11 units. delay only on the output
• The entire delay is lumped into the gate
output gate. After a delay, primary
output changes after any input to endmodule
the module M changes.
 Pin-to-Pin Delays
• Another method of
delay specification for a
module is pin-to-pin
timing.
• Delays are assigned
individually to paths
from each input to each
output.
• Thus, delays can be
separately specified for
each input/output path.
• Pin-to-pin delays for
standard parts can be
directly obtained from
data books.
• Pin-to-pin delays for
modules of a digital
circuit are obtained by
circuit
• characterization, using
a low-level simulator
like SPICE.
• Although pin-to-pin delays are very
detailed, for large circuits they are easier
to model than distributed delays because
the designer writing delay models needs
to know only the I/O pins of the module
rather than the internals of the module.
• The internals of the module may be
designed by using gates.
• Data flow, behavioral statements, or
mixed design, but the pin-to-pin delay
specification remains the same.
• Pin-to-pin delays are also known as path
delays.
 Path Delay Modelling
• Specify Blocks
• A delay between asource (input or inout) pin and a
destination (output or inout) pin of a module is called
amodule pathdelay.
• Path delays are assigned in Verilog within the
keywords specify and endspecify.
• The statements within these keywords constitute a
specify block.
Specify blocks contain statements to do the following:
• Assign pin-to-pin timing delays across module paths
• Set up timing checks in the circuits
• Define specparam constants
//pin-to-pin delays
module M (out, a, b, c, d);
output out;
input a, b, c, d;
wire e, f;
//Specify block with path delay
statements
specify
(a => out) = 9;
(b => out) = 9;
(c => out) = 11;
(d => out) = 11;
endspecify
//gate instantiations
and a1(e, a, b) ;
and a2(f, c, d);
and a3(out, e, f);
endmodule

The specify block is a

separate block in the
module and does not
appear under any other
block, such as initial or
always.
 Parallel connection
• A parallel connection is specified by the
symbol =>
• Usage: ( <sourcefield> =>
<destinationfield>) = <delay-value>;
• In a parallel connection, each bit in source
field connects to its corresponding bit in
the destination field.
• If the source and the destination fields are
vectors, they must have the same number
of bits. Otherwise, there is a mismatch.
 between the source field
and destination field are
connected in a parallel
connection.
//bit-to-bit connection. both a
and out are single-bit
(a => out) = 9;
//vector connection. both a and
out are 4-bit vectors a[3 : 0] ,
out [3 : 0]
//a is source field, out is
destination field.
(a => out) = 9;
//the above statement is
shorthand notation
//for four bit-to-bit connection
statements
(a[O] => out[O]) = 9;
(a[l] => out[l]) = 9;
(a[2] => out[2]) = 9;
 //illegal connection
a[4:0] is a 5-bit vector, out[3:0] is 4-bit vector
//Mismatch between bit width of source and
destination fields
(a => out) = 9; //bit width does not match.
Full connection
A full connection is specified by the symbol *> and is
used as shown below.
Usage: (<sourcefreld> *><destination-field> ) =<delay-
value>;
In a full connection, each bit in the source field
connects to every bit in the
destination field.
If the source and the destination are vectors, then they
need not have the same number of bits.
A full connection describes the delay between each bit
of the source and every bit in the destination.
//Full Connection
module M (out, a, b, c, d);
output out;
input a, b, c, d;
wire e, f;
//full connection
specify
(a,b *> out) = 9;
(c,d *> out) = 11;
endspecify
and a1 (e, a, b) ;
//Full Connection
and a2(f, c, d);
and a3(out, e, f);
endmodule
 specparam statements
Special parameters can be declared for use inside a
specify block.
They are declared by the keyword specparam.
The specparam values are often used to store values for
non simulation tools, such as delay calculators, synthesis
tools, and layout estimators.
//Specify parameters using specparam statement
specify
//define parameters inside the specify block
specparam d_to_q = 9;
specparam clk_to_q = 11;
(d=>q)= d_to_q;
(clk=>q)= clk_to_q;
endspecify
 Conditional path delays
• Based on the states of input signals to a circuit, the pin-to-pin
delays might change.
• Verilog allows path delays to be assignedconditionally, based on
the value of the signals in the circuit.
• A conditional path delay is expressed with the if conditional
statement. A conditional path delay is expressed with the if
conditional statement.
• The operands can be scalar or vector, module input or inout ports
or their bit-selects or part-selects, locally defined registers or nets
or their bit-selects or part-selects, or compile time constants
(constant numbers and specify block parameters).
• The conditional expression can contain any logical, bitwise,
reduction, concatenation, or conditional operator.
• The else construct cannot be used.
• Conditional path delays are also known asstate dependent path
delays(SDPD).
//Conditional Path Delays if (~(b & C)) ((b) => out) =
module M (out, a, b, c, d); 13;
output out; //Use concatenation
input a, b, c, d; operator.
wire e, f; //Use Full connection
//specify block with conditional if {{c,d} == 2’b01}
pin-to-pin timing
specify //Conditional Path Delays
//different pin-to-pin timing (c,d *> out) = 11;
based on state of signal a. if ({c,d} != 2’b01)
if (a) (a => out) = 9; (c,d *> out) = 13;
if (~a) (a => out) = 10;
//Conditional expression
endspecify
contains two signals b , c. and a1(e, a, b) ;
//If b & c is true, delay = 9, and a2(f, C, d);
//otherwise delay = 13. and a3(out, e, f);
if (b & C) (b => out) = 9; endmodule
 Rise, fall, and turn-off delays
//Specify one delay only. Used for all transitions
specparam t-delay = 11;
(clk => q) = t-delay;
//Specify two delays, rise and fall
//Rise used for transitions 0->l, 0->z, z->l
//Fall used for transitions 1->0, l->z, z->0
specparam t-rise = 9, t-fall = 13;
(clk => q) = (t-rise, t-fall);
//Specify three delays, rise, fall, and turn-off
//Rise used for transitions 0->1, z->1
//Fall used for transitions 1->0, z->0
//Turn-off used for transitions 0->z, 1->z
specparam t-rise = 9, t-fall = 13, t-turnoff = 11;
(clk => q) = (t-rise, t-fall, t-turnoff);
//specify six delays.
//Delays are specified in order
//for transitions 0->l, 1->0, 0->z, z->l, 1->z, z->0. Order
//must be followed strictly.
specparam t-01 = 9, t-10 = 13, t-0z = 11;
specparam t-z1 = 9, t-1z = 11, t-z0 = 13;
(clk => q) = (t - 01, t-10, t-0z, t-zl, t-lz, t-z0);
//specify twelve delays.
//Delays are specified in order
//for transitions 0->l, 1->0, 0->z, z->l, 1-zz, z->0
/ / 0->X, X->1, 1->X, X->0, X->z, z->X.
//Order must be followed strictly.
specparam t-01 = 9, t-10 = 13, t-0z = 11;
specparam t-zl = 9, t-lz = 11, t-zO = 13;
specparam t-Ox = 4, t-xl = 13, t-lx = 5;
specparam t-xO = 9, t-xz = 11, t-zx = 7;
(clk => q) = (t-01, t-10, t-Oz, t-zl, t-lz, t-zO,
t-Ox, t-xl, t-lx, t-xo, t-xz, t-zx );
 Min, max, and typical delays
Min, max, andtypical values can also be
specified for pin-to-pin delays
//Specify three delays, rise, fall, and turn-off
//Each delay has a min:typ:max value
specparam t-rise = 8:9:10, t-fall = 12:13:14, t-
turnoff = 10:11:12;
(clk => q) = (t-rise, t-fall, t-turnoff) ;
 Handling X transitions
Verilog uses the pessimistic method to compute delays
for transitions to the X state.
The pessimistic approach dictates that if X transition
delays are not explicitly specified.
Transitions fromX to a known state should take
maximum possible time
Transition from a known state to X should take the
minimum possible time.
//Six delays specified
//for transitions 0->1, 1->0, 0->z, z->1, 1->z, z->0.
specparam t-01 = 9, t-10 = 13, t-0z = 11;
specparam t-z1 = 9, t-1z = 11, t-z0 = 13;
(clk => q) = (t-01, t-10, t-0z, t-z1, t-1z, t-z0);
 Timing Checks
• Timing verification is particularly important for
timing critical, highspeed sequential circuits
like microprocessors.
• System tasks are provided to do timing checks
in Verilog.
• Three most common timing checks tasks are
 $setup
 $hold
 and $width
• All timing checks must be inside thespecify
blocks only.
 $setup and $hold checks
$ setup and $hold tasks
are used to check the
setup andhold
constraints for a
sequential element in the
design.
• In a sequential
element like an edge-
triggered flip-flop, the
setup time is the
minimum time the
data must arrive
before the active
clock edge.
• Thehold time is the
minimum time the
data cannot change
after the active clock
edge.
 $setup task
Setup checks can be specified with the system
task$setup.
Usage:$setup(data-event, reference-event, limit);
data-event: Signal that is monitored for violations.
reference-event: Signal that establishes a
reference for monitoring the
data-event signal.
Limit: Minimum time required for setup of data
event.
Violation is reported if (T -T ) <limit
reference-event data-event
 Example
//Setup check is set.
//clock is the reference
//data is being checked for violations
//Violation reported if Tposedge-clk - Tdata< 3
specify
$setup(data, posedge clock, 3);
endspecify
 $hold task
Hold checks can be specified with the system
task $hold.
Usage: $hold (reference-event, data-event,
limit);
reference-event: Signal that establishes a
reference for monitoring the
data-event signal:data-event Signal that is
monitored for violation
limit: Minimum time required for hold of data
event
Violation is reported if (Tdata-event –Treference-event )< limit
specify
$hold(posedge clear, data, 5);
endspecify
$width Check
The system task $width
is used to check that
the width of a pulse
meets the minimum
width requirement.
Usage:
$width(reference-event,
limit).
reference-event: Edge-
triggered event (edge
transition of a signal).
Limit: Minimum width
of the pulse.
Thedata-event is not specified explicitly for
$width but is derived as the next opposite
reference-event signal.
edge of the
Thus, the $width task checks the time
between the transition of a signal value to
next opposite transition in the signal value.
Example
specify
$width (posedge clock, 6 ) ;
endspecify
 Delay Back-
Annotation
The various steps in the flow
that use delay back-annotation
are as follows.
1. The designer writes the RTL
description and then performs
functional simulation.
2. The RTL description is
converted to a gate-level netlist
by a logic synthesis tool.
3. The designer obtains pre-
layout estimates of delays in the
chip by using a delay calculator
and information about the IC
fabrication process.
4. Then, the designer does timing
simulation or static timing
verification of the gate-level
netlist, using these preliminary
values to check that the gate-
level netlist meets timing
constraints.
5. The post-layout delay values
areback-annotated to modify the
delay estimates for the gate-