lnit-y

vlocked feauontial ceuit

Llocked deqential incuit design inelvs weating wneits that

wtoe and'proceus infonmatior ovn time, using cock tignal
o ynenniye ttate "tronitions. hese cincuita eonaiat f memy
lement ike jlipp and combinatienal daie nabling them to
gnbate Dutputs boseol on cwvent and pactinput thein
ntvnal states.

2
Pstlem 0onition
nctiernalt
: deine
dltanl yine
Me ueguenoloinouit
re deined Behaviow and

tote DLapram :- RepHesent the cinit behaviown a stote

'u

oH toble. his viualiys the teansition betwen states and

the outpwts alsoated w ith each tate.

3tate ticigmment Aaaigh binany codes

eodes to theltates in the state table.
4Exoitaion equatione: etuminé the input tquatisns need eo
lip-lop
tranition dto the nt tate te cuent
:Bg the
to
baseol tate and np
5 Combinational togie ccebiational
inatiomal dogi to dnnpltm ent
dhe evcitatiey Uatiov
6- cit bnplemtation and tutput function.
Buütd the
and the clock

fon the state

diagam duign the cinuit waing T glip top

(Oc

machine e
ine ie jinite utate machine called mealy machine.
Step2: tate Table

Peent tote (Ps) p Net dtate (ND)| p lip flepe

TA T8 Tc
1
-

1
|00-
0

~00

00-00
X X
o---0x

X X

--0- X
00~---0000
-0 X-x0-X-
X X
X0KXo-kk
0-9-0x>X0-Ko0
Aep 3 ate
quatins Ff Sfp quatien
Fot TA, for Ta for Te

00 1 11 [0 O0 [[10
0 6 I
00
XX
10 0

TA = AA+ &e
 bad00ll1
0 0|| 00
|0

incuut Bag an

TA
 euige a lockedl AeUUntial cineit tat oatu accDNdli
to the state
digami
Q

0 10

olo

hal tep1 state Table

T flip Flop]

Bustnt tatel p| Net tate p lp Flop p

TA
QB+

|0

O0

0o

hp dtate Eualov f Flp-Plep p euolio

Fo TA, for TB.\6o0
A
 cincit

z(p)

TA

CK

# Analyus of clocAed syuential Cincut

2utpuut k ctate a clockead ueaieatial cHcuit i unc Arpedl

inpds
and pueYios state.

4tt consists

tod dable j- Aso ealleo a teukien table conuit

section
i tpt inpLuts, phesnt state, nett state'and
2tae
att DlagHan
outpud
:. GHaphical epkuutation state toble
tate ejuation-
dpecihu nut dUuu of pHet
toate un dUnA pHesent ctate
Ato
and inputs. butput eyuation ia alo odesenibtd in
tu pHe Udt dtate ard ainputs
Q Uye toe tubte ono ote
DA A

-A

CLK
sor" frem the ecùt
stoe Teo ip re b{A6) ,kowrj hput'>'ond

Atate Eqwatisns FF Snpud Euahen

Stote euahen b Fp Fl»p 4

n+ =D
B D,=
DA A+ = Ax t
+ B

DB - QB t A
(At B)
Ktate Table -
Bestt Ltote ( |
PS) P |Ner Stae (NS)P |FF ps
DA DB

000|
F0

0
0-

tate Dioquonh
)0

Vo
 # State Reduction

dtd the
deligening
For rampler
pHoctu

oe
the dguential
have afollewing
a
the

pincuit
state

ineuit. . byone

state diaguami
proct oling

Yo

state ssignm ent

aulgning bia valuu
the fokocd
ate AuAiguun ut g
machune h .
binay Value heuld
toa the itates of aueutnlial
Hap input ip
the tates n ych oay that the a

be given
to
minimm nunbu
be implenented with a
yuietions may
togie gate.
pu Aote Algunet
nunbes diates om
to atates one-to- ene
nulmbev do
Binany ugmnt giu binay
basu.
st utiliyu Çray codles do bg Qbout minimum
+
hge
Guay Cade hesigumunt
dharnitio
e
he ita
tald
pecifiu a state hy
each value that
bne-Hot huighment s
tonvey
hit ,n wuch thhe e ul
men fhe
a presie postisn the
Finitestate Machène (FSM),
fo eanple fos
or fon a fotatate
possibtl asuignnent art givon in the
thnee

Jottmuing table:
 Atate

So
Binany
00
| Gaay-Code One-Het
00
0010

00
|0D0
No- Ffe 2 2

foom the given

given state diagnam
Atate beductient aind d Heduce unbe ff b
edlucung the nunben dtalc, ahle kec unpk Putput
Kelatiohship wnchangd
step 1i Make the Heduceo state table

PHesent state Net &tote Outpul

=|
b

a
3cde10
40

tup 2 - find equivaleut atote n educed ctate table and

Tioo
tate 0T
totes ha Me
et
dt
Ja
atod e
dlput ,ao
inputa
to Same

dtotee ate eguralrt.Herce eaee-th

nOve tote Ool pla ce dhe ntea nert utote thaving

PHunt Stote Net stote

Output
X=0

db

cd

td
 Step
ep 3r Repeat
state '
Jhe Gtep 2
d'ond
Hnove
p! aH#
ad
y
ou
a
eguival trd

e9uival ent.
stae
Row
equivalent. Row comespoualug
ctade
u foul an
jau

ODTPUT
PRESENT STATe |NEXT STATE
X=0

|Step Yr Since, no Luvalet tote u dound. Thenyore, the

u
final
state

Hencei

Btatt
eaueion

Jnal
tafe
omplete
Aas fve states .
4 finitet state Nackines (ESM)

A Foide dtate Machine (FsM) alio kne a dtade Machint 0.

t
u
jnde

in a
ed
atate automaton (FsA),u a mathumatical
to
do

a
deign equtntial ogic incuits

inite
toay'
nnb
d pM1 Ut he bchoviouot
of states and
.
~tl
moal

dhal
of computation

tvani tisns betwen these stots bas ed

ea ult
Bn inputs nd ite cMNent atate

} Mooue Nachinei

A Mooxe Hachine u a iype hexe dhe output

FSM the
hat dhe
macine depends dotey Gn ul cuMGt dtate.Thu nedh
Ldput langes Bhen the machine tansitions to a new state,
that tate.
Dnd the outut ehains atable aut the olwatie of

tadte

Block

Comhinoti onal
decode
Output
2Mealy Nachint ;
Nealy oclhine ul a type FM kert dke oulpud iu

detwnwed by koth evvunt atate and the twvent dp inpud

the
Thie mta that the otput ean change dnttantantBuly whtn
ht uinpaut thange, ever the machne Urand iun dhe dane tate.
state aiagxam

'

Yo

Block Dinguam'
Pseseent stale

net state
Combutatienel
Šnput
togie

Dutpet
-
HAZARDS

Hazardsareunwanted switching transients that may appearat the output of a circuit because ditferent paths

exhibit diferent propagation delays. Hazards occur in comblnatlonal circults, where they may causea temporaryfalse

output value. When they occur in asynchronoussequential circults hazards may result in a transition to a wrong stable

state.

In designing asynchronoussequentlal circuits, care must be taken to conform to certain restrictions and

precautions to ensure that the circuits operate propertly.Thecircuit must be operated in fundamentalmode with onhy

one input changing at any time and must be free of critical races. inaddition, there is one more phenomenon caled a

hazard that may cause the circut to malfunction.

Hazards In Combinational Circuits

A hazard is a condition in which a change in a single variable producesa momentary change in outputwhen

no change in outputshould occur.

10 11

140

NAND-OR diêun )NANDelt

Fig Circuits with Hazards

Assume that all three inputs are initially equal to 1. This causesthe outputof gate 1 to be 1,thatof gate2 to be 0

and that of the circuit to be 1. Now consider a change in x 2from 1 to 0. Then the outputof gate 1 changes to0 and

that of gate 2changesto 1, leaving theoutput at 1. However,the outputmay momentarilygo to 0 if the propagation

delay through the iverteris taken into consideratlon. The delay In the Inverter may cause the output of gate 1 to

changeto0 before the output of gale 2 changesto 1.

The twoclrcults shown in Fig Implement the Boolean functlon in
sum-of-products
form:

This typeof limplementation may cause the output to gO to O when It should remaln a 1. If however, the clrcult is

implemented instead in product-of-sumsform namely, then the output may momentarily go to 1 when it should
remain0.The first case is referred to asstatle 1-hazard and the second case as statle 0-hazard.

A third type of hazard, known as dynamlc hazard, causes the outout to change three or more times when it

should change from 1 to0 or from 0to 1.

Fig Types of hazards

The change in x2 from 1 to O moves the circult from minterm 111 to minterm 101.The hazard exists because the

change in input results in a diferent product term covering the two minterm.

Fig llustrates hazard and its removal

Minterm 111 Is covered by the product term implemented in gate 1 and minterm 101 is covered by the product

termimplemented in gate2.The remedy for eliminatinga hazard is to enclose the two minterms with anotherproduct

term that overlaps both groupings. The hazard-free clrcuit obtained by such a conflguration is shown in figure below.
The extra gate in the circuit generates the product term
xx%, In general, hazards in combinational circults can be

removed by cove ring anytwo minterms that may produce a

hazard with a product term comnon toboth.The removal
of hazards requires the
addition of redundant gatesto the circult.

Flg. Hazard free circuit

Essential Hazards

asynchronous sequential circuits called an essential hazard. This

Another type of hazard that may occur in is

caused by unequal delays along two or more paths that originate trom the
same input. An excessive
type of hazard is

delay through an invertercircult in comparison to the delay assoclated with the feedback path may cause such a

hazard.

Esential hazards cannot be corrected by ading redundantgatesas in statichazards. The problem that they

impose can be corected by adjusting the amount ofdelay in the affected path.To avoid esential hazards, each

feedback loop must be handled with individual care to ensure that the delay in the feedback path is longenough

compare d with delays of other signalsthat originatefrom theinput terminals.