Calibration Free Power Reduction Technique for

11Bit, 45MS/s Pipelined ADC Implementation

Amitesh Kumar Tripathi Kiran Kumar Garje

Scientist-C, ANURAG, DRDO Scientist-E, ANURAG, DRDO
Kanchanbagh, Hyderabad-58, India. Kanchanbagh, Hyderabad-58, India.
amiteshkumar@anurag.drdo.in kirankumar@anurag.drdo.in

Abstract—This paper proposes an efficient power saving Section VI concludes the paper.
scheme in pipelined analog to digital converter (ADC) by scaling
residue output four times, called as 4X residue output scaling II. E RRORS A SSOCIATED W ITH M ULTIPLYING DAC S
technique. The proposed technique provides excellent solution
for error due to insufficient DC gain, inaccurate settling, lim- General block diagram of M-stage pipelined ADC [3] is
ited swing and OTA non linearity. In the 4X residue output shown in Fig-1. Each pipelined stage is converting n-bit per
scaling, the residue amplifier will bring the interstage output stage and consist of front sample & hold, n-bit ADC, n-
to ±250mV (4X scaled) instead of full scale ±1V . The 4X bit DAC, subtractor and residue amplifier. Front sample &
residue output scaling is implemented in 11 bit, 45MS/s dual
hold, n-bit DAC, subtractor and residue amplifier is commonly
channel pipelined analog-to-digital converter. The proposed ADC
is realized by four 2.5 bit pipelined stages, followed by 3-bit flash implemented by a switched capacitor circuit called Multiplying
ADC. The proposed dual channel ADC consumes 60mW of power DAC (MDAC). Opamp based switched capacitor circuits are
and occupies the 3.5mm 2 area in UMC65nm CMOS technology. most commonly used for implementation of MDAC. Closed-
Post layout simulation with RC-CC (Coupled RC Extraction) loop gain of opamp based MDACs are primarily the function
achieves the SFDR of 72dB and SINAD of 62 dB at input of of capacitor ratio.
5.5MHz with sampling frequency of 45 MHz.
keywords: Residue output scaling, Calibration Free
Pipelined ADC, Telescopic OTA, Pipelined ADC, Satellite
Hand-held Terminal.

I. I NTRODUCTION
Satellite is the most promising and useful communication
media for broadcasting application [1]. Due to large coverage
area, it is widely used for digital TV broadcasting, remote
sensing application and satellite hand-held application. Wide
dynamic range and good bit-error-rate (BER) is the most
desirable feature of satellite hand-held receiver [2]. BER of
10−5 is essential for audio & video application. To achieve Fig. 1. General block diagram of M-stage pipelined ADC with n-bit
such a BER, implementation of forward error correction logic conversion per step [3]
is absolutely essential. To implement forward error correction
logic digitally, it is neccessory to convert received analog Block Diagram of a opamp based 2.5 bit switched capacitor
baseband signal into digital format. analog-to-digital-converter MDAC circuit is shown in Fig-2. The output of the 2.5-bit
(ADC) is used for that purpose. MDAC can be expressed as
This paper presents a 11Bit, 45MS/s dual channel pipelined
ADC suitable for satellite handheld receiver terminal. The Vout = 4.Vin + β.Vdac (1)
individual channel of ADC is implemented by 2.5bit-2.5bit- where β.Vdac = ±3Vref , ±2Vref , ±1Vref , 0 are decided by
2.5bit-2.5bit-3bit per stage in UMC65nm CMOS technology. the digital output from the sub-ADC. Switched capacitor
Dual ADC consumes 60mW of power with 3.3V supply and implementation of multiplying DACs mainly has the following
achieved figure-of-merit (FOM) is 0.325pJ per conversion. errors:
The ADC low power dissipation is achieved by implementing
MDAC with 4X residue scaling. 1) Gain error is deviation of MDAC closed loop gain by
Rest of the paper is organized as follows: Section II provides 4 and it is caused by capacitor mismatch and finite
the basic details of error associated with Multiplying DACs. DC gain of opamp.
Section III provides the details of proposed 4X residue scaling 2) Non-linearity error is caused by capacitor mismatch
technique. Section IV presents the ADC implementation de- and op-amp non-linearity.
tails. Section V summarizes the post-layout simulation result.
978-1-5090-3646-2/16/$31.002016
c IEEE
 sense that it does not require extra circuitry and is very useful
for lower node process technology.

Fig. 3. Conceptual waveform of (a) full swing interstage pipelined ADC (b)
Fig. 2. Opamp based switched capacitor implementation of 2.5-bit MDAC 4X residue output scaled pipelined ADC

3) Thermal noise is due to ON resistance of the switches

and op-amp thermal noise. TABLE I. C OMPARISON OF F IRST S TAGE OTA R EQUIREMENT W ITH
4) Settling error is due to op-amps finite unity gain & W ITHOUT 4X R ESIDUE S CALING
bandwidth (UGBW) and closed loop feedback factor.
Parameter Formula Without With
All the above errors are mostly associated with OTA and Output Scaling Output Scaling
switched-capacitor network. Errors due to capacitor mismatch Sampling Capacitor Cs 3.2pF 3.2pF
can be minimized by using MIM (Metal-Insulator-Metal) Feedback Capacitor Cf 800f F 3.2pF
capacitor, common centriod layout technique and shielding.
Residue Gain A 4 1
Finite DC gain, finite unity gain bandwidth (UGBW) and
Cf
limited swing of the OTA are the major source of errors in Feedback Factor β= 1/5 1/2
Cs + Cf
the switched capacitor MDAC implementation. High DC gain,
1 N
high unity gain bandwidth and large output swing requirement OTA DC Gain Adc > 2 ≈ 80dB ≈ 72dB
β
of op-amp becomes the major bottleneck of the pipelined ADC
design, specially in lower node process. (N )log2
OTA UGBW fugb > fs ≈ 948M Hz ≈ 380M Hz
βπ
Output Swing Vswing ±1V ±250mV
III. 4X R ESIDUE O UTPUT S CALING T ECHNIQUE
Major source of errors in SC-MDAC implementation are
finite DC gain & unity gain bandwidth, limited swing of OTA. Comparison of first stage OTA requirement with & without
High DC gain, high unity gain bandwidth requirement and scaling is shown in Table-I. Due to 4X residue output scaling,
large output swing is the crucial design parameter for wide switched capacitor feedback factor become 1/2 instead of 1/5,
input range ADC with the lower node CMOS process. Various which causes 10% reduction in open loop gain requirement of
calibration algorithms are proposed in [4] [5] [6] [7] [8] to OTA, 60% reduction in the unity gain frequency requirement of
tackle to errors associated with opamp DC gain but this require OTA and 75% reduction in the swing of OTA. This residue scal-
extra circuitry and generally interrupt the analog to digital ing technique greatly reduces the design complexity of OTA in
conversion process. We have proposed a 4X residue scaling multi-bit per stage pipelined implementation. By using residue
technique to overcome these errors associated with OTA. The scaling, feedback factor of multi-bit per stage MDAC circuit
conceptual waveform of 4X residue scaling technique is shown can be bring to its ideal value. For lower node process, it is
in Fig-3. In the 4X residue scaling technique, the residue very advantageous because it reduces the OTA specification
amplifier will bring the interstage output to ±250mV (4X and swing requirement which results good amount of power
scaled) instead of full scale ±1V . This can be achieved by saving for ADC.
decreasing the gain of residue amplifier by 4X. Hence first The proposed 4X output scaling technique can be generalized
2.5bit pipelined stage is having the gain of 1 (Ideally closed to N X scaling, where N is the residue gain of first pipelined
loop gain should be 4). stage i.e. 2X scaling for 1.5-bit first stage, 4X scaling for 2.5-
Due to 4X output scaling, the design of comparator will bit stage, 8X scaling for 3.5-bit stage, 16X scaling for 4.5-bit
become more stringent, but due to digital error correction stage, · · ·. Since we have implemented the dual channel ADC
circuit and pre-amplifier based architecture, comparator can with 2.5-bit stages, we have implemented 2.5-bit first pipelined
be designed liberally. This design technique is unique in the stage with 4X residue scaling.
 IV. ADC C IRCUIT D ETAILS A common mode feedback (CMFB) circuit is required for
a fully differential telescopic OTA to set up common mode
A. Dynamic Comparator output voltage. A switched capacitor CMFB is not only a
Dynamic comparator is always a very good choice for high popular choice but also it allows a larger output swing.
speed implementation [9]. Main bottleneck of dynamic latch is Simulated result shows that telescopic OTA achieved the DC-
its huge offset. Pre-amplifier is placed before the dynamic latch gain of 82dB and fU GBW = 680M Hz with 1mA of bias
for reducing the offset error. Pre-amplifier should have the DC current. The main drawback of the telescopic OTA is its small
gain of 3 to 10 [10]. Comparator offset upto V ref /2n+1 [11] output voltage swing. The available swing in proposed OTA
(n is the number of bit resolved per stage) can be corrected is given by 2(V DD − 7 ∗ VDS sat ), where VDS sat is the
by digital error correction circuit. saturation voltage of transistor. But due to 4X scaling, the
swing requirement of telescopic OTA is greatly reduced.

Fig. 4. Schematic of dynamic latch used for the implementation of comparator

[10]

Fig-4 shows the schematic diagram of fully differential

dynamic latch used in comparator. Its basic functionality is
as follows:
• If LATCH EN=LOW, then M5 and M6 will be OFF. Fig. 5. Double Cascode Telescopic Operational Trans-conductance Amplifier
This will make latch inactive. LATCH EN=LOW will (OTA)
pulldown OUTP to logic LOW and OUTM to logic
HIGH. This is sample phase.
C. Implementation of sampling switches
• If LATCH EN=HIGH, Then M5 and M6 will be
ON. This will make latch active for the operation. In switched-capacitor implementation of pipelined ADC,
Since M7 is ON so VDD is now connected to the switches are implemented with MOS transistors. These MOS
source of M7. Now if INP>INM, then Due to positive switches cause non-idealities and errors like clock feed
feedback, INP will be pulled to VDD and INM will through, charge injection and signal dependent ON resistance.
be pulled to VSS. So OUTP=VDD and OUTM=VSS. Error due to clock-feed through and charge-injection can
If INP<INM, Then due to positive feedback, INP will be removed by bottom plate sampling and dummy switches
be pulled down to VSS and INM will be pulled up to [10][11][13]. The ON resistance of a MOS switch is given by
VDD. This is decision phase. 1
RON = (4)
Simulated result shows that the comparator offset voltage is μn Cox W
L (V DD − VIN − VT H )
less than 225μV which is very much within the specification
Equation-4 clearly shows that the turn-on resistance of a
limit.
MOS switch is input signal-dependent and creates non-linear
distortion. Bootstrapping technique [12][14] is very popular
B. Telescopic Operational Trans-conductance Amplifier (OTA) for removing non-linearity due to input dependent RON . The
basic idea of bootstrapping is that the linearity of a MOS
Fig-5 shows the topology used for the OTA in sample &
switches can be improved significantly if VGS is kept constant
hold and MDAC of pipelined stages[12]. A double cascode
irrespective of input changes. The bootstrapped switch in
telescopic OTA is choosen because it provides very high gain,
shown in Fig-6.
high unity-gain-bandwidth and fast settling. Gain and UGBW
Here NMOS M9 is working as a switch. Its basic operation is
of telescopic OTA is given by
as follows:
AV = (gm1 [gm5 .ro5 .ro7 .ro1 ||gm15 .ro9 .ro15 .ro11 ]) (2) • When switch is turned off. A NMOS switch is con-
gm1 nected to ground while capacitor C3 is charged to a
fU GBW = (3) supply voltage.
CL
 • In the next clock phase, capacitor C3 , now charged to connected to output node. Since there is no charge transferring
Vdd, is connected between the gate and the source of scheme, capacitor matching is not an issue here in this scheme.
the switch and acts like a constant DC voltage. The achieved dynamic performances of sample & hold are:
SFDR=95.04dB, SINAD=82.73dB.
Simulated output of clock boosting circuit is shown in Fig-7.
Simulation results shows that boosted clock is following the E. Top Level ADC Details
input signal and maintaining a constant VGS which removes
the non-linearity due to input dependent on resistance of the Fig-9 shows the architectural block diagram of 2.5bit-
switch and provides the 93dB of linearity. 2.5bit-2.5bit-2.5bit-3bit per stage pipelined ADC. All the cur-
rent and voltage references are generated by bandgap circuit.
Each individual pipelined stage is implemented by sample &
hold, low resolution ADC (Sub-ADC), low resolution DAC
(sub-DAC) and a residue amplifier. Fully differential double
cascode telescopic OTA is used for the implementation of
sample & hold and MDAC. Finally the digital outputs are error
corrected, multiplexed and digitally buffered for 10pF load.

Fig. 6. Transistor level schematic of clock boosting circuit [12]

Fig. 9. Block Diagram of 11Bit, 45Msps Dual Channel Pipelined ADC

Fig. 7. Transient simulation result of clock boosting circuit

V. S IMULATED R ESULTS
D. Flip Around Sample and Hold Amplifier FFT plot of full chip post layout simulation with RC
CC parasitics extraction is shown in Fig-10 and achieved
To ensure that first stage sub-ADC and MDAC see the same results are tabulated in Table-II. Figure-of-Merit of our ADC is
input, Front-end sample and hold is commonly used. Flip- calculated by equation-5. Our FOM calculation include power
around topology is used commonly due to advantage that the dissipation due to on-chip voltage reference generation circuit
feedback factor is unity [11]. Hence OTA design, used in SHA, also.
is power efficient. Flip-around topology is also insensitive P
F OM = (5)
to capacitor mismatch as it is a single capacitor sampling. (2)(fs )(2EN OB )
Fully differential schematic diagram of Flip-around sample
and hold topology is shown in Fig-8. During sample phase where P is power dissipation, fs is sampling frequency, ENOB
is effective number of bits. Equation has extra factor of 2 at
denominator due to dual channel ADC operation.
Table-III compares the performance of this ADC with the
number of recently published ADC work. The comparison
shows that achieved figure-of-merit is very much comparable
with the state of art published work.

VI. C ONCLUSION
The design of a dual channel 11bit, 45Msps Pipelined
ADC for satellite handheld receiver is presented here. Switched
capacitor circuit is used for the implementation of ADC.
Fig. 8. Block diagram of flip around sample and hold amplifier (SHA) Double cascode telescopic OTA is used due to high gain
and UGB requirement. We have proposed 4X residue output
(S), input is charged to sampling capacitor(Cs ) and during scaling technique to reduce the design constraints of telescopic
hold phase (H), capacitor is flipped to feedback and directly OTA. With the 4X residue output scaling, switched capacitor
 less and very much comparable with state of art published
work.

ACKNOWLEDGMENT
The authors would like to thank Shri CVS Sastry, Outstand-
ing Scientist & Director, ANURAG for his encouragement,
support and inspiration.

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