Micro blaze the boot loader creating it
When we last looked at the MicroZed we focused upon how the Zynq configured both the
processing system, the programmable logic and how this differed from traditional FPGA’s.
Having understood the academics behind the configuration it is time to look at how we create a FSBL
and use it together with our software application and programmable logic design to create a
configurable system which will boot following power on or reset.
Thanks to Xilinx generation of a FSBL which will load you application and configure your FPGA is
remarkably simple as an example FSBL is provided. Within the current SDK workspace (the one
which contains your project) create a new project using the new -> application project as shown in
figure one
Figure One, Creating the First Stage Boot Loader Project
Select if you want to use C or C++, the board support package defined for your system (used_bsp)
and the name of the project in this case I used the name uzed_fsbl.
On the next tab select the Zynq FSBL option from the available templates as shown in figure two and
your FSBL project will be created, we are then nearly ready to create the boot image. If you have
compile automatically selected the FSBL will be complied, if not it will be complied on demand later
on.
Figure Two, Creating the FSBL from the template provided.
However we need to make a change to the linker script provided with the FSBL as it has no idea
where the DDR memory is located in the processor address space. Therefore we need to open the
lscrip.ld and add the DDR memory location into the file. The location of the DDR within the address
space can be found in the linker script you have created for your application this information can be
found in the system.xml file under the hw platform definition.
Figure three, Defining the DDR address space.
Figure three shows the FSBL lscript.ld with the DDR address for the system added in, if you forget to
do this you will find that the boot loader will run, the FPGA will configure however, the application
will not run if you have configured your application to execute in DDR.
Generating Configuration Image
Looking under the project explorer, you should hopefully now have the following modules. Each
should have a slightly different symbol identifying the type of module using figure four as an
example you will see the following structure.
1. uzed_hw – named after the processing subsystem you created, this is the hardware
definition of your file
2. uzed_bsp – This is the board support package you created.
3. uzed_app. – The application itself.
4. Used_fsbl – The first stage boot loader we have just created and modified the linker script
for.
Within this application as we are creating a bare metal application (no operating system) you will
need the following files to create a boot image in this specific order.
1. First Stage Boot Loader
2. FPGA programming bit file (created in Vivado when we ran the implementation)
3. C Application
Creating a boot image is very simple within SDK using the “Create Zynq Boot Image” option under
the Xilinx Tools Menu as shown in figure four.
Figure Four, the option for creating the Zynq Boot Image
Once you have selected this a new dialog box will open allowing you to select the require files the
files needed are defined above and can be seen in figure five.
Figure five, the complete files needed for the boot image
It is important to stress that the FPGA bit file must ALWAYS follow the FSBL. Clicking on create image
will create both a *.bin and a *.mcs file which can be programmed into the target device.
With the MicroZed we have the option storing this generated file in either the QSPI which requires a
JTAG programming cable or within the micro SD card.
The simpler of the two is to use the MicroSD card all you need to do for this, is insert the SD card
into the computer you used to generate the boot file on and transfer the .bin file to the SD card.
However for this to work correctly you then need to rename the file name to be boot.bin, inserting
this into the MicroZed and performing a reset once the mode pins (using the jumpers) have been set
to configure from the SD card should result in your application being up and running as you desire.
If you wish to configure the QSPI, the following methods should be used, either SDK using the
program flash option under the Xilinx tools options or Xilinx impact can also be used for
programming configuration memories.
As we are using the QSPI interface, this is defined in the re-customise IP options within Vivado as
shown in figure six. Hence the hardware definition will contain the QSPI IP core and the location in
the address map allowing the first stage boot loader to be able to interface to this device and
configure the device.
Figure six, the Vivado view showing the Quad SPI memory under the flash
memory interfaces.
The next stage in programming the device is to connect the Zynq hardware system to your PC using
the JTAG programming cable. Programming the configuration memory is then as simple as selecting
the “Program Flash” option from the Xilinx tools menu within SDK as shown in figure seven
Figure seven, Programming the configuration memory
Navigate and select the MCS file you generated and enter an offset of 0x0 in the dialog box which
appears and ensuring your target hardware is powered on click on program (Figure Seven)
Figure Seven, programming flash dialog.
This may take a few minutes for the device to be programmed and verify if you ticked the verify
option. Once it is complete power down your hardware and re apply the power (alternately reset
the processor), provided you have the mode pins configured correctly your Zynq system will spring
to life having configured and start to run the application software and FPGA design.
