1

CHAPTER 2
ARCHITECTURE DETAILS AND
INSTRUCTION SET OF 8085 AND 8086
MICROPROCESSOR

Ramchandra Pokhrel

2082-01-11
 8085 Microprocessor
2

◻ A microprocessor is a multipurpose, programmable,

clock-driven, register base electronic device, that
reads binary instruction from storage device called
memory accept binary data as input and process data
according to those instruction and provide result as
output.
 8085 Microprocessor
3

◻ Introduced in 1977
◻ 8-bit general purpose µp
◻ Capable of addressing 64 k of memory
◻ Has 40 pins
◻ Requires +5 v power supply
◻ Can operate with 3 MHz clock
◻ 8085 upward compatible
8085
Microprocessor
4

8085 Pin
Configuration
5

8085 Microprocessor Pins and Signals

 8085 Microprocessor :Pin description
◻ Higher Order Address pins- A15 – A8
◻ Lower Order Address/ Data Pins- AD7-AD0
These are time multiplexed pins and are de-multiplexed using the pin ALE
◻ Control Pins – RD, WR
These are active low Read & Write pins
◻ Status Pins – ALE, IO/M (active low), S1, S0
ALE (Address Latch Enable)-Used to de-multiplex AD7-AD0
IO/M – Used to select I/O or Memory operation
S1,S0 – Denote the status of data on data bus
◻ Interrupt Pins – TRAP, RST7.5, RST 6.5, RST 5.5, INTR, INTA
These are hardware interrupts used to initiate an interrupt service routine
stored at predefined locations of the system memory.
◻ Serial I/O pins – SID (Serial Input Data), SOD (Serial Output Data)
These pins are used to interface 8085 with a serial device.
8085 Microprocessor :Pin Description Cont..

◻ Clock Pins- X1, X2, CLK(OUT)

X1, X2- These are clock input pins. A crystal is connected
between these pins such that fcrystal= 2f8085 where fcrystal= crystal
frequency & f8085 = operating frequency of 8085
CLK(OUT) – This is an auxiliary clock output source
◻ Reset Pins – Reset In (active low), Reset Out
Reset In is used to reset 8085 whereas Reset Out can be used
to reset other devices in the system
◻ DMA (Direct Memory Access) pins – HOLD, HLDA
These pins are used when data transfer is to be performed
directly between an external device and the main memory of
the system.
◻ Power Supply Pins - +VCC, VSS
8

8085 Internal Architecture

 8085 Microprocessor
9

It consists of five essential blocks.

1. ARITHMETIC LOGIC SECTION
2. REGISTER SECTION
3. THE INTERRUPT CONTROL SECTION
4. SERIAL I/O SECTION
5. THE TIMING AND CONTROL UNIT
 8085 Microprocessor
10

◻ ARITHMETIC LOGIC SECTION: This section

consists of
Accumulator(A)
Temporarily Register (TR)
A flag register (FR)
An arithmetic logic unit (ALU)
 8085 Microprocessor
11

ALU
It performs various arithmetic and logic operations.
The data is available in accumulator and
temporary/general purpose registers.
Arithmetic Operations:
■ Addition, Subtraction, Increment, Decrement etc.
Logic Operations:
■ AND, OR, X-OR, Complement etc.
 8085 Microprocessor
12

Registers array
▪ Six general purpose 8-bit registers: B, C, D, E, H, L
▪ They can also be combined as register pairs to
perform 16-bit operations: BC, DE, HL
▪ Registers are programmable (data load, move, etc.)
Temporary Register
■ W and Z, 8-bit register and holds the data temporarily during
the program execution.
 8085 Microprocessor
13

◻ Accumulator
It the main register of microprocessor.
It is also called register ‘A’.
It is an 8-bit register.
It is used in the arithmetic and logic operations.
It always contains one of the operands on which
arithmetic/logic has to be performed.
After the arithmetic/logic operation, the contents of
accumulator are replaced by the result.
 8085 Microprocessor
14

◻ The Program Counter (PC)

This is a 16 bit register that is used to control the sequencing of the
execution of instructions.
This register always holds the address of the next instruction.
Since it holds an address, it must be 16 bits wide.
◻ The Stack pointer
The stack pointer is also a 16-bit register that is used to point into
memory.
The memory this register points to is a special area called the stack.
The stack is an area of memory used to hold data that will be
retreived soon.
The stack is usually accessed in a Last In First Out (LIFO) fashion.
 8085 Microprocessor
15

◻ Increment/Decrement Register
This register is used to increment or decrement the value of Stack
Pointer.
During PUSH operation, the value of Stack Pointer is incremented.
During POP operation, the value of Stack Pointer is decremented.
◻ Address Latch
It is group of 8 buffers.
The upper-byte of 16-bit address is stored in this latch.
And then it is made available to the peripheral devices.
 8085 Microprocessor
16

◻ Address/Data Latch
The lower-byte of address and 8-bit of data are multiplexed.
It holds either lower-byte of address or 8-bits of data.
This is decided by ALE (Address Latch Enable) signal.
■ If ALE = 1 then Address/Data Latch contains lower-byte of address.
■ If ALE = 0 then It contains 8-bit data.
 8085 Microprocessor
17

Flags register

◻ There is flags register whose bits are affected by the arithmetic &
logic operations.
■ S-sign flag
■ The sign flag is set if bit D7 of the accumulator is set
after an arithmetic or logic operation.
■ Z-zero flag
■ Set if the result of the ALU operation is 0. Otherwise is
reset. This flag is affected by operations on the
accumulator as well as other registers. (DCR B).
 8085 Microprocessor
18

■ AC-Auxiliary Carry
■ This flag is set when a carry is generated from bit D3
and passed to D4 . This flag is used only internally for
BCD operations.
■ P-Parity flag
■ After an ALU operation if the result has an even number
of 1’s the p-flag is set. Otherwise it is cleared. So, the
flag can be used to indicate even parity.
■ CY-carry flag
■ bit is SET if there is a carry from the MSB position
during an addition operation or if there is a borrow
during the subtraction operation, otherwise this flag is
RESET.
 8085 Microprocessor
19

◻ Program Status Word (PSW)

The contents of Accumulator and Status Flags clubbed
together is known as Program Status Word (PSW).
It is a 16-bit word.
 8085 Microprocessor
20

Interrupt Controller
It is used to handle the interrupts.
There are 5 interrupt signals in 8085:
■ TRAP
■ RST 7.5
■ RST 6.5
■ RST 5.5
■ INTR
Interrupt controller receives these interrupts according to
their priority and applies them to the microprocessor.
❑ There is one outgoing signal INTA which is called
Interrupt Acknowledge.
 8085 Microprocessor
21

◻ Instruction Register
It is used to hold the current instruction which the
microprocessor is about to execute.
It is an 8-bit register.
◻ Instruction Decoder
It interprets the instruction stored in instruction register.
It generates various machine cycles depending upon the
instruction.
The machine cycles are then given to the Timing and
Control Unit.
 8085 Microprocessor
22

Timing and Control Unit

◻ It controls all the operations of microprocessor and peripheral devices.
◻ Depending upon the machine cycles received from Instruction Decoder, it
generates 12 control signals:
■ S0 and S1 (Status Signals).

■ ALE (Address Latch Enable).

■ RD (Read, active low).

■ WR (Write, active low).

■ IO/M (Input-Output/Memory).

■ READY

■ RESET IN

■ RESET OUT

■ CLK OUT

■ HOLD and HLDA

 8085 Microprocessor
23

◻ Serial I/O Controller

It is used to convert serial data into parallel and parallel data into serial.
Microprocessor works with 8-bit parallel data.
Serial I/O devices works with serial transfer of data.
Therefore, this unit is the interface between microprocessor and serial
I/O devices.
Two pins SID (Serial Input Data), SOD (Serial Output Data)
These pins are used to interface 8085 with a serial device.

◻ Power Supply
This unit provides +5V power supply to the microprocessor.
The microprocessor needs +5V power supply for its operation.
 8085 Microprocessor
24

◻ The 8085 is an 8-bit general purpose microprocessor that can

address 64K Byte of memory.
◻ It has 40 pins and uses +5V for power. It can run at a maximum
frequency of 3 MHz.
The pins on the chip can be grouped into 6 groups:
■ Address Bus.
■ Data Bus.
■ Control and Status Signals.
■ Power supply and frequency.
■ Externally Initiated Signals.
■ Serial I/O ports.
 8085 Microprocessor
25

❑ 8085 Bus
The 8-bit 8085 CPU (or MPU – Micro Processing Unit)
communicates with the other units using a 16-bit address bus, an
8-bit data bus and a control bus.
 8085 Microprocessor
26

Address Bus , Data Bus and Control Bus

◻ The address bus has 8 signal lines A8 – A15 which are

unidirectional.
◻ The other 8 address bits are multiplexed (time shared) with the 8

data bits.
So, the bits AD0 – AD7 are bi-directional and serve as A0 –
A7 and D0 – D7 at the same time.
■ During the execution of the instruction, these lines carry the
address bits during the early part, then during the late parts of
the execution, they carry the 8 data bits.
In order to separate the address from the data, we can use a
latch to save the value before the function of the bits changes.
◻ There is no real control bus. Instead, the control bus is made up of a number of single
bit control signals.
 8085 Microprocessor
27

Control and Status Signal

◻ There are 4 main control and status signals. These are:

■ ALE: Address Latch Enable. This signal is a pulse that become

1 when the AD0 – AD7 lines have an address on them. It
becomes 0 after that. This signal can be used to enable a latch
to save the address bits from the AD lines.
■ RD: Read. Active low.
■ WR: Write. Active low.
■ IO/M: This signal specifies whether the operation is a memory
operation (IO/M=0) or an I/O operation (IO/M=1).
■ S1 and S0 : Status signals to specify the kind of operation
being performed .Usually un-used in small systems.
 8085 Microprocessor
28

Frequency Control Signals

◻ There are 3 important pins in the frequency control group.

X0 and X1 are the inputs from the crystal or clock generating

circuit.
■ The frequency is internally divided by 2.
■ So, to run the microprocessor at 3 MHz, a clock running
at 6 MHz should be connected to the X0 and X1 pins.
CLK (OUT): An output clock pin to drive the clock of the rest
of the system.
 Instruction Cycle, Machine Cylce and T-states
29

T- State: One subdivision of an operation. A T-state lasts for

one clock period.
■ An instruction’s execution length is usually measured in a
number of T-states. (clock cycles).
Machine Cycle: The time required to complete one operation
of accessing memory, I/O, or acknowledging an external
request.
■ This cycle may consist of 3 to 6 T-states.
Instruction Cycle: The time required to complete the execution
of an instruction.
■ In the 8085, an instruction cycle may consist of 1 to 6
machine cycles.
30

Thank You !!
 8085 Instructions
31

◻ Since the 8085 is an 8-bit device it can have up to 2^8 (256)

instructions.
◻ However, the 8085 only uses 246 combinations that represent a
total of 74 instructions.
◻ Most of the instructions have more than one format.
◻ These instructions can be grouped into five different groups:
■ Data Transfer
■ Arithmetic
■ Logic
■ Branch
■ Machine Control
 8085 Instructions
32

Instruction and Data Formats

◻ Each instruction has two parts. – The first part is the

task or operation to be performed.

• This part is called the “opcode” (operation code)
◻ The second part is the data to be operated on

• Called the “operand”.

 8085 Instructions
33

Data Transfer Instruction

– These instruction simply COPY the data from the
source to the destination.
– MOV, MVI, LDA, and STA
– They transfer:
• Data between registers.
• Data Byte to a register or memory location.
• Data between a memory location and a register.
• Data between an I\O Device and the accumulator.
–The data in the source is not changed.
1. Data Transfer (Copy) Operations
1. Load a 8-bit number in a Register
2. Copy from Register to Register
3. Copy between Register and Memory
4. Copy between Input/Output Port and Accumulator
5. Load a 16-bit number in a Register pair
6. Copy between Register pair and Stack memory
Example Data Transfer (Copy)
Operations/Instructions

1. Load a 8-bit number 4F in MVI B, 4FH

register B
2. Copy from Register B to MOV A,B
Register A
3. Load a 16-bit number 2050 LXI H, 2050H
in Register pair HL
4. Copy from Register B to MOV M,B
Memory Address 2050
5. Copy between OUT 01H
Input/Output Port and IN 07H
Accumulator
2. Arithmetic Operations
1. Addition of two 8-bit numbers
2. Subtraction of two 8-bit numbers
3. Increment/ Decrement a 8-bit number
Example Arithmetic Operations/Instructions

1. Add a 8-bit number 32H to ADI 32H

Accumulator
2. Add contents of Register B to ADD B
Accumulator
3. Subtract a 8-bit number 32H SUI 32H
from Accumulator
4. Subtract contents of Register C SUB C
from Accumulator
5. Increment the contents of INR D
Register D by 1
6. Decrement the contents of DCR E
Register E by 1
3. Logical & Bit Manipulation
Operations
1. AND two 8-bit numbers
2. OR two 8-bit numbers
3. Exclusive-OR two 8-bit numbers
4. Compare two 8-bit numbers
5. Complement
6. Rotate Left/Right Accumulator bits
Example Logical & Bit Manipulation
Operations/Instructions

1. Logically AND Register H with ANA H

Accumulator
2. Logically OR Register L with ORA L
Accumulator
3. Logically XOR Register B with XRA B
Accumulator
4. Compare contents of Register CMP C
C with Accumulator
5. Complement Accumulator
CMA
6. Rotate Accumulator Left
RAL
4. Branching Operations
These operations are used to control the flow of
program execution
1.Jumps
■ Conditional jumps
■ Unconditional jumps
2.Call & Return
■ Conditional Call & Return
■ Unconditional Call & Return
Example Branching Operations/Instructions

1. Jump to a 16-bit Address JC 2080H

2080H if Carry flag is SET
2. Unconditional Jump JMP 2050H
3. Call a subroutine with its 16-bit CALL 3050H
Address
4. Return back from the Call RET
5. Call a subroutine with its 16-bit
CNC 3050H
Address if Carry flag is RESET
6. Return if Zero flag is SET
RZ
5. Machine Control Instructions
These instructions affect the operation of the
processor. For e.g.
HLT Stop program execution
NOP Do not perform any operation
 4. Addressing Modes of 8085
◻ Format of a typical Assembly language instruction is
given below-
[Label:] Mnemonic [Operands] [;comments]
HLT
MVI A, 20H
MOV M, A ;Copy A to memory location whose
address is stored in register pair HL
LOAD: LDA 2050H ;Load A with contents of memory
location with address 2050H
READ: IN 07H ;Read data from Input port with
address 07H
Addressing Modes
◻ Most of instruction requires operand.
◻ The various way of assigning operands are called
addressing modes.
◻ Addressing modes of 8085
1. Register Addressing
2. Immediate Addressing
3. Memory Addressing
4. Input/Output Addressing
1. Register Addressing
◻ Operands are one of the internal registers of 8085
◻ Examples-
MOV A, B
ADD C
2. Immediate Addressing
◻ Value of the operand is given in the instruction
itself
◻ Example-
MVI A, 20H
LXI H, 2050H
ADI 30H
SUI 10H
3. Memory Addressing
◻ One of the operands is a memory location
◻ Depending on how address of memory location is
specified, memory addressing is of two types
Direct addressing
Indirect addressing
3(a) Direct Addressing
◻ 16-bit Address of the memory location is specified
in the instruction directly
◻ Examples-
LDA 2050H ;load A with contents of memory
location with address 2050H
STA 3050H ;store A with contents of memory
location with address 3050H
 3(b) Indirect Addressing
◻ A memory pointer register is used to store the
address of the memory location
◻ Example-
MOV M, A ;copy register A to memory location
whose address is stored in register pair
HL

H L
A 30H 20H 50H 2050H 30H
4. Input/Output Addressing
◻ 8-bit address of the port is directly specified in the
instruction
◻ Examples-
IN 07H
OUT 21H
Instruction & Data Formats
8085 Instruction set can be classified according to
size (in bytes) as
1. 1-byte Instructions
2. 2-byte Instructions
3. 3-byte Instructions
1. One-byte Instructions
◻ Includes Opcode and Operand in the same byte
◻ Examples-

Opcode Operand Binary Code Hex Code

MOV C, A 0100 1111 4FH
ADD B 1000 0000 80H
HLT 0111 0110 76H
2. Two-byte Instructions
◻ First byte specifies Operation Code
◻ Second byte specifies Operand
◻ Examples-
Opcode Operand Binary Code Hex Code
MVI A, 32H 0011 1110 3EH
0011 0010 32H
MVI B, F2H 0000 0110 06H
1111 0010 F2H
3. Three-byte Instructions
◻ First byte specifies Operation Code
◻ Second & Third byte specifies Operand
◻ Examples-
Opcode Operand Binary Code Hex Code
LXI H, 2050H 0010 0001 21H
0101 0000 50H
0010 0000 20H
LDA 3070H 0011 1010 3AH
0111 0000 70H
0011 0000 30H
 8086 Microprocessor

55
 8086 Microprocessor
56

Features of 8086 Microprocessor:

1. Intel 8086 was launched in 1978.
2. It was the first 16-bit microprocessor.
3. This microprocessor had major improvement over the
execution speed of 8085.
4. It is available as 40-pin Dual-Inline-Package (DIP).
5. It is available in three versions:
a. 8086 (5 MHz)
b. 8086-2 (8 MHz)
c. 8086-1 (10 MHz)
6. It consists of 29,000 transistors.
 Block Diagram of 8086 Microprocessor
57
 Block Diagram of 8086 Microprocessor
58

The 8086 CPU is divided into two independent

functional units:
1. Bus Interface Unit (BIU)
2. Execution Unit (EU)
Bus Interface Unit (BIU)
The function of BIU is to:
■ Fetch the instruction or data from memory.
■ Write the data to memory.
■ Write the data to the port.
■ Read data from the port.
 Block Diagram of 8086 Microprocessor
59

Instruction Queue
To increase the execution speed, BIU fetches as many
as six instruction bytes ahead to time from memory.
All six bytes are then held in first in first out 6 byte
register called instruction queue.
Then all bytes have to be given to EU one by one.
This pre fetching operation of BIU may be in parallel
with execution operation of EU, which improves the
speed execution of the instruction.
 Block Diagram of 8086 Microprocessor
60

Execution Unit (EU)

The functions of execution unit are:
To tell BIU where to fetch the instructions or data from.
To decode the instructions.
To execute the instructions.
The EU contains the control circuitry to perform various
internal operations. A decoder in EU decodes the
instruction fetched memory to generate different
internal or external control signals required to perform
the operation. EU has 16-bit ALU, which can perform
arithmetic and logical operations on 8-bit as well as
16-bit.
 Block Diagram of 8086 Microprocessor
61

General Purpose Registers of 8086

These registers can be used as 8-bit registers individually or can
be used as 16-bit in pair to have AX, BX, CX, and DX.
■ AX Register: AX register is also known as accumulator
register that stores operands for arithmetic operation like
divided, rotate.
■ BX Register: This register is mainly used as a base register.
It holds the starting base location of a memory region within
a data segment.
■ CX Register: It is defined as a counter. It is primarily used
in loop instruction to store loop counter.
■ DX Register: DX register is used to contain I/O port address
for I/O instruction.
 Block Diagram of 8086 Microprocessor
62

Segment Registers
Additional registers called segment registers generate memory address when combined
with other in the microprocessor. In 8086 microprocessor, memory is divided into 4
segments as follow :
 Block Diagram of 8086 Microprocessor
63

1. Code Segment (CS): The CS register is used for addressing a

memory location in the Code Segment of the memory, where the
executable program is stored.
2. Data Segment (DS): The DS contains most data used by
program. Data are accessed in the Data Segment by an offset
address or the content of other register that holds the offset
address.
3. Stack Segment (SS): SS defined the area of memory used for
the stack.
4. Extra Segment (ES): ES is additional data segment that is used
by some of the string to hold the destination data.
 Block Diagram of 8086 Microprocessor
64

Pointers and index registers.

The pointers contain within the particular segments. The pointers IP, BP, SP
usually contain offsets within the code, data and stack segments respectively
1.Stack Pointer (SP) is a 16-bit register pointing to program stack in stack
segment.
2.Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP
register is usually used for based, based indexed or register indirect addressing.
3.Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed
and register indirect addressing, as well as a source data addresses in string
manipulation instructions.
4.Destination Index (DI) is a 16-bit register. DI is used for indexed, based
indexed and register indirect addressing, as well as a destination data address in
string manipulation instructions.
 Block Diagram of 8086 Microprocessor
65

Flag Registers of 8086

Flag register in EU is of 16-bit and is shown in fig. 3:

Fig. 3: Flag Register of 8086

Flags Register determines the current state of the processor. They are modified
automatically by CPU after mathematical operations, this allows to determine
the type of the result, and to determine conditions to transfer control to other
parts of the program.
8086 has 9 flags and they are divided into two categories:
1. Conditional Flags
2. Control Flags
 Block Diagram of 8086 Microprocessor
66

1. Conditional Flags
Conditional flags represent result of last arithmetic or logical instruction executed.
Conditional flags are as follows:
Carry Flag (CF): This flag indicates an overflow condition for unsigned integer
1.
arithmetic. It is also used in multiple-precision arithmetic.
Auxiliary Flag (AF): If an operation performed in ALU generates a carry/barrow from
2.
lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), the AF flag is set i.e. carry
given by D3 bit to D4 is AF flag. This is not a general-purpose flag, it is used internally
by the processor to perform Binary to BCD conversion.
Parity Flag (PF): This flag is used to indicate the parity of result. If lower order 8-bits
3.

of the result contains even number of 1’s, the Parity Flag is set and for odd number of
1’s, the Parity Flag is reset.
Zero Flag (ZF): It is set; if the result of arithmetic or logical operation is zero else it is
4.

reset.
Sign Flag (SF): In sign magnitude format the sign of number is indicated by MSB bit. If
5.
the result of operation is negative, sign flag is set.
 Block Diagram of 8086 Microprocessor
67

6. Overflow Flag (OF): It occurs when signed numbers are added or subtracted. An OF
indicates that the result has exceeded the capacity of machine.
2. Control Flags
Control flags are set or reset deliberately to control the operations of the execution unit. Control flags
are as follows:
Trap Flag (TP):
1.

It is used for single step control.

It allows user to execute one instruction of a program at a time for debugging.
When trap flag is set, program can be run in single step mode.
Interrupt Flag (IF):
2.

It is an interrupt enable/disable flag.

If it is set, the maskable interrupt of 8086 is enabled and if it is reset, the interrupt is disabled.
It can be set by executing instruction sit and can be cleared by executing CLI instruction.
Direction Flag (DF):
3.

It is used in string operation.

If it is set, string bytes are accessed from higher memory address to lower memory address.
When it is reset, the string bytes are accessed from lower memory address to higher memory address.
8086 Pin Configuration
 Pins and Signals Common signals
70

AD0-AD15 (Bidirectional)

Address/Data bus

Low order address bus; these are

multiplexed with data.

When AD lines are used to transmit

memory address the symbol A is used
instead of AD, for example A0-A15.

When data are transmitted over AD lines

the symbol D is used in place of AD, for
example D0-D7, D8-D15 or D0-D15.

A16/S3, A17/S4, A18/S5, A19/S6

High order address bus. These are

multiplexed with status signals
 Pins and Signals
71
Common signals
BHE (Active Low)/S7 (Output)

Bus High Enable/Status

It is used to enable data onto the most

significant half of data bus, D8-D15. 8-bit
device connected to upper half of the
data bus use BHE (Active Low) signal. It
is multiplexed with status signal S7.

MN/ MX

MINIMUM / MAXIMUM

This pin signal indicates what mode the

processor is to operate in.

RD (Read) (Active Low)

The signal is used for read operation.

It is an output signal.
It is active when low.
 Pins and Signals Common signals
72

READY
This is the acknowledgement from the
slow device or memory that they have
completed the data transfer.

The signal made available by the devices

is synchronized by the 8284A clock
generator to provide ready input to the
8086.
The signal is active high.
 Pins and Signals
73
Common signals

RESET (Input)
Causes the processor to immediately
terminate its present activity.
The signal must be active HIGH for at
least four clock cycles.

CLK
The clock input provides the basic timing
for processor operation and bus control
activity. Its an asymmetric square wave
with 33% duty cycle.

INTR Interrupt Request

This is a triggered input. This is sampled
during the last clock cycles of each
instruction to determine the availability
of the request. If any interrupt request is
pending, the processor enters the
interrupt acknowledge cycle.

This signal is active high and internally

synchronized.
 Pins and Signals
Min/ Max Pins
74
The 8086 microprocessor can work in two
modes of operations : Minimum mode and
Maximum mode.

In the minimum mode of operation the

microprocessor do not associate with any
co-processors and can not be used for
multiprocessor systems.

In the maximum mode the 8086 can work

in multi-processor or co-processor
configuration.

Minimum or maximum mode operations

are decided by the pin MN/ MX(Active low).

When this pin is high 8086 operates in

minimum mode otherwise it operates in
Maximum mode.
 Pins and Signals
75 Minimum mode signals

ALE (Address Latch Enable) Used to demultiplex the

address and data lines using external latches
 Pins and Signals
76

Minimum mode signals

HOLD Input signal to the processor form the bus masters

as a request to grant the control of the bus.

Usually used by the DMA controller to get the

control of the bus.

HLDA (Hold Acknowledge) Acknowledge signal by the

processor to the bus master requesting the control
of the bus through HOLD.

The acknowledge is asserted high, when the

processor accepts HOLD.
 Pins and Signals
77

Maximum mode signals

 Pins and Signals
78
Maximum mode signals
 Pins and Signals
79 Maximum mode signals
 8086 Microprocessor
80

● Memory Organization
● Each byte in memory has a 20 bit address starting with 0 to 220-1 or 1 meg
of addressable memory
● Addresses are expressed as 5 hex digits from 00000 - FFFFF
● Problem: But 20 bit addresses are TOO BIG to fit in 16 bit registers!
● Solution: Memory Segment
● Block of 64K (65,536) consecutive memory bytes
● A segment number is a 16 bit number
● Segment numbers range from 0000 to FFFF
● Within a segment, a particular memory location is specified
with an offset
● An offset also ranges from 0000 to FFFF
 8086 Microprocessor
81
 8086 Microprocessor
82

◻ Segmented Memory
Segmented memory addressing: absolute (linear) address is a combination of a
16-bit segment value added to a 16-bit offset
addresses

one segment
linear
Intel
8086 Microprocessor

• Memory Address Generation

• The BIU has a dedicated adder for determining physical memory addresses

Offset Value (16 bits)

Segment Register (16 bits) 0000

Adder

Physical Address (20 Bits)

 Intel
8086 Microprocessor

Example Address Calculation

•If the data segment starts at location 1000h and a
data reference contains the address 29h where is
the actual data? 2 9

Offset: 0000000000101001

Segment: 0001000000000000 0000

Address: 0001000000000010 1001

 8086 Microprocessor

Segment:Offset Address
•Logical Address is specified as segment:offset
•Physical address is obtained by shifting the segment address 4
bits to the left and adding the offset address
•Thus the physical address of the logical address A4FB:4872 is
A4FB0
+ 4872
A9822
8086 Microprocessor
Your turn . . .

What linear address corresponds to the segment/offset

address 028F:0030?

028F0 + 0030 = 02920

Always use hexadecimal notation for addresses.

Your turn . . .
What segment addresses correspond to the linear address
28F30h?

Many different segment-offset addresses can produce the

linear address 28F30h. For example:
28F0:0030, 28F3:0000, 28B0:0430, . . .
 The Code Segment
0H

4000H
CS: 0400H

IP 0056H 4056H
CS:IP = 400:56
Logical Address

Memory
0400 0
Segment Register

Offset + 0056
Physical or 04056H 0FFFFFH
Absolute Address

The offset is the distance in bytes from the start of the segment.
The offset is given by the IP for the Code Segment.
Instructions are always fetched with using the CS register.

The physical address is also called the absolute address.

TIMING DIAGRAM OF
8085
Timing diagram of 8085

◻ Timing diagram is the display of initiation of read/write and transfer of data

operations under the control of 3-status signals IO / M , S1, and S0.
◻ As the heartbeat is required for the survival of the human being, the CLK is
required for the proper operation of different sections of the microprocessors.
All actions in the microprocessor is controlled by either leading or trailing edge
of the clock.
◻ If I ask a man to bring 6-bags of wheat, each weighing 100 kg, he may take
6-times to perform this task in going and bringing it. A stronger man might
perform the same task in 3- times only.
◻ Thus, it depends on the strength of the man to finish the job quickly or slowly.
◻ Here, we can assume both weaker and strong men as machine. The weaker man
has taken 6-machine cycle (6-times going and coming with one bag each time)
to execute the job where as the stronger
man has taken only 3-machine cycle for the same job.
◻ Similarly, a machine may execute one instruction in as many as 3-machine
cycles while the other machine can take only one machine cycle to execute the
same instruction.
Timing diagram of 8085

◻ Thus, the machine that has taken only one machine cycle is efficient than the
one taking 3-machine cycle.
◻ Each machine cycle is composed of many clock cycle. Since, the data and
instructions, both are stored in the memory, the µP performs fetch operation to
read the instruction or data and then execute the instruction.
◻ The µP in doing so may take several cycles to perform fetch and execute
operation.
◻ The 3-status signals : IO / M , S1, and S0 are generated at the beginning of each
machine cycle.
◻ The unique combination of these 3-status signals identify read or write
operation and remain valid for the duration of the cycle.
◻ Table- shows details of the unique combination of these status signals to
identify different machine cycles.
◻ Thus, time taken by any µP to execute one instruction is calculated in terms of
the clock period.
Timing diagram of 8085

Table. Machine cycle status and control signals

Processor Cycle

◻ The function of the microprocessor is divided into fetch and

execute cycle of any instruction of a program.
◻ The program is nothing but number of instructions stored in the
memory in sequence.
◻ Thus, an instruction cycle is defined as the time required to
fetch and execute an instruction.
◻ For executing any program, basically 2-steps are followed
sequentially with the help of clocks Fetch, and Execute.
◻ The time taken by the µP in performing the fetch and execute
operations are called fetch and execute cycle.
◻ Thus, sum of the fetch and execute cycle is called the
instruction cycle as indicated in Fig.
Instruction Cycle (IC) = Fetch cycle (FC) + Execute Cycle
(EC)
Fig (a) Processor cycle
Opcode Fetch
◻ The 1st step in communicating between the microprocessor and
memory is reading from the memory. This reading process is
called opcode fetch.
◻ The process of opcode fetch operation requires minimum
4-clock cycles T1, T2, T3, and T4 and is the 1st machine cycle
(M1) of every instruction.
◻ In order to differentiate between the data byte pertaining to an
opcode or an address, the machine cycle takes help of the status
signal IO/ M , S1, and S0.
◻ The IO/ M = 0 indicates memory operation and S1 = S0 = 1
indicates Opcode fetch operation.
◻ The opcode fetch machine cycle M1 consists of 4-states (T1,
T2, T3, and T4).
◻ The 1st 3- states are used for fetching (transferring) the byte
from the memory and the 4th-state is used to decode it.
Timing Diagram of Opcode Fetch
◻ The process of opcode fetch operation requires minimum 4-clock cycles
T1, T2, T3, and T4 and is the 1st machine cycle (M1) of every
instruction.
Example
Fetch a byte 41H stored at memory location 2105H.
For fetching a byte, the microprocessor must find out the memory
location where it is stored.
Then provide condition (control) for data flow from memory to the
microprocessor.
The µP fetches opcode of the instruction from the memory as per the
sequence below
• A low IO/ M means microprocessor wants to communicate with
memory.
• The µP sends a high on status signal S1 and S0 indicating fetch
operation.
• The µP sends 16-bit address. AD bus has address in 1st clock of the
1st machine cycle, T1 .
• AD 7 to AD0 address is latched in the external latch when ALE = 1.
Timing Diagram of Opcode Fetch

• In T 2, the RD control signal becomes low to enable the

memory for read operation.
• The memory places opcode on the AD bus
• The data is placed in the data register (DR) and then it is
transferred to IR
◻ During T3 the RD signal becomes high and memory is
disabled.
◻ During T4 the opcode is sent for decoding and decoded in T4.
◻ The execution is also completed in T4 if the instruction is
single byte.
◻ More machine cycles are essential for 2- or 3-byte instructions.
The 1st machine cycle M1 is meant for fetching the opcode.
The machine cycles M2 and M3 are required either to read/
write data or address from the memory or I/O devices.
Timing Diagram of Opcode Fetch
Timing Diagram of Opcode Fetch
Example
Opcode fetch MOV B,C.
T1 : The 1st clock of 1st machine cycle (M1) makes ALE high indicating
address latch enabled which loads low-order address 00H on AD7 ⇔ AD0
and high-order address 10H simultaneously on A15 ⇔ A8. The address
00H is latched in T1.
T2 : During T2 clock, the microprocessor issues RD control signal to
enable the memory and memory places 41H from 1000H location on the
data bus.
T3 : During T3, the 41H is placed in the instruction register and RD = 1
(high) disables signal. It means the memory is disabled in T3 clock cycle.
The opcode cycle is completed by end of T3 clock cycle.
T4 : The opcode is decoded in T4 clock and the action as per 41H is taken
accordingly. In other word, the content of C-register is copied in
B-register.
Execution time for opcode 41H is Clock frequency of 8085 = 3.125 MHz
Time (T) for one clock = 1/3.125 MHz = 325.5 ns = 0.32 µS
Execution time for opcode fetch = 4T = 4*0.32 µS = 1.28 µS
Timing Diagram of Opcode Fetch

Fig. Timing Diagram of Opcode fetch

Timing Diagram of Opcode Fetch
Explain the execution of MVI B,05H stored at locations indicated below

The MVI B,05H instruction requires 2-machine cycles (M1 and M2).
M1 requires 4-states and M2 requires 3-states, total of 7-states as shown in Fig. 5.3 (d). Status signals IO/ M , S1 and
S0 specifies the 1st machine cycle as the op-code fetch.
In T1-state, the high order address {10H} is placed on the bus A15 ⇔ A8 and low-order
address {00H} on the bus AD7 ⇔ AD0 and ALE = 1.
In T2 -state, the RD line goes low, and the data 06H from memory location 1000H are placed on the data bus.
The fetch cycle becomes complete in T3-state.
The instruction is decoded in the T4-state. During T4-state, the contents of the bus are unknown.
With the change in the status signal, IO/ M = 0, S1 = 1 and S0 = 0, the 2nd machine cycle is identified as the memory
read.
The address is 1001H and the data byte [05H] is fetched via the data bus.
Both M1 and M2 perform memory read operation, but the M1
is called op-code fetch i.e., the 1st machine cycle of each instruction is identified as the opcode
fetch cycle.
Execution time for MBI B,05H i.e., memory read machine cycle and instruction cycle
is
Timing Diagram of Opcode Fetch
Timing Diagram of Read
Read Cycle
The high order address (A15 ⇔ A8) and low order address (AD7 ⇔ AD0) are asserted on 1st low going transition of
the clock pulse. The timing diagram for IO/M read are shown in Fig.5.3 (e) and ( f). The A15 ⇔ A8 remains valid in
T1, T2, and T3 i.e. duration of the bus cycle, but AD7 ⇔ AD0 remains valid only in T1. Since it has to remain valid
for the whole bus cycle, it must be saved for its use in the T2 and T3.
ALE is asserted at the beginning of T1 of each bus cycle and is negated towards the end of T1. ALE is active during
T1 only and is used as the clock pulse to latch the address (AD7 ⇔AD0) during T1. The RD is asserted near the
beginning of T2. It ends at the end of T3. As soon as the RD becomes active, it forces the memory or I/O port to
assert data. RD becomes inactive towards the end of T3, causing the port or memory to terminate the data.
Timing Diagram of I/O Read

Fig: I/O Read timing diagram

Timing Diagram of Memory
Write

Fig: Memory Write timing diagram

Timing Diagram of IO Write

Fig: IO Write timing diagram

Timing Diagram of STA

Fig: timing diagram of STA

 Zelalem Birhanu, AAiT 108

8086 Instruction Set

 In this lecture
109

◻ Introduction
◻ 8086 Instruction Types
◻ 8086 Addressing Modes
 Introduction – recap
110

There are three language levels that can be used to write

◻
a program for a microcomputer

❑ Machine language
❑ Assembly Language
❑ High-Level Language
 Introduction – recap…cntd
111

Machine Language

These are the binary codes for the instructions you want
◻

the microcomputer to execute

11101001000000000101000

◻ It is hard or impossible for a programmer to write code

in machine language, because it requires memorizing all the
instructions in binary form and soon the program will
get out of control!
 Introduction – recap…cntd
112

Assembly Language

Uses two, three, or four letter mnemonics to represent each instruction

◻
type

◻The letters in an assembly language mnemonic are usually initials or a

short form of the English word(s) for the operation performed by the
instruction
e.g., SUB for subtract , XOR for Exclusive OR , etc

Assembly language program has to be translated to

◻

machine language so that it can be loaded into memory

and run – This is done by the assembler
 Introduction – recap…cntd
113

High-Level Languages

These languages use program statements which are even more

◻
English-like than those of assembly language
e.g. BASIC, C, C++, Java, ...

Each high-level statement may represent many machine code

◻

instructions

An interpreter (compiler) program is used to translate higher-level

◻

language statements to machine codes, which can be loaded into

memory and executed.
 Introduction – recap…cntd
114

◻ Elements of an instruction

Operation Addresses
Code (Opcode) (operands)

◻ 8086 has variable-length instructions (8 bits to 40 bits)

 8086 Instruction Types
115

◻ The 8086 instructions can be grouped in to six categories

❑ Data transfer instructions

❑ Arithmetic instructions
❑ Bit manipulation instructions
❑ String manipulation instructions
❑ Control transfer instructions
❑ Processor control instructions
 Data Transfer Instructions
116

◻ Used to transfer data from source operand to destination

operand
❑ Memory to register e.g. MOV AX, [0005h] (AX←[0005h])
❑ Register to memorye.g. PUSH AL
❑ Immediate to memory/register e.g. MOV AH, 09h
❑ I/O device to register e.g. IN AX, 4
❑ Register to I/O device e.g. OUT AL, 2

◻ All the store, move, load, exchange, input and output

instructions belong to this category
MOV , PUSH, POP , XCHG, XLAT, IN, OUT, LEA, PUSHF,
POPF
 Arithmetic instructions
117

◻ Perform arithmetic operations

❑ Addition e.g. ADD, ADC, INC, AAA,
❑ Subtraction e.g. SUB, SBB, DEC, CMP
❑ Multiplication e.g. MUL, IMUL
❑ Division e.g. DIV, IDIV

e.g. ADD AL, 5 (AL←AL+5)

MUL BL (AX ←AL*BL)
MUL BX (DX:AX ←AX*BX)
 String Manipulation Instructions
118

◻ A string is a series of bytes or a series of words in sequential

memory locations. It often consists of ASCII character
codes

e.g. LODSB – Load byte at DS: [SI] into AL. Update SI

STOSW – Store word in AX into ES:[DI]. Update DI
CMPSB – Compare bytes: ES:[DI] from DS:[SI]
 Bit Manipulation Instructions
119

◻ Logical instructions
NOT, AND, OR, XOR
◻ Shift instructions
SHL, SHR, SAL, SAR
CF Byte/Word
◻ Rotate instructions
RCL
ROL, ROR, RCL, RCR

CF Byte/Word
RCR

e.g. MOV AL, 1Ch (AL←1Ch (00011100b))

ROR AL, 1 (rotate AL one bit to the right) (AL = 00001110b)
 Control Transfer Instructions
120

◻ These instructions are used to tell the processor to start

fetching instructions from some new address, rather than
continuing in sequence
❑ Unconditional transfer instructions e.g. CALL, RET, JMP
❑ Conditional transfer instructions e.g. JE, JG, JGE, JL, JLE, JZ
❑ Iteration control instructions e.g. LOOP, LOOPE, JCXZ
❑ Interrupt instructions e.g. INT, IRET

e.g. SUB AX, 32 AX=AX-32;

JZ label If(AX==0)
{
… BX=10;
label: }
MOV BX, 10
 Processor Control Instructions
121

◻ Set/clear flags, control the operation of the processor

❑ Flag instructions
❑ e.g. STC – set carry flag
❑ External hardware synchronization instructions
❑ e.g. WAIT - Do nothing until signal on the TEST pin is low
❑ No operation instructions e.g. NOP
 Addressing Modes
122

◻ Describe the types of operands and the way they are

accessed for executing an instruction

◻ 8086 addressing modes:

❑ Immediate
❑ Direct
❑ Register
❑ Register Indirect
❑ Indexed
❑ Register Relative
❑ Based Indexed
❑ Relative Based Indexed
 Immediate Addressing
123

◻ Immediate data is a part of instruction, and appears in

the form of successive byte(s)

e.g. MOV AX, 0005H (AX←0005H)

Here, 0005H is the immediate data. The immediate

data may be 8-bit or 16-bit in size.
 Direct Addressing
124

◻ In the direct addressing mode, a 16-bit memory address

(offset) is directly specified in the instruction

e.g. MOV AX, [5000H ] (AX←[DS:5000H])

Here, data resides in a memory location in the data

segment, whose effective address may be computed
using 5000H as the offset address and content of DS
as segment address.
 Register Addressing
125

◻ In register addressing mode, the data is stored in a register

and it is referred using the particular register

◻ All the registers, except IP, may be used in this mode

e.g. MOV AX, BX (AX←BX)

Here, data is transferred from register BX to register AX

 Register Indirect Addressing
126

◻ Sometimes, the address of the memory location, which

contains data or operand, is determined in an indirect way,
using the offset registers

◻ The offset address of data is in either BX, SI or DI registers.

The default segment is either DS or ES.

e.g. MOV AX, [BX ] (AX←[DS:BX])

Here, data is present in a memory location in DS whose

offset address is in BX.
 Indexed Addressing
127

◻ Offset of the operand is stored in one of the index registers

(SI and DI). DS and ES are the default segments for SI and
DI respectively
◻ This mode is a special case of register indirect addressing
mode

e.g. MOV AX, [SI ] (AX←[DS:SI])

Here, data is present in a memory location in DS whose

offset address is in SI.
 Register Relative Addressing
128

◻ The data is available at an effective address formed by

adding an 8-bit or 16-bit displacement with the content of
any one of the registers BX, BP, SI and DI in the default
segment (DS or ES)

e.g. MOV AX, 50H[BX ] (AX←

[DS:BX+50H])
 Based Indexed Addressing
129

◻ The effective address of data is formed by adding content of

a base register (BX or BP) to the content of an index
register (SI or DI)

e.g. MOV AX, [BX ][SI] (AX←[DS:BX+SI])

 Relative Based Indexed Addressing
130

◻ The effective address is formed by adding an 8 or 16-bit

displacement with the sum of contents of any one of the
base registers (BX or BP) and any one of the index registers
(SI or DI), in a default segment

e.g. MOV AX, 50H[BX ][SI] (AX←

[DS:BX+SI+50])
131

◻ Thank U