ICX409AK

Diagonal 6mm (Type 1/3) CCD Image Sensor for PAL Color Video Cameras

Description
The ICX409AK is an interline CCD solid-state 16 pin DIP (Plastic)
image sensor suitable for PAL color video cameras
with a diagonal 6mm (Type 1/3) system. Compared
with the conventional product ICX059CK, basic
characteristics such as sensitivity, smear, dynamic
range and S/N are improved drastically.
This chip features a field period readout system and
an electronic shutter with variable charge-storage
time.
This chip is suitable for applications such as surveillance
cameras, automotive cameras, etc.

AAAAA
Features
• High sensitivity (+6dB compared with the ICX059CK)

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• Low smear (–15dB compared with the ICX059CK) Pin 1
2
• High D range (+5dB compared with the ICX059CK)

AAAAA
• High S/N

AAAAA
• High resolution and low dark current V
• Excellent antiblooming characteristics

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• Ye, Cy, Mg, and G complementary color mosaic filters on chip
12
• Continuous variable-speed shutter
• No voltage adjustment 3
H 40
(Reset gate and substrate bias are not adjusted.) Pin 9
• Reset gate: 5V drive
• Horizontal register: 5V drive Optical black position
(Top View)
Device Structure
• Interline CCD image sensor
• Image size: Diagonal 6mm (Type 1/3)
• Number of effective pixels: 752 (H) × 582 (V) approx. 440K pixels
• Total number of pixels: 795 (H) × 596 (V) approx. 470K pixels
• Chip size: 5.59mm (H) × 4.68mm (V)
• Unit cell size: 6.50µm (H) × 6.25µm (V)
• Optical black: Horizontal (H) direction : Front 3 pixels, rear 40 pixels
Vertical (V) direction : Front 12 pixels, rear 2 pixels
• Number of dummy bits: Horizontal 22
Vertical 1 (even fields only)
• Substrate material: Silicon

∗Super HAD CCD is a trademark of Sony Corporation. The Super HAD CCD is a version of Sony's high performance CCD HAD (Hole-
Accumulation Diode) sensor with sharply improved sensitivity by the incorporation of a new semiconductor technology developed by Sony
Corporation.

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

–1–
E00611B28
 ICX409AK

Block Diagram and

VOUT

GND

Vφ1

Vφ3

Vφ4
Vφ2
NC

NC
Pin Configuration
8 7 6 5 4 3 2 1
(Top View)

Cy Ye Cy Ye

Vertical Register
G Mg G Mg

Cy Ye Cy Ye

G Mg G Mg

Cy Ye Cy Ye

Mg G Mg G Note)

Horizontal Register
Note) : Photo sensor

9 10 11 12 13 14 15 16
GND

φRG

Hφ1
VL

NC
φSUB

Hφ2
VDD

Pin Description
Pin No. Symbol Description Pin No. Symbol Description
1 Vφ4 Vertical register transfer clock 9 VDD Supply voltage
2 Vφ3 Vertical register transfer clock 10 GND GND
3 Vφ2 Vertical register transfer clock 11 φSUB Substrate clock
4 Vφ1 Vertical register transfer clock 12 VL Protective transistor bias
5 GND GND 13 φRG Reset gate clock
6 NC 14 NC
7 NC 15 Hφ1 Horizontal register transfer clock
8 VOUT Signal output 16 Hφ2 Horizontal register transfer clock

Absolute Maximum Ratings

Item Ratings Unit Remarks
VDD, VOUT, φRG – φSUB –40 to +8 V
Vφ1, Vφ3 – φSUB –50 to +15 V
Against φSUB
Vφ2, Vφ4, VL – φSUB –50 to +0.3 V
Hφ1, Hφ2, GND – φSUB –40 to +0.3 V
VDD, VOUT, φRG – GND –0.3 to +20 V
Against GND Vφ1, Vφ2, Vφ3, Vφ4 – GND –10 to +18 V
Hφ1, Hφ2 – GND –10 to +6 V
Vφ1, Vφ3 – VL –0.3 to +28 V
Against VL
Vφ2, Vφ4, Hφ1, Hφ2, GND – VL –0.3 to +15 V
Voltage difference between vertical clock input pins to +15 V ∗1
Between input clock
Hφ1 – Hφ2 –6 to +6 V
pins
Hφ1, Hφ2 – Vφ4 –14 to +14 V
Storage temperature –30 to +80 °C
Operating temperature –10 to +60 °C
∗1 +24V (Max.) when clock width < 10µs, clock duty factor < 0.1%.
–2–
 ICX409AK

Bias Conditions
Item Symbol Min. Typ. Max. Unit Remarks
Supply voltage VDD 14.55 15.0 15.45 V
Protective transistor bias VL ∗1

Substrate clock φSUB ∗2

∗1 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL
power supply for the V driver should be used.
∗2 Do not apply a DC bias to the substrate clock pin, because a DC bias is generated within the CCD.

DC Characteristics
Item Symbol Min. Typ. Max. Unit Remarks
Supply current IDD 4 6 mA

Clock Voltage Conditions

Waveform
Item Symbol Min. Typ. Max. Unit Remarks
diagram
Readout clock voltage VVT 14.55 15.0 15.45 V 1
VVH1, VVH2 –0.05 0 0.05 V 2 VVH = (VVH1 + VVH2)/2
VVH3, VVH4 –0.2 0 0.05 V 2
VVL1, VVL2,
–8.0 –7.0 –6.5 V 2 VVL = (VVL3 + VVL4)/2
VVL3, VVL4
VφV 6.3 7.0 8.05 V 2 VφV = VVHn – VVLn (n = 1 to 4)
Vertical transfer clock VVH3 – VVH –0.25 0.1 V 2
voltage
VVH4 – VVH –0.25 0.1 V 2
VVHH 0.3 V 2 High-level coupling
VVHL 0.3 V 2 High-level coupling
VVLH 0.3 V 2 Low-level coupling
VVLL 0.3 V 2 Low-level coupling

Horizontal transfer VφH 4.75 5.0 5.25 V 3

clock voltage VHL –0.05 0 0.05 V 3
Input through 0.1µF
VφRG 4.5 5.0 5.5 V 4
capacitance
VRGLH – VRGLL 0.4 V 4 Low-level coupling
Reset gate clock
voltage VRGL – VRGLm 0.5 V 4 Low-level coupling

VDD VDD VDD

VRGH V 4
+0.3 +0.6 +0.9

Substrate clock voltage VφSUB 21.0 22.0 23.5 V 5

–3–
 ICX409AK

Clock Equivalent Circuit Constant

Item Symbol Min. Typ. Max. Unit Remarks

Capacitance between vertical transfer CφV1, CφV3 1500 pF

clock and GND CφV2, CφV4 1000 pF
CφV12, CφV34 820 pF

Capacitance between vertical transfer CφV23, CφV41 330 pF

clocks CφV13 120 pF
CφV24 100 pF
Capacitance between horizontal
CφH1, CφH2 75 pF
transfer clock and GND
Capacitance between horizontal
CφHH 22 pF
transfer clocks
Capacitance between reset gate clock
CφRG 5 pF
and GND
Capacitance between substrate clock
CφSUB 270 pF
and GND
R1, R3 100 Ω
Vertical transfer clock series resistor
R2, R4 150 Ω
Vertical transfer clock ground resistor RGND 68 Ω
Horizontal transfer clock series resistor RφH 15 Ω
Reset gate clock series resistor RφRG 50 Ω

Vφ1 Vφ2

CφV12
R1 R2
RφH RφH
Hφ1 Hφ2
CφV1 CφV2 CφHH
CφV41 CφV23
CφH1 CφH2

CφV24 CφV13
CφV4 RGND CφV3
R4 R3
CφV34

Vφ4 Vφ3

Vertical transfer clock equivalent circuit Horizontal transfer clock equivalent circuit
RφRG
RGφ

CφRG

Reset gate clock equivalent circuit

–4–
 ICX409AK

Drive Clock Waveform Conditions

(1) Readout clock waveform
100%
90%

II II
φM

VVT
φM
2
10%
0% 0V
tr twh tf

(2) Vertical transfer clock waveform

Vφ1 Vφ3

VVH1 VVHH VVHH

VVH VVHH VVHH VVH

VVHL VVHL
VVHL
VVHL VVH3

VVL1 VVL3 VVLH

VVLH

VVLL VVLL
VVL VVL

Vφ2 Vφ4

VVHH VVHH VVHH VVHH

VVH VVH

VVHL
VVH2 VVHL VVHL VVHL
VVH4

VVLH VVLH
VVL2

VVLL VVLL
VVL VVL
VVL4

VVH = (VVH1 + VVH2)/2

VVL = (VVL3 + VVL4)/2
VφV = VVHn – VVLn (n = 1 to 4)
–5–
 ICX409AK

(3) Horizontal transfer clock waveform

tr twh tf

90%

VφH twl

10%

VHL

(4) Reset gate clock waveform

tr twh tf

VRGH

twl

Point A
RG waveform VφRG

VRGLH
VRGL
VRGLL
VRGLm

Hφ1 waveform
VφH/2 [V]

VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from
Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and
VRGLL.
VRGL = (VRGLH + VRGLL)/2
Assuming VRGH is the minimum value during the interval twh, then:
VφRG = VRGH – VRGL
Negative overshoot level during the falling edge of RG is VRGLm.

(5) Substrate clock waveform

100%
90%

φM

VφSUB φM
2
10%
VSUB 0%
tr twh tf
(A bias generated within the CCD)

–6–
 ICX409AK

Clock Switching Characteristics

twh twl tr tf
Item Symbol Unit Remarks
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
During
Readout clock VT 2.3 2.5 0.5 0.5 µs
readout
Vertical transfer Vφ1, Vφ2,
15 250 ns ∗1
clock Vφ3, Vφ4
Hφ1 26 28.5 26 28.5 6.5 9.5 6.5 9.5
transfer clock

ns ∗2
During
Horizontal

imaging Hφ2 26 28.5 26 28.5 6.5 9.5 6.5 9.5

During Hφ1 5.38 0.01 0.01
parallel-serial µs
conversion Hφ2 5.38 0.01 0.01

Reset gate clock φRG 11 13 51 3 3 ns

During drain
Substrate clock φSUB 1.5 1.8 0.5 0.5 µs
charge
∗1 When vertical transfer clock driver CXD1267AN is used.
∗2 tf ≥ tr – 2ns, and the cross-point voltage (VCR) for the Hφ1 rising side of the Hφ1 and Hφ2 waveforms must be
at least VφH/2 [V].

two
Item Symbol Unit Remarks
Min. Typ. Max.
Horizontal transfer clock Hφ1, Hφ2 22 26 ns ∗3

∗3 The overlap period for twh and twl of horizontal transfer clocks Hφ1 and Hφ2 is two.

–7–
 ICX409AK

Image Sensor Characteristics (Ta = 25°C)

Item Symbol Min. Typ. Max. Unit Measurement method Remarks
Sensitivity S 760 950 mV 1
RMgG 0.93 1.35 2
Sensitivity ratio
RYeCy 1.15 1.48 2
Saturation signal Ysat 1000 mV 3 Ta = 60°C
Smear Sm –110 –93 dB 4
20 % 5 Zone 0 and I
Video signal shading SHy
25 % 5 Zone 0 to II'

Uniformity between video ∆Sr 10 % 6

signal channels ∆Sb 10 % 6
Dark signal Ydt 2 mV 7 Ta = 60°C
Dark signal shading ∆Ydt 1 mV 8 Ta = 60°C
Flicker Y Fy 2 % 9
Flicker R-Y Fcr 5 % 9
Flicker B-Y Fcb 5 % 9
Line crawl R Lcr 3 % 10
Line crawl G Lcg 3 % 10
Line crawl B Lcb 3 % 10
Line crawl W Lcw 3 % 10
Lag Lag 0.5 % 11

Zone Definition of Video Signal Shading

752 (H)
12 12

8
V
10
H H
8 8 582(V)

Zone 0, I 6
Zone II, II'
Ignored region
V
10 Effective pixel region

Measurement System
[∗Y]
[∗A]
CCD signal output LPF1 Y signal output

(3dB down 6.3MHz)

CCD C.D.S AMP

S
H [∗C]
LPF2 Chroma signal output
SH
(3dB down 1MHz)

Note) Adjust the amplifier gain so that the gain between [∗A] and [∗Y] , and between [∗A] and [∗C] equals 1.
–8–
 ICX409AK

Image Sensor Characteristics Measurement Method

Measurement conditions

1) In the following measurements, the device drive conditions are at the typical values of the bias and clock
voltage conditions.

2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical
black level (OB) is used as the reference for the signal output, which is taken as the value of Y signal output
or chroma signal output of the measurement system.

Color coding of this image sensor & Composition of luminance (Y) and chroma (color difference) signals

Cy Ye Cy Ye As shown in the left figure, fields are read out. The charge is
A1 mixed by pairs such as A1 and A2 in the A field. (pairs such
G Mg G Mg
as B in the B field)
B
Cy Ye Cy Ye As a result, the sequence of charges output as signals from
A2 the horizontal shift register (Hreg) is, for line A1, (G + Cy),
Mg G Mg G (Mg + Ye), (G + Cy), and (Mg + Ye).

Hreg

Color Coding Diagram

These signals are processed to form the Y signal and chroma (color difference) signal. The Y signal is formed
by adding adjacent signals, and the chroma signal is formed by subtracting adjacent signals. In other words,
the approximation:
Y = {(G + Cy) + (Mg + Ye)} × 1/2
= 1/2 {2B + 3G + 2R}
is used for the Y signal, and the approximation:
R – Y = {(Mg + Ye) – (G + Cy)}
= {2R – G}
is used for the chroma (color difference) signal. For line A2, the signals output from Hreg in sequence are
(Mg + Cy), (G + Ye), (Mg + Cy), (G + Ye).
The Y signal is formed from these signals as follows:
Y = {(G + Ye) + (Mg + Cy)} × 1/2
= 1/2 {2B + 3G + 2R}
This is balanced since it is formed in the same way as for line A1.
In a like manner, the chroma (color difference) signal is approximated as follows:
– (B – Y) = {(G + Ye) – (Mg + Cy)}
= – {2B – G}
In other words, the chroma signal can be retrieved according to the sequence of lines from R – Y and – (B – Y)
in alternation. This is also true for the B field.

–9–
 ICX409AK

Definition of standard imaging conditions

1) Standard imaging condition I:

Use a pattern box (luminance 706cd/m2, color temperature of 3200K halogen source) as a subject. (Pattern
for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter and
image at F5.6. The luminous intensity to the sensor receiving surface at this point is defined as the standard
sensitivity testing luminous intensity.

2) Standard imaging condition II:

Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles.
Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted
to the value indicated in each testing item by the lens diaphragm.

1. Sensitivity
Set to standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of
1/250s, measure the Y signal (Ys) at the center of the screen and substitute the value into the following
formula.
250
S = Ys × [mV]
50
2. Sensitivity ratio
Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y signal
output is 200mV, and then measure the Mg signal output (SMg [mV]) and G signal output (SG [mV]), and Ye
signal output (SYe [mV]) and Cy signal output (SCy [mV]) at the center of the screen with frame readout
method. Substitute the values into the following formula.

RMgG = SMg/SG
RYeCy = SYe/SCy

3. Saturation signal
Set to standard imaging condition II. After adjusting the luminous intensity to 10 times the intensity with
average value of the Y signal output, 200mV, measure the minimum value of the Y signal.

4. Smear
Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity to
500 times the intensity with average value of the Y signal output, 200mV. When the readout clock is
stopped and the charge drain is executed by the electronic shutter at the respective H blankings, measure
the maximum value YSm [mV] of the Y signal output and substitute the value into the following formula.
YSm 1 1
Sm = 20 × log × × [dB] (1/10V method conversion value)
200 500 10

5. Video signal shading

Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity so
that the average value of the Y signal output is 200mV. Then measure the maximum (Ymax [mV]) and
minimum (Ymin [mV]) values of the Y signal and substitute the values into the following formula.

SHy = (Ymax – Ymin)/200 × 100 [%]

6. Uniformity between video signal channels

Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y signal
output is 200mV, and then measure the maximum (Crmax, Cbmax [mV]) and minimum (Crmin, Cbmin
[mV]) values of the R – Y and B – Y channels of the chroma signal and substitute the values into the
following formula.

∆Sr = | (Crmax – Crmin)/200 | × 100 [%]

∆Sb = | (Cbmax – Cbmin)/200 | × 100 [%]

– 10 –
 ICX409AK

7. Dark signal
Measure the average value of the Y signal output (Ydt [mV]) with the device ambient temperature 60°C and
the device in the light-obstructed state, using the horizontal idle transfer level as a reference.

8. Dark signal shading

After measuring 7, measure the maximum (Ydmax [mV]) and minimum (Ydmin [mV]) values of the Y signal
output and substitute the values into the following formula.

∆Ydt = Ydmax – Ydmin [mV]

9. Flicker
1) Fy
Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y signal
output is 200mV, and then measure the difference in the signal level between fields (∆Yf [mV]). Then
substitute the value into the following formula.

Fy = (∆Yf/200) × 100 [%]

2) Fcr, Fcb
Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y signal
output is 200mV, insert an R or B filter, and then measure both the difference in the signal level between
fields of the chroma signal (∆Cr, ∆Cb) as well as the average value of the chroma signal output (CAr, CAb).
Substitute the values into the following formula.

Fci = (∆Ci/CAi) × 100 [%] (i = r, b)

10. Line crawls

Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y signal
output is 200mV, and then insert a white subject and R, G, and B filters and measure the difference
between Y signal lines for the same field (∆Ylw, ∆Ylr, ∆Ylg, ∆Ylb [mV]). Substitute the values into the
following formula.

Lci = (∆Yli/200) × 100 [%] (i = w, r, g, b)

11. Lag
Adjust the Y signal output value generated by strobe light to 200mV. After setting the strobe light so that it
strobes with the following timing, measure the residual signal (Ylag). Substitute the value into the following
formula.

Lag = (Ylag/200) × 100 [%]

FLD

V1

Light
Strobe light
timing

Y signal output 200mV Ylag (lag)

Output

– 11 –
 Drive Circuit

15V

1 20 100k
2 19
3 18
4 17
XSUB
5 16 1/35V 0.1
XV2 –7.0V
6 CXD1267AN
15 3.3/16V
XV1
7 14
XSG1
8 13 22/16V
XV3
9 12
XSG2
10 11
XV4

22/20V

– 12 –
1 2 3 4 5 6 7 8 100
2SK523
NC
NC

Vφ4
Vφ1
Vφ2
Vφ3
CCD OUT
VOUT

GND

3.9k
ICX409
(BOTTOM VIEW)
φRG

Hφ1
GND

VL

NC

Hφ2
VDD

φSUB

16 15 14 13 12 11 10 9
Hφ2
2200p 1M
Hφ1
0.01

100k 3.3/20V

1/20V
0.1
RG
ICX409AK
 ICX409AK

Spectral Sensitivity Characteristics (excludes both lens characteristics and light source characteristics)

1.0
Ye
0.9
Cy G
0.8

0.7
Relative Response

0.6

0.5

Mg
0.4

0.3

0.2

0.1

0
400 450 500 550 600 650 700

Wave Length [nm]

Sensor Readout Clock Timing Chart

V1
2.6
V2

Odd Field
V3

V4
1.5 2.6 2.6 2.6
33.6

0.2

V1
V2
Even Field
V3

V4

Unit : µs

– 13 –
 Drive Timing Chart (Vertical Sync)

FLD

VD

BLK

HD

1
4
3
5

2
20

15

10
25
335

325

320
330

310
315

620
625
340

– 14 –
V1

V2

V3

V4

CCD 581 2 4 6 2 4 6 582 1 3 5 1 3 5

OUT 582 13 5 1 35 581 2 4 6 2 4 6
ICX409AK
 Drive Timing Chart (Horizontal Sync)

HD

BLK

H1
H2

1
5
3
2
1
3

1
3
2
2

5
1

3
10
10
10

20
20

22

40

30

20

750

745
752
RG

– 15 –
V1

V2

V3

V4

SUB
ICX409AK
 ICX409AK

Notes on Handling

1) Static charge prevention

CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following
protective measures.
a) Either handle bare handed or use non-chargeable gloves, clothes or material.
Also use conductive shoes.
b) When handling directly use an earth band.
c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.
d) Ionized air is recommended for discharge when handling CCD image sensor.
e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges.

2) Soldering
a) Make sure the package temperature does not exceed 80°C.
b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30W
soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently.
c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering
tool, use a thermal controller of the zero cross On/Off type and connect it to ground.

3) Dust and dirt protection

Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and
dirt. Clean glass plates with the following operation as required, and use them.
a) Perform all assembly operations in a clean room (class 1000 or less).
b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should
dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized
air is recommended.)
c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass.
d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when
moving to a room with great temperature differences.
e) When a protective tape is applied before shipping, just before use remove the tape applied for
electrostatic protection. Do not reuse the tape.

4) Installing (attaching)
a) Remain within the following limits when applying a static load to the package. Do not apply any load more
than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to limited
portions. (This may cause cracks in the package.)

AAAA AAAA AAAA

Cover glass

AAAA AAAA AAAA

Plastic package
50N 50N 1.2Nm

Compressive strength Torsional strength

b) If a load is applied to the entire surface by a hard component, bending stress may be generated and the
package may fracture, etc., depending on the flatness of the bottom of the package. Therefore, for
installation, use either an elastic load, such as a spring plate, or an adhesive.

– 16 –
 ICX409AK

c) The adhesive may cause the marking on the rear surface to disappear, especially in case the regulated
voltage value is indicated on the rear surface. Therefore, the adhesive should not be applied to this area,
and indicated values should be transferred to the other locations as a precaution.
d) The notch of the package is used for directional index, and that can not be used for reference of fixing.
In addition, the cover glass and seal resin may overlap with the notch of the package.
e) If the lead bend repeatedly and the metal, etc., clash or rub against the package, the dust may be
generated by the fragments of resin.
f) Acrylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyano-
acrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives. (reference)

5) Others
a) Do not expose to strong light (sun rays) for long periods, color filters will be discolored. When high
luminance objects are imaged with the exposure level control by electronic-iris, the luminance of the
image-plane may become excessive and discolor of the color filter will possibly be accelerated. In such a
case, it is advisable that taking-lens with the automatic-iris and closing of the shutter during the power-off
mode should be properly arranged. For continuous using under cruel condition exceeding the normal
using condition, consult our company.
b) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or
usage in such conditions.
c) The brown stain may be seen on the bottom or side of the package. But this does not affect the CCD
characteristics.
d) This package has 2 kinds of internal structure. However, their package outline, optical size, and strength
are the same.

Structure A Structure B

Package

Chip

Metal plate
(lead frame)

Cross section of
lead frame

The cross section of lead frame can be seen on the side of the package for structure A.

– 17 –
 Package Outline Unit: mm
16 pin DIP (450mil)
A
6.1 D

0˚ to 9˚
9 16

~
2.5
C

9.5
11.43
2.5

8.4
11.4 ± 0.1
V

5.7
2-R0.5

~
H

2.5
1.2 10.3 8 11.6 1

0.5
0.25
12.2 ± 0.1
B'
9.2 2.5

3.35 ± 0.15

1.2
1. “A” is the center of the effective image area.
~

– 18 –
2. The two points “B” of the package are the horizontal reference.

3.1
The point “B'” of the package is the vertical reference.

3. The bottom “C” of the package, and the top of the cover glass “D”
are the height reference.
0.69 0.3

1.27
4. The center of the effective image area relative to “B” and “B'”
(For the first pin only) 1.27 0.46 is (H, V) = (6.1, 5.7) ± 0.15mm.

3.5 ± 0.3
0.3 M
5. The rotation angle of the effective image area relative to H and V is ± 1˚.

6. The height from the bottom “C” to the effective image area is 1.41 ± 0.10mm.
PACKAGE STRUCTURE The height from the top of the cover glass “D” to the effective image area is 1.94 ± 0.15mm.
PACKAGE MATERIAL Plastic 7. The tilt of the effective image area relative to the bottom “C” is less than 50µm.
LEAD TREATMENT
The tilt of the effective image area relative to the top “D” of the cover glass is less than 50µm.
GOLD PLATING
LEAD MATERIAL 42 ALLOY 8. The thickness of the cover glass is 0.75mm, and the refractive index is 1.5.

PACKAGE MASS 0.90g 9. The notches on the bottom of the package are used only for directional index, they must
not be used for reference of fixing.
DRAWING NUMBER AS-C2.2-01(E)

Sony Corporation
ICX409AK