Unit-VI
Digital Registers
Flip-flop is a 1 bit memory cell which can be used for storing the digital data. To increase the
storage capacity in terms of number of bits, we have to use a group of flip-flop. Such a group
of flip-flop is known as a Register. The n-bit register will consist of n number of flip-flop and
it is capable of storing an n-bit word.
The binary data in a register can be moved within the register from one flip-flop to another.
The registers that allow such data transfers are called as shift registers. There are four mode
of opearation of a shift register.
Serial Input Serial Output
Serial Input Parallel Output
Parallel Input Serial Output
Parallel Input Parallel Output
Serial Input Serial Output
Let all the flip-flop be initially in the reset condition i.e. Q3 = Q2 = Q1 = Q0 = 0. If we entry of a
four bit binary number 1 1 1 1 into the register. When this is to be done, this number should
be applied to Din bit by with the LSB bit applied first. The D input of FF-3 i.e. D3 is connected
to serial data input Din. Output of FF-3 i.e. Q3 is connected to the input of the next flip-flop
i.e. D2 and so on.
Block Diagram
Operation
Before application of clock signal let Q3 Q2 Q1 Q0 = 0000 and apply LSB bit of the number to
be entered to Din. So Din=D3=1. Apply the clock. On the first falling edge of clock, the FF-3 is
set, and stored word in the register is Q3 Q2 Q1 Q0 = 1000.
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Apply the next bit to Din. So Din=1. As soon as the next negative edge of the clock hits, FF-2
will set and the stored word change to Q3 Q2 Q1 Q0 = 1100.
Apply the next bit to be stored i.e. 1 to Din. Apply the clock pulse. As soon as the third
negative clock edge hits, FF-1 will be set and output will be modified to Q3 Q2 Q1 Q0 = 1110.
Similarly with Din=1 and with the fourth negative clock edge arriving, the stored word in the
register is Q3 Q2 Q1 Q0 = 1111.
Truth Table
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Waveforms
Serial Input Parallel Output
In such types of operations, the data is entered serially and taken out in parallel
fashion.
Data is loaded bit by bit. The outputs are disabled as long as the data is loading.
As soon as the data loading gets completed, all the flip-flops contain their required
data, the outputs are enabled so that all the loaded data is made available over all
the output lines at the same time.
4 clock cycles are required to load a four bit word. Hence the speed of operation of
SIPO mode is same as that of SISO mode.
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Block Diagram
Parallel Input Serial Output (PISO)
Data bits are entered in parallel fashion.
The circuit shown below is a four bit parallel input serial output register.
Output of previous Flip Flop is connected to the input of the next one via a
combinational circuit.
The binary input word B0,B1,B2,B3 is applied though the same combinational circuit.
There are two modes in which this circuit can work namely shift mode or load mode.
Load mode
When the shift/load bar line is low (0), the AND gate 2,4 and 6 become active. They will pass
B1,B2,B3 bits to the corresponding flip-flops. On the low going edge of clock, the binary input
B0,B1,B2,B3 will get loaded into the corresponding flip-flops. Thus parallel loading takes
place.
Shift mode
When the shift/load bar line is low (1), the AND gate 2,4 and 6 become inactive. Hence the
parallel loading of the data becomes impossible. But the AND gate 1,3 and 5 become active.
Therefore the shifting of data from left to right bit by bit on application of clock pulses. Thus
the parallel in serial out operation take place.
Block Diagram
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Parallel Input Parallel Output (PIPO)
In this mode, the 4 bit binary input B0,B1,B2,B3 is applied to the data inputs D0,D1,D2,D3
respectively of the four flip-flops. As soon as a negative clock edge is applied, the input
binary bits will be loaded into the flip-flops simultaneously. The loaded bits will appear
simultaneously to the output side. Only clock pulse is essential to load all the bits.
Block Diagram
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Bidirectional Shift Register
If a binary number is shifted left by one position then it is equivalent to multiplying
the original number by 2. Similarly if a binary number is shifted right by one position
then it is equivalent to dividing the original number by 2.
Hence if we want to use the shift register to multiply and divide the given binary
number, then we should be able to move the data in either left or right direction.
Such a register is called as a bi-directional register. A four bit bi-directional shift
register is shown in fig.
There are two serial inputs namely the serial right shift data input DR and the serial
left shift data input DL along with a mode select input (M).
Block Diagram
Operation
S.N. Condition Operation
If M = 1, then the AND gates 1,3,5 and 7 are enable whereas
the remaining AND gates 2,4,6 and 8 will be disabled.
With M = 1 : Shift
1 The data at DR is shifted to right bit by bit from FF-3 to FF-0
right operation
on the application of clock pulses. Thus with M = 1 we get
the serial right shift operation.
When the mode control M is connected to 0 then the AND
gates 2,4,6 and 8 are enabled while 1,3,5 and 7 are disabled.
With M = 0 : Shift
2 The data at DL is shifted left bit by bit from FF-0 to FF-3 on
left operation
the application of clock pulses. Thus with M = 0 we get the
serial right shift operation.
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Universal Shift Register
A shift register which can shift the data in only one direction is called a uni-directional shift
register. A shift register which can shift the data in both directions is called a bi-directional
shift register. Applying the same logic, a shift register which can shift the data in both
directions as well as load it parallely, then it is known as a universal shift register. The shift
register is capable of performing the following operation
Parallel loading
Lift shifting
Right shifting
The mode control input is connected to logic 1 for parallel loading operation whereas it is
connected to 0 for serial shifting. With mode control pin connected to ground, the universal
shift register acts as a bi-directional register. For serial left operation, the input is applied to
the serial input which goes to AND gate-1 shown in figure. Whereas for the shift right
operation, the serial input is applied to D input.
Block Diagram
Digital Counters
Counter is a sequential circuit. A digital circuit which is used for a counting pulses is known
counter. Counter is the widest application of flip-flops. It is a group of flip-flops with a clock
signal applied. Counters are of two types.
Asynchronous or ripple counters
Synchronous counters.
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Asynchronous or ripple counters
The logic diagram of a 2-bit ripple up counter is shown in figure. The toggle(T) flip-flop are
being used. But we can use the JK flip-flop also with J and K connected permanently to logic
1. External clock is applied to the clock input of flip-flop A and QA output is applied to the
clock input of the next flip-flop i.e. FF-B.
Logical Diagram
Operation
S.N. Condition Operation
Initially let both the FFs be in
1 QBQA = 00 ............... initially
the reset state
As soon as the first negative clock edge is applied,
FF-A will toggle and QA will be equal to 1.
QA is connected to clock input of FF-B. Since QA has
changed from 0 to 1, it is treated as the positive
2 After 1st negative clock edge clock edge by FF-B. There is no change in QB
because FF-B is a negative edge triggered FF.
QBQA = 01 ............... After the first clock pulse
On the arrival of second negative clock edge, FF-A
toggles again and QA = 0.
The change in QA acts as a negative clock edge for
After 2nd negative clock
3 FF-B. So it will also toggle, and QB will be 1.
edge
QBQA = 10 ............... After the second clock pulse
On the arrival of 3rd negative clock edge, FF-A
4 After 3rd negative clock edge
toggles again and QA become 1 from 0.
Since this is a positive going change,FF-B does not
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respond to it and remains inactive. So QB does not
change and continues to be equal to 1.
QBQA = 11 ............... After the third clock pulse
On the arrival of 4th negative clock edge, FF-A
toggles again and QA become 1 from 0.
This negative change in QA acts as clock pulse for
5 After 4th negative clock edge FF-B. Hence it toggles to change QB from 1 to 0.
QBQA = 00 ............... After the fourth clock pulse
Truth Table
Synchronous counters
If the "clock" pulses are applied to all the flip-flops in a counter simultaneously, then such a
counter is called as synchronous counter.
2- bit Synchronous up counter
The JA and KA inputs of FF-A are tied to logic 1. So FF-A will work as a toggle flip-flop. The JB
and KB inputs are connected to QA.
Logical Diagram
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Operation
S.N. Condition Operation
Initially let both the FFs be in
1 QBQA = 00 ............... initially
the reset state
As soon as the first negative clock edge is applied,
FF-A will toggle and QA will change from 0 to 1.
But at the instant of application of negative clock
edge, QA ,JB = KB =0 Hence FF-B will not change its
2 After 1st negative clock edge
state. So QB will remain 0.
QBQA = 01 ............... After the first clock pulse
On the arrival of second negative clock edge, FF-A
toggles again and QA change from 1 to 0.
After 2nd negative clock But at this instant QA was 1. So JB = KB=1 and FF-B
3 will toggle. Hence QB changes from 0 to 1.
edge
QBQA = 10 ............... After the second clock pulse
On application of the third falling clock edge, FF-A
will toggle from 0 to 1 but there is no change of
state for FF-B.
4 After 3rd negative clock edge
QBQA = 11 ............... After the third clock pulse
On application of the next clock pulse, QA will
5 After 4th negative clock edge change from 1 to 0 as QB will also change from 1 to
0.
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QBQA = 00 ............... After the fourth clock pulse
Classification of counters
Depending on the way in which the counting progresses, the synchronous or asynchronous
counters are classified as follows.
Up counters
Down counters and Up/Down counters
UP/DOWN Counter
In the up/down counter, when up counter and down counter combined together to obtain
an UP/DOWN counter. A mode control (M) input is also provided to select either up or
down mode. A combinational circuit is required to be designed and used between each pair
of flip-flop in order to achieve the up/down operation.
Type of up/down counters
UP/DOWN ripple counters
UP/DOWN synchronous counters
UP/DOWN Ripple Counters
In the UP/DOWN ripple counter all the FFs operate in the toggle mode. So either T flip-flops
or JK flip-flops are to be used. The LSB flip-flop receives clock directly. But the clock to every
other FF is obtained from (Q = Q bar) output of the previous FF.
UP counting mode (M=0) - The Q output of the preceding FF is connected to the
clock of the next stage if up counting is to be achieved. For this mode, the mode
select input M is at logic 0 (M=0).
DOWN counting mode (M=1) - If M =1, then the Q bar output of the preceding FF is
connected to the next FF. This will operate the counter in the counting mode.
Example
3- bit binary up/down ripple counter.
3-bit : hence three FFs are required.
UP/DOWN : So a mode control input is essential.
For a ripple up counter, the Q output of preceding FF is connected to the clock input
of the next one.
For a ripple up counter, the Q output of preceding FF is connected to the clock input
of the next one.
For a ripple down counter, the Q bar output of preceding FF is connected to the
clock input of the next one.
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Let the selection of Q and Q bar output of the preceding FF be controlled by the
mode control input M such that, If M = 0, UP counting. So connect Q to CLK. If M = 1,
DOWN counting. So connect Q bar to CLK
Block Diagram
Truth Table
Operation
S.N. Condition Operation
If M = 0 and M bar = 1, then the AND gates 1 and 3
in fig. will be enabled whereas the AND gates 2 and
4 will be disabled.
Case 1: With M = 0 (Up Hence QA gets connected to the clock input of FF-B
1
counting mode) and QB gets connected to the clock input of FF-C.
These connections are same as those for the normal
up counter. Thus with M = 0 the circuit work as an
up counter.
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If M = 1, then AND gates 2 and 4 in fig. are enabled
whereas the AND gates 1 and 3 are disabled.
Hence QA bar gets connected to the clock input of
Case 2: With M = 1 (Down FF-B and QB bar gets connected to the clock input of
2
counting mode) FF-C.
These connections will produce a down counter.
Thus with M = 1 the circuit works as a down
counter.
Modulus Counter (MOD-N Counter)
The 2-bit ripple counter is called as MOD-4 counter and 3-bit ripple counter is called as
MOD-8 counter. So in general, an n-bit ripple counter is called as modulo-N counter.
Where,MOD number = 2n
Type of modulus
2-bit up or down (MOD-4)
3-bit up or down (MOD-8)
4-bit up or down (MOD-16)
Application of the counters
Frequency counters
Digital clock
Time measurement
A to D converter
Frequency divider circuits
Digital triangular wave generator
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